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cleanup + work on frame lenght

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spi
polymurph 3 years ago
parent 0b46bcc24a
commit cde2895fff
3 changed files with 51 additions and 75 deletions
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25
ked/csl/interfaces/spi.h
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@ -23,32 +23,42 @@ extern "C" {
#include "pin.h"
#include "spi.h"
#include <stdint.h>
#include "hardwareDescription.h"
// TODO: when everything worksmove this into imp.spi.c
#include "hardwareDescription.h"
#define SPI_BASE ((SPI_TypeDef *)spiBase_Addr_List[spi_hw_ch])
/*! Enum of possible States*/
typedef enum{
SPI_SLAVE,
SPI_MASTER
} spi_mode_t;
/* Enum of clock polarities*/
typedef enum{
SPI_NONINVERTED,
SPI_INVERTED
}spi_clkPol_t;
/*! Enum of phases*/
typedef enum{
SPI_CAPTURE_ON_FIRST_CLK_TRANSITION,
SPI_CAPTURE_ON_SECCOND_CLK_TRANSITION
} spi_phase_t;
/*! Enum of frame formats*/
typedef enum{
SPI_MSB_FIRST,
SPI_LSB_FIRST
}spi_framef_t;
/*! Enum of frame lenghts*/
typedef enum{
SPI_FRAME_LENGTH_8BIT,
SPI_FRAME_LENGTH_16BIT
}spi_framel_t;
/*! Enum of communication mode*/
typedef enum{
SPI_DOUPLEX,
SPI_SIMPLEX
@ -274,6 +284,16 @@ void spiSetPhase(
spi_phase_t spiGetPhase(
spiCH_t spi_hw_ch);
/**
* @brief Set frame length
* one can choose between 4/8/16 bits. For devices that not support a given frame length an error
* will be generated.
* @param spi_hw_ch SPI hardware channel
* @param framel Frame length
*/
void spiSetBitFrameLength(
spiCH_t spi_hw_ch,
spi_framel_t framel);
/**
* @brief Set SPI frame format
@ -283,7 +303,6 @@ spi_phase_t spiGetPhase(
void spiSetFrameFormat(
spiCH_t spi_hw_ch,
spi_framef_t framef);
/**
* @brief Get SPI frame format
* @param spi_hw_ch SPI hardware channel

16
ked/csl/stm32f042/Src/imp_spi.c
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@ -57,6 +57,22 @@ void spiSetPhase(spiCH_t spi_hw_ch, spi_phase_t phase)
SPI_BASE->CR1 |= phase << SPI_CR1_CPHA_Pos;
}
void spiSetBitFrameLength(spiCH_t spi_hw_ch, spi_framel_t framel)
{
SPI_BASE->CR2 &= ~(SPI_CR2_FRXTH | SPI_CR2_DS);
// using p.974 as example
if(framel == SPI_FRAME_LENGTH_8BIT) {
// set FIFO reception threshold to 8 bit
SPI_BASE->CR2 |= SPI_CR2_FRXTH;
// set transfer lwnght to 8 bit
SPI_BASE->CR2 |= SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2;
return;
}
SPI_BASE->CR2 |= SPI_CR2_DS;
}
void spiSetFrameFormat(spiCH_t spi_hw_ch, spi_framef_t framef)
{
// reset

85
ked/drivers/spi.c
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@ -11,94 +11,36 @@ void spiInitMaster(spiCH_t spi_hw_ch,
{
// TODO: step by step implementation
#if 0
RCC->APB2ENR |= (1<<12); // Enable SPI1 CLock
SPI1->CR1 |= (1<<0)|(1<<1); // CPOL=1, CPHA=1
//SPI_BASE->CR1 |= (1<<0) | (1 << 1);
SPI1->CR1 |= (1<<2); // Master Mode
//SPI_BASE->CR1 |= (1 << 2);
SPI1->CR1 |= (3<<3); // BR[2:0] = 011: fPCLK/16, PCLK2 = 80MHz, SPI clk = 5MHz
//SPI_BASE-> CR1 |= (3<<3);
SPI1->CR1 &= ~(1<<7); // LSBFIRST = 0, MSB first
//SPI_BASE->CR1 &= ~(1<<7);
SPI1->CR1 |= (1<<8) | (1<<9); // SSM=1, SSi=1 -> Software Slave Management
//SPI_BASE->CR1 |= (1 << 8) | (1 << 9);
SPI1->CR1 &= ~(1<<10); // RXONLY = 0, full-duplex
//SPI_BASE->CR1 &= ~(1<<10);
SPI1->CR1 &= ~(1<<11); // CRCL =0, 8 bit data
//SPI_BASE->CR1 &= ~(1 << 11);
#endif
#if 1
//RCC->APB2ENR |= (1<<12); // Enable SPI1 CLock
spiEnableBus(spi_hw_ch);
//SPI1->CR1 |= (1<<0)|(1<<1); // CPOL=1, CPHA=1
//SPI_BASE->CR1 |= (1<<0) | (1 << 1);
spiSetPolarity(spi_hw_ch,clockPolarity);
spiSetPhase(spi_hw_ch,phase);
//SPI1->CR1 |= (1<<2); // Master Mode
//SPI_BASE->CR1 |= (1 << 2);
spiSetMode(spi_hw_ch, SPI_MASTER);
//SPI1->CR1 |= (3<<3); // BR[2:0] = 011: fPCLK/16, PCLK2 = 80MHz, SPI clk = 5MHz
//SPI_BASE-> CR1 |= (3<<3);
spiSetClockPrescaler(spi_hw_ch, prescaler);
//SPI1->CR1 &= ~(1<<7); // LSBFIRST = 0, MSB first
//SPI_BASE->CR1 &= ~(1<<7);
spiSetFrameFormat(spi_hw_ch,frameFormat);
// TODO: find out what settings shouldbe made for theSlave Management
//SPI1->CR1 |= (1<<8) | (1<<9); // SSM=1, SSi=1 -> Software Slave Management
//SPI_BASE->CR1 |= (1 << 8) | (1 << 9);
//spiSetSoftwareSlaveManagement(spi_hw_ch,1);
//spiSetInternalSlaveSelect(spi_hw_ch,0);
//SPI_BASE->CR1 |= (1 << 8) | (1 << 9);
spiSetSoftwareSlaveManagement(spi_hw_ch,1);
spiSetInternalSlaveSelect(spi_hw_ch,0);
//SPI1->CR1 &= ~(1<<10); // RXONLY = 0, full-duplex
//SPI_BASE->CR1 &= ~(1<<10);
spiSetComMode(spi_hw_ch, comMode);
//SPI1->CR1 &= ~(1<<11); // CRCL =0, 8 bit data
SPI_BASE->CR1 |= SPI_CR1_CRCL;
SPI_BASE->CR2 = SPI_CR2_SSOE | SPI_CR2_RXNEIE | SPI_CR2_FRXTH | SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2;
//spiDissable(spi_hw_ch);
#endif
//SPI1->CR2 = 0;
//SPI_BASE->CR2 = 0;
/*
spiReset(spi_ch);
//TODO: test this for relevance of functionality. Leave it away, compilw it and run it
//SPI1->CR1 &= ~(1<<11); // CRCL =0, 8 bit data
//SPI_BASE->CR1 |= SPI_CR1_CRCL;
spiEnableBus(spi_ch);
spiSetClockPrescaler(spi_hw_ch, prescaler);
spiSetPolarity(spi_ch, clockPolarity);
spiSetBitFrameLength(spi_hw_ch, SPI_FRAME_LENGTH_8BIT);
spiSetMode(spi_ch, mode);
spiSetPhase(spi_ch, phase);
spiSetFrameFormat(spi_ch, frameFormat);
spiSetClockPrescaler(spi_ch, prescaler);
spiDissable(spi_hw_ch);
*/
// TODO: find out what SSOE does
// TODO: find out what FRXTH does
SPI_BASE->CR2 |= SPI_CR2_SSOE;// | SPI_CR2_FRXTH;// | SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2;
}
void spiSetupCH(spi_ch_t *ch, spiCH_t spi_hw_ch, pinNo_t chipselectPin)
@ -108,8 +50,7 @@ void spiSetupCH(spi_ch_t *ch, spiCH_t spi_hw_ch, pinNo_t chipselectPin)
pinWrite(chipselectPin, 0);
}
uint8_t spiReadReg(spi_ch_t *spi_ch,
uint8_t reg_address) {
uint8_t spiReadReg(spi_ch_t *spi_ch, uint8_t reg_address) {
uint8_t buf;
// select target device

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