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Linux/stm/Debug/g4_i2c.list

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g4_i2c.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001d8 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00002d08 080001d8 080001d8 000101d8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000040 08002ee0 08002ee0 00012ee0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08002f20 08002f20 0002000c 2**0
CONTENTS
4 .ARM 00000008 08002f20 08002f20 00012f20 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08002f28 08002f28 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08002f28 08002f28 00012f28 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08002f2c 08002f2c 00012f2c 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08002f30 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000000fc 2000000c 08002f3c 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000600 20000108 08002f3c 00020108 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .debug_info 0000f181 00000000 00000000 0002003c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000020eb 00000000 00000000 0002f1bd 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000c70 00000000 00000000 000312a8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00000b88 00000000 00000000 00031f18 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0002469e 00000000 00000000 00032aa0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0000ec59 00000000 00000000 0005713e 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000e5851 00000000 00000000 00065d97 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000053 00000000 00000000 0014b5e8 2**0
CONTENTS, READONLY
20 .debug_frame 00003248 00000000 00000000 0014b63c 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001d8 <__do_global_dtors_aux>:
80001d8: b510 push {r4, lr}
80001da: 4c05 ldr r4, [pc, #20] ; (80001f0 <__do_global_dtors_aux+0x18>)
80001dc: 7823 ldrb r3, [r4, #0]
80001de: b933 cbnz r3, 80001ee <__do_global_dtors_aux+0x16>
80001e0: 4b04 ldr r3, [pc, #16] ; (80001f4 <__do_global_dtors_aux+0x1c>)
80001e2: b113 cbz r3, 80001ea <__do_global_dtors_aux+0x12>
80001e4: 4804 ldr r0, [pc, #16] ; (80001f8 <__do_global_dtors_aux+0x20>)
80001e6: f3af 8000 nop.w
80001ea: 2301 movs r3, #1
80001ec: 7023 strb r3, [r4, #0]
80001ee: bd10 pop {r4, pc}
80001f0: 2000000c .word 0x2000000c
80001f4: 00000000 .word 0x00000000
80001f8: 08002ec8 .word 0x08002ec8
080001fc <frame_dummy>:
80001fc: b508 push {r3, lr}
80001fe: 4b03 ldr r3, [pc, #12] ; (800020c <frame_dummy+0x10>)
8000200: b11b cbz r3, 800020a <frame_dummy+0xe>
8000202: 4903 ldr r1, [pc, #12] ; (8000210 <frame_dummy+0x14>)
8000204: 4803 ldr r0, [pc, #12] ; (8000214 <frame_dummy+0x18>)
8000206: f3af 8000 nop.w
800020a: bd08 pop {r3, pc}
800020c: 00000000 .word 0x00000000
8000210: 20000010 .word 0x20000010
8000214: 08002ec8 .word 0x08002ec8
08000218 <__aeabi_uldivmod>:
8000218: b953 cbnz r3, 8000230 <__aeabi_uldivmod+0x18>
800021a: b94a cbnz r2, 8000230 <__aeabi_uldivmod+0x18>
800021c: 2900 cmp r1, #0
800021e: bf08 it eq
8000220: 2800 cmpeq r0, #0
8000222: bf1c itt ne
8000224: f04f 31ff movne.w r1, #4294967295
8000228: f04f 30ff movne.w r0, #4294967295
800022c: f000 b96e b.w 800050c <__aeabi_idiv0>
8000230: f1ad 0c08 sub.w ip, sp, #8
8000234: e96d ce04 strd ip, lr, [sp, #-16]!
8000238: f000 f806 bl 8000248 <__udivmoddi4>
800023c: f8dd e004 ldr.w lr, [sp, #4]
8000240: e9dd 2302 ldrd r2, r3, [sp, #8]
8000244: b004 add sp, #16
8000246: 4770 bx lr
08000248 <__udivmoddi4>:
8000248: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800024c: 9d08 ldr r5, [sp, #32]
800024e: 4604 mov r4, r0
8000250: 468c mov ip, r1
8000252: 2b00 cmp r3, #0
8000254: f040 8083 bne.w 800035e <__udivmoddi4+0x116>
8000258: 428a cmp r2, r1
800025a: 4617 mov r7, r2
800025c: d947 bls.n 80002ee <__udivmoddi4+0xa6>
800025e: fab2 f282 clz r2, r2
8000262: b142 cbz r2, 8000276 <__udivmoddi4+0x2e>
8000264: f1c2 0020 rsb r0, r2, #32
8000268: fa24 f000 lsr.w r0, r4, r0
800026c: 4091 lsls r1, r2
800026e: 4097 lsls r7, r2
8000270: ea40 0c01 orr.w ip, r0, r1
8000274: 4094 lsls r4, r2
8000276: ea4f 4817 mov.w r8, r7, lsr #16
800027a: 0c23 lsrs r3, r4, #16
800027c: fbbc f6f8 udiv r6, ip, r8
8000280: fa1f fe87 uxth.w lr, r7
8000284: fb08 c116 mls r1, r8, r6, ip
8000288: ea43 4301 orr.w r3, r3, r1, lsl #16
800028c: fb06 f10e mul.w r1, r6, lr
8000290: 4299 cmp r1, r3
8000292: d909 bls.n 80002a8 <__udivmoddi4+0x60>
8000294: 18fb adds r3, r7, r3
8000296: f106 30ff add.w r0, r6, #4294967295
800029a: f080 8119 bcs.w 80004d0 <__udivmoddi4+0x288>
800029e: 4299 cmp r1, r3
80002a0: f240 8116 bls.w 80004d0 <__udivmoddi4+0x288>
80002a4: 3e02 subs r6, #2
80002a6: 443b add r3, r7
80002a8: 1a5b subs r3, r3, r1
80002aa: b2a4 uxth r4, r4
80002ac: fbb3 f0f8 udiv r0, r3, r8
80002b0: fb08 3310 mls r3, r8, r0, r3
80002b4: ea44 4403 orr.w r4, r4, r3, lsl #16
80002b8: fb00 fe0e mul.w lr, r0, lr
80002bc: 45a6 cmp lr, r4
80002be: d909 bls.n 80002d4 <__udivmoddi4+0x8c>
80002c0: 193c adds r4, r7, r4
80002c2: f100 33ff add.w r3, r0, #4294967295
80002c6: f080 8105 bcs.w 80004d4 <__udivmoddi4+0x28c>
80002ca: 45a6 cmp lr, r4
80002cc: f240 8102 bls.w 80004d4 <__udivmoddi4+0x28c>
80002d0: 3802 subs r0, #2
80002d2: 443c add r4, r7
80002d4: ea40 4006 orr.w r0, r0, r6, lsl #16
80002d8: eba4 040e sub.w r4, r4, lr
80002dc: 2600 movs r6, #0
80002de: b11d cbz r5, 80002e8 <__udivmoddi4+0xa0>
80002e0: 40d4 lsrs r4, r2
80002e2: 2300 movs r3, #0
80002e4: e9c5 4300 strd r4, r3, [r5]
80002e8: 4631 mov r1, r6
80002ea: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002ee: b902 cbnz r2, 80002f2 <__udivmoddi4+0xaa>
80002f0: deff udf #255 ; 0xff
80002f2: fab2 f282 clz r2, r2
80002f6: 2a00 cmp r2, #0
80002f8: d150 bne.n 800039c <__udivmoddi4+0x154>
80002fa: 1bcb subs r3, r1, r7
80002fc: ea4f 4e17 mov.w lr, r7, lsr #16
8000300: fa1f f887 uxth.w r8, r7
8000304: 2601 movs r6, #1
8000306: fbb3 fcfe udiv ip, r3, lr
800030a: 0c21 lsrs r1, r4, #16
800030c: fb0e 331c mls r3, lr, ip, r3
8000310: ea41 4103 orr.w r1, r1, r3, lsl #16
8000314: fb08 f30c mul.w r3, r8, ip
8000318: 428b cmp r3, r1
800031a: d907 bls.n 800032c <__udivmoddi4+0xe4>
800031c: 1879 adds r1, r7, r1
800031e: f10c 30ff add.w r0, ip, #4294967295
8000322: d202 bcs.n 800032a <__udivmoddi4+0xe2>
8000324: 428b cmp r3, r1
8000326: f200 80e9 bhi.w 80004fc <__udivmoddi4+0x2b4>
800032a: 4684 mov ip, r0
800032c: 1ac9 subs r1, r1, r3
800032e: b2a3 uxth r3, r4
8000330: fbb1 f0fe udiv r0, r1, lr
8000334: fb0e 1110 mls r1, lr, r0, r1
8000338: ea43 4401 orr.w r4, r3, r1, lsl #16
800033c: fb08 f800 mul.w r8, r8, r0
8000340: 45a0 cmp r8, r4
8000342: d907 bls.n 8000354 <__udivmoddi4+0x10c>
8000344: 193c adds r4, r7, r4
8000346: f100 33ff add.w r3, r0, #4294967295
800034a: d202 bcs.n 8000352 <__udivmoddi4+0x10a>
800034c: 45a0 cmp r8, r4
800034e: f200 80d9 bhi.w 8000504 <__udivmoddi4+0x2bc>
8000352: 4618 mov r0, r3
8000354: eba4 0408 sub.w r4, r4, r8
8000358: ea40 400c orr.w r0, r0, ip, lsl #16
800035c: e7bf b.n 80002de <__udivmoddi4+0x96>
800035e: 428b cmp r3, r1
8000360: d909 bls.n 8000376 <__udivmoddi4+0x12e>
8000362: 2d00 cmp r5, #0
8000364: f000 80b1 beq.w 80004ca <__udivmoddi4+0x282>
8000368: 2600 movs r6, #0
800036a: e9c5 0100 strd r0, r1, [r5]
800036e: 4630 mov r0, r6
8000370: 4631 mov r1, r6
8000372: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000376: fab3 f683 clz r6, r3
800037a: 2e00 cmp r6, #0
800037c: d14a bne.n 8000414 <__udivmoddi4+0x1cc>
800037e: 428b cmp r3, r1
8000380: d302 bcc.n 8000388 <__udivmoddi4+0x140>
8000382: 4282 cmp r2, r0
8000384: f200 80b8 bhi.w 80004f8 <__udivmoddi4+0x2b0>
8000388: 1a84 subs r4, r0, r2
800038a: eb61 0103 sbc.w r1, r1, r3
800038e: 2001 movs r0, #1
8000390: 468c mov ip, r1
8000392: 2d00 cmp r5, #0
8000394: d0a8 beq.n 80002e8 <__udivmoddi4+0xa0>
8000396: e9c5 4c00 strd r4, ip, [r5]
800039a: e7a5 b.n 80002e8 <__udivmoddi4+0xa0>
800039c: f1c2 0320 rsb r3, r2, #32
80003a0: fa20 f603 lsr.w r6, r0, r3
80003a4: 4097 lsls r7, r2
80003a6: fa01 f002 lsl.w r0, r1, r2
80003aa: ea4f 4e17 mov.w lr, r7, lsr #16
80003ae: 40d9 lsrs r1, r3
80003b0: 4330 orrs r0, r6
80003b2: 0c03 lsrs r3, r0, #16
80003b4: fbb1 f6fe udiv r6, r1, lr
80003b8: fa1f f887 uxth.w r8, r7
80003bc: fb0e 1116 mls r1, lr, r6, r1
80003c0: ea43 4301 orr.w r3, r3, r1, lsl #16
80003c4: fb06 f108 mul.w r1, r6, r8
80003c8: 4299 cmp r1, r3
80003ca: fa04 f402 lsl.w r4, r4, r2
80003ce: d909 bls.n 80003e4 <__udivmoddi4+0x19c>
80003d0: 18fb adds r3, r7, r3
80003d2: f106 3cff add.w ip, r6, #4294967295
80003d6: f080 808d bcs.w 80004f4 <__udivmoddi4+0x2ac>
80003da: 4299 cmp r1, r3
80003dc: f240 808a bls.w 80004f4 <__udivmoddi4+0x2ac>
80003e0: 3e02 subs r6, #2
80003e2: 443b add r3, r7
80003e4: 1a5b subs r3, r3, r1
80003e6: b281 uxth r1, r0
80003e8: fbb3 f0fe udiv r0, r3, lr
80003ec: fb0e 3310 mls r3, lr, r0, r3
80003f0: ea41 4103 orr.w r1, r1, r3, lsl #16
80003f4: fb00 f308 mul.w r3, r0, r8
80003f8: 428b cmp r3, r1
80003fa: d907 bls.n 800040c <__udivmoddi4+0x1c4>
80003fc: 1879 adds r1, r7, r1
80003fe: f100 3cff add.w ip, r0, #4294967295
8000402: d273 bcs.n 80004ec <__udivmoddi4+0x2a4>
8000404: 428b cmp r3, r1
8000406: d971 bls.n 80004ec <__udivmoddi4+0x2a4>
8000408: 3802 subs r0, #2
800040a: 4439 add r1, r7
800040c: 1acb subs r3, r1, r3
800040e: ea40 4606 orr.w r6, r0, r6, lsl #16
8000412: e778 b.n 8000306 <__udivmoddi4+0xbe>
8000414: f1c6 0c20 rsb ip, r6, #32
8000418: fa03 f406 lsl.w r4, r3, r6
800041c: fa22 f30c lsr.w r3, r2, ip
8000420: 431c orrs r4, r3
8000422: fa20 f70c lsr.w r7, r0, ip
8000426: fa01 f306 lsl.w r3, r1, r6
800042a: ea4f 4e14 mov.w lr, r4, lsr #16
800042e: fa21 f10c lsr.w r1, r1, ip
8000432: 431f orrs r7, r3
8000434: 0c3b lsrs r3, r7, #16
8000436: fbb1 f9fe udiv r9, r1, lr
800043a: fa1f f884 uxth.w r8, r4
800043e: fb0e 1119 mls r1, lr, r9, r1
8000442: ea43 4101 orr.w r1, r3, r1, lsl #16
8000446: fb09 fa08 mul.w sl, r9, r8
800044a: 458a cmp sl, r1
800044c: fa02 f206 lsl.w r2, r2, r6
8000450: fa00 f306 lsl.w r3, r0, r6
8000454: d908 bls.n 8000468 <__udivmoddi4+0x220>
8000456: 1861 adds r1, r4, r1
8000458: f109 30ff add.w r0, r9, #4294967295
800045c: d248 bcs.n 80004f0 <__udivmoddi4+0x2a8>
800045e: 458a cmp sl, r1
8000460: d946 bls.n 80004f0 <__udivmoddi4+0x2a8>
8000462: f1a9 0902 sub.w r9, r9, #2
8000466: 4421 add r1, r4
8000468: eba1 010a sub.w r1, r1, sl
800046c: b2bf uxth r7, r7
800046e: fbb1 f0fe udiv r0, r1, lr
8000472: fb0e 1110 mls r1, lr, r0, r1
8000476: ea47 4701 orr.w r7, r7, r1, lsl #16
800047a: fb00 f808 mul.w r8, r0, r8
800047e: 45b8 cmp r8, r7
8000480: d907 bls.n 8000492 <__udivmoddi4+0x24a>
8000482: 19e7 adds r7, r4, r7
8000484: f100 31ff add.w r1, r0, #4294967295
8000488: d22e bcs.n 80004e8 <__udivmoddi4+0x2a0>
800048a: 45b8 cmp r8, r7
800048c: d92c bls.n 80004e8 <__udivmoddi4+0x2a0>
800048e: 3802 subs r0, #2
8000490: 4427 add r7, r4
8000492: ea40 4009 orr.w r0, r0, r9, lsl #16
8000496: eba7 0708 sub.w r7, r7, r8
800049a: fba0 8902 umull r8, r9, r0, r2
800049e: 454f cmp r7, r9
80004a0: 46c6 mov lr, r8
80004a2: 4649 mov r1, r9
80004a4: d31a bcc.n 80004dc <__udivmoddi4+0x294>
80004a6: d017 beq.n 80004d8 <__udivmoddi4+0x290>
80004a8: b15d cbz r5, 80004c2 <__udivmoddi4+0x27a>
80004aa: ebb3 020e subs.w r2, r3, lr
80004ae: eb67 0701 sbc.w r7, r7, r1
80004b2: fa07 fc0c lsl.w ip, r7, ip
80004b6: 40f2 lsrs r2, r6
80004b8: ea4c 0202 orr.w r2, ip, r2
80004bc: 40f7 lsrs r7, r6
80004be: e9c5 2700 strd r2, r7, [r5]
80004c2: 2600 movs r6, #0
80004c4: 4631 mov r1, r6
80004c6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80004ca: 462e mov r6, r5
80004cc: 4628 mov r0, r5
80004ce: e70b b.n 80002e8 <__udivmoddi4+0xa0>
80004d0: 4606 mov r6, r0
80004d2: e6e9 b.n 80002a8 <__udivmoddi4+0x60>
80004d4: 4618 mov r0, r3
80004d6: e6fd b.n 80002d4 <__udivmoddi4+0x8c>
80004d8: 4543 cmp r3, r8
80004da: d2e5 bcs.n 80004a8 <__udivmoddi4+0x260>
80004dc: ebb8 0e02 subs.w lr, r8, r2
80004e0: eb69 0104 sbc.w r1, r9, r4
80004e4: 3801 subs r0, #1
80004e6: e7df b.n 80004a8 <__udivmoddi4+0x260>
80004e8: 4608 mov r0, r1
80004ea: e7d2 b.n 8000492 <__udivmoddi4+0x24a>
80004ec: 4660 mov r0, ip
80004ee: e78d b.n 800040c <__udivmoddi4+0x1c4>
80004f0: 4681 mov r9, r0
80004f2: e7b9 b.n 8000468 <__udivmoddi4+0x220>
80004f4: 4666 mov r6, ip
80004f6: e775 b.n 80003e4 <__udivmoddi4+0x19c>
80004f8: 4630 mov r0, r6
80004fa: e74a b.n 8000392 <__udivmoddi4+0x14a>
80004fc: f1ac 0c02 sub.w ip, ip, #2
8000500: 4439 add r1, r7
8000502: e713 b.n 800032c <__udivmoddi4+0xe4>
8000504: 3802 subs r0, #2
8000506: 443c add r4, r7
8000508: e724 b.n 8000354 <__udivmoddi4+0x10c>
800050a: bf00 nop
0800050c <__aeabi_idiv0>:
800050c: 4770 bx lr
800050e: bf00 nop
08000510 <MX_GPIO_Init>:
* Output
* EVENT_OUT
* EXTI
*/
void MX_GPIO_Init(void)
{
8000510: b580 push {r7, lr}
8000512: b08a sub sp, #40 ; 0x28
8000514: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000516: f107 0314 add.w r3, r7, #20
800051a: 2200 movs r2, #0
800051c: 601a str r2, [r3, #0]
800051e: 605a str r2, [r3, #4]
8000520: 609a str r2, [r3, #8]
8000522: 60da str r2, [r3, #12]
8000524: 611a str r2, [r3, #16]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
8000526: 4b2f ldr r3, [pc, #188] ; (80005e4 <MX_GPIO_Init+0xd4>)
8000528: 6cdb ldr r3, [r3, #76] ; 0x4c
800052a: 4a2e ldr r2, [pc, #184] ; (80005e4 <MX_GPIO_Init+0xd4>)
800052c: f043 0304 orr.w r3, r3, #4
8000530: 64d3 str r3, [r2, #76] ; 0x4c
8000532: 4b2c ldr r3, [pc, #176] ; (80005e4 <MX_GPIO_Init+0xd4>)
8000534: 6cdb ldr r3, [r3, #76] ; 0x4c
8000536: f003 0304 and.w r3, r3, #4
800053a: 613b str r3, [r7, #16]
800053c: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOF_CLK_ENABLE();
800053e: 4b29 ldr r3, [pc, #164] ; (80005e4 <MX_GPIO_Init+0xd4>)
8000540: 6cdb ldr r3, [r3, #76] ; 0x4c
8000542: 4a28 ldr r2, [pc, #160] ; (80005e4 <MX_GPIO_Init+0xd4>)
8000544: f043 0320 orr.w r3, r3, #32
8000548: 64d3 str r3, [r2, #76] ; 0x4c
800054a: 4b26 ldr r3, [pc, #152] ; (80005e4 <MX_GPIO_Init+0xd4>)
800054c: 6cdb ldr r3, [r3, #76] ; 0x4c
800054e: f003 0320 and.w r3, r3, #32
8000552: 60fb str r3, [r7, #12]
8000554: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000556: 4b23 ldr r3, [pc, #140] ; (80005e4 <MX_GPIO_Init+0xd4>)
8000558: 6cdb ldr r3, [r3, #76] ; 0x4c
800055a: 4a22 ldr r2, [pc, #136] ; (80005e4 <MX_GPIO_Init+0xd4>)
800055c: f043 0301 orr.w r3, r3, #1
8000560: 64d3 str r3, [r2, #76] ; 0x4c
8000562: 4b20 ldr r3, [pc, #128] ; (80005e4 <MX_GPIO_Init+0xd4>)
8000564: 6cdb ldr r3, [r3, #76] ; 0x4c
8000566: f003 0301 and.w r3, r3, #1
800056a: 60bb str r3, [r7, #8]
800056c: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
800056e: 4b1d ldr r3, [pc, #116] ; (80005e4 <MX_GPIO_Init+0xd4>)
8000570: 6cdb ldr r3, [r3, #76] ; 0x4c
8000572: 4a1c ldr r2, [pc, #112] ; (80005e4 <MX_GPIO_Init+0xd4>)
8000574: f043 0302 orr.w r3, r3, #2
8000578: 64d3 str r3, [r2, #76] ; 0x4c
800057a: 4b1a ldr r3, [pc, #104] ; (80005e4 <MX_GPIO_Init+0xd4>)
800057c: 6cdb ldr r3, [r3, #76] ; 0x4c
800057e: f003 0302 and.w r3, r3, #2
8000582: 607b str r3, [r7, #4]
8000584: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
8000586: 2200 movs r2, #0
8000588: 2120 movs r1, #32
800058a: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
800058e: f000 fd4f bl 8001030 <HAL_GPIO_WritePin>
/*Configure GPIO pin : PtPin */
GPIO_InitStruct.Pin = B1_Pin;
8000592: f44f 5300 mov.w r3, #8192 ; 0x2000
8000596: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000598: 4b13 ldr r3, [pc, #76] ; (80005e8 <MX_GPIO_Init+0xd8>)
800059a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800059c: 2300 movs r3, #0
800059e: 61fb str r3, [r7, #28]
HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
80005a0: f107 0314 add.w r3, r7, #20
80005a4: 4619 mov r1, r3
80005a6: 4811 ldr r0, [pc, #68] ; (80005ec <MX_GPIO_Init+0xdc>)
80005a8: f000 fbc0 bl 8000d2c <HAL_GPIO_Init>
/*Configure GPIO pin : PtPin */
GPIO_InitStruct.Pin = LD2_Pin;
80005ac: 2320 movs r3, #32
80005ae: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80005b0: 2301 movs r3, #1
80005b2: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80005b4: 2300 movs r3, #0
80005b6: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80005b8: 2300 movs r3, #0
80005ba: 623b str r3, [r7, #32]
HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
80005bc: f107 0314 add.w r3, r7, #20
80005c0: 4619 mov r1, r3
80005c2: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
80005c6: f000 fbb1 bl 8000d2c <HAL_GPIO_Init>
/* EXTI interrupt init*/
HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
80005ca: 2200 movs r2, #0
80005cc: 2100 movs r1, #0
80005ce: 2028 movs r0, #40 ; 0x28
80005d0: f000 fb77 bl 8000cc2 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
80005d4: 2028 movs r0, #40 ; 0x28
80005d6: f000 fb8e bl 8000cf6 <HAL_NVIC_EnableIRQ>
}
80005da: bf00 nop
80005dc: 3728 adds r7, #40 ; 0x28
80005de: 46bd mov sp, r7
80005e0: bd80 pop {r7, pc}
80005e2: bf00 nop
80005e4: 40021000 .word 0x40021000
80005e8: 10110000 .word 0x10110000
80005ec: 48000800 .word 0x48000800
080005f0 <MX_I2C1_Init>:
I2C_HandleTypeDef hi2c1;
/* I2C1 init function */
void MX_I2C1_Init(void)
{
80005f0: b580 push {r7, lr}
80005f2: af00 add r7, sp, #0
/* USER CODE END I2C1_Init 0 */
/* USER CODE BEGIN I2C1_Init 1 */
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
80005f4: 4b1b ldr r3, [pc, #108] ; (8000664 <MX_I2C1_Init+0x74>)
80005f6: 4a1c ldr r2, [pc, #112] ; (8000668 <MX_I2C1_Init+0x78>)
80005f8: 601a str r2, [r3, #0]
hi2c1.Init.Timing = 0x30A0A7FB;
80005fa: 4b1a ldr r3, [pc, #104] ; (8000664 <MX_I2C1_Init+0x74>)
80005fc: 4a1b ldr r2, [pc, #108] ; (800066c <MX_I2C1_Init+0x7c>)
80005fe: 605a str r2, [r3, #4]
hi2c1.Init.OwnAddress1 = 0;
8000600: 4b18 ldr r3, [pc, #96] ; (8000664 <MX_I2C1_Init+0x74>)
8000602: 2200 movs r2, #0
8000604: 609a str r2, [r3, #8]
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
8000606: 4b17 ldr r3, [pc, #92] ; (8000664 <MX_I2C1_Init+0x74>)
8000608: 2201 movs r2, #1
800060a: 60da str r2, [r3, #12]
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
800060c: 4b15 ldr r3, [pc, #84] ; (8000664 <MX_I2C1_Init+0x74>)
800060e: 2200 movs r2, #0
8000610: 611a str r2, [r3, #16]
hi2c1.Init.OwnAddress2 = 0;
8000612: 4b14 ldr r3, [pc, #80] ; (8000664 <MX_I2C1_Init+0x74>)
8000614: 2200 movs r2, #0
8000616: 615a str r2, [r3, #20]
hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
8000618: 4b12 ldr r3, [pc, #72] ; (8000664 <MX_I2C1_Init+0x74>)
800061a: 2200 movs r2, #0
800061c: 619a str r2, [r3, #24]
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
800061e: 4b11 ldr r3, [pc, #68] ; (8000664 <MX_I2C1_Init+0x74>)
8000620: 2200 movs r2, #0
8000622: 61da str r2, [r3, #28]
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
8000624: 4b0f ldr r3, [pc, #60] ; (8000664 <MX_I2C1_Init+0x74>)
8000626: 2200 movs r2, #0
8000628: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
800062a: 480e ldr r0, [pc, #56] ; (8000664 <MX_I2C1_Init+0x74>)
800062c: f000 fd3b bl 80010a6 <HAL_I2C_Init>
8000630: 4603 mov r3, r0
8000632: 2b00 cmp r3, #0
8000634: d001 beq.n 800063a <MX_I2C1_Init+0x4a>
{
Error_Handler();
8000636: f000 f8d5 bl 80007e4 <Error_Handler>
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
800063a: 2100 movs r1, #0
800063c: 4809 ldr r0, [pc, #36] ; (8000664 <MX_I2C1_Init+0x74>)
800063e: f000 fdc1 bl 80011c4 <HAL_I2CEx_ConfigAnalogFilter>
8000642: 4603 mov r3, r0
8000644: 2b00 cmp r3, #0
8000646: d001 beq.n 800064c <MX_I2C1_Init+0x5c>
{
Error_Handler();
8000648: f000 f8cc bl 80007e4 <Error_Handler>
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
800064c: 2100 movs r1, #0
800064e: 4805 ldr r0, [pc, #20] ; (8000664 <MX_I2C1_Init+0x74>)
8000650: f000 fe03 bl 800125a <HAL_I2CEx_ConfigDigitalFilter>
8000654: 4603 mov r3, r0
8000656: 2b00 cmp r3, #0
8000658: d001 beq.n 800065e <MX_I2C1_Init+0x6e>
{
Error_Handler();
800065a: f000 f8c3 bl 80007e4 <Error_Handler>
}
/* USER CODE BEGIN I2C1_Init 2 */
/* USER CODE END I2C1_Init 2 */
}
800065e: bf00 nop
8000660: bd80 pop {r7, pc}
8000662: bf00 nop
8000664: 20000028 .word 0x20000028
8000668: 40005400 .word 0x40005400
800066c: 30a0a7fb .word 0x30a0a7fb
08000670 <HAL_I2C_MspInit>:
void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
{
8000670: b580 push {r7, lr}
8000672: b08a sub sp, #40 ; 0x28
8000674: af00 add r7, sp, #0
8000676: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000678: f107 0314 add.w r3, r7, #20
800067c: 2200 movs r2, #0
800067e: 601a str r2, [r3, #0]
8000680: 605a str r2, [r3, #4]
8000682: 609a str r2, [r3, #8]
8000684: 60da str r2, [r3, #12]
8000686: 611a str r2, [r3, #16]
if(i2cHandle->Instance==I2C1)
8000688: 687b ldr r3, [r7, #4]
800068a: 681b ldr r3, [r3, #0]
800068c: 4a17 ldr r2, [pc, #92] ; (80006ec <HAL_I2C_MspInit+0x7c>)
800068e: 4293 cmp r3, r2
8000690: d128 bne.n 80006e4 <HAL_I2C_MspInit+0x74>
{
/* USER CODE BEGIN I2C1_MspInit 0 */
/* USER CODE END I2C1_MspInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
8000692: 4b17 ldr r3, [pc, #92] ; (80006f0 <HAL_I2C_MspInit+0x80>)
8000694: 6cdb ldr r3, [r3, #76] ; 0x4c
8000696: 4a16 ldr r2, [pc, #88] ; (80006f0 <HAL_I2C_MspInit+0x80>)
8000698: f043 0302 orr.w r3, r3, #2
800069c: 64d3 str r3, [r2, #76] ; 0x4c
800069e: 4b14 ldr r3, [pc, #80] ; (80006f0 <HAL_I2C_MspInit+0x80>)
80006a0: 6cdb ldr r3, [r3, #76] ; 0x4c
80006a2: f003 0302 and.w r3, r3, #2
80006a6: 613b str r3, [r7, #16]
80006a8: 693b ldr r3, [r7, #16]
/**I2C1 GPIO Configuration
PB8-BOOT0 ------> I2C1_SCL
PB9 ------> I2C1_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
80006aa: f44f 7340 mov.w r3, #768 ; 0x300
80006ae: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
80006b0: 2312 movs r3, #18
80006b2: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_PULLUP;
80006b4: 2301 movs r3, #1
80006b6: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80006b8: 2300 movs r3, #0
80006ba: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
80006bc: 2304 movs r3, #4
80006be: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80006c0: f107 0314 add.w r3, r7, #20
80006c4: 4619 mov r1, r3
80006c6: 480b ldr r0, [pc, #44] ; (80006f4 <HAL_I2C_MspInit+0x84>)
80006c8: f000 fb30 bl 8000d2c <HAL_GPIO_Init>
/* I2C1 clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
80006cc: 4b08 ldr r3, [pc, #32] ; (80006f0 <HAL_I2C_MspInit+0x80>)
80006ce: 6d9b ldr r3, [r3, #88] ; 0x58
80006d0: 4a07 ldr r2, [pc, #28] ; (80006f0 <HAL_I2C_MspInit+0x80>)
80006d2: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
80006d6: 6593 str r3, [r2, #88] ; 0x58
80006d8: 4b05 ldr r3, [pc, #20] ; (80006f0 <HAL_I2C_MspInit+0x80>)
80006da: 6d9b ldr r3, [r3, #88] ; 0x58
80006dc: f403 1300 and.w r3, r3, #2097152 ; 0x200000
80006e0: 60fb str r3, [r7, #12]
80006e2: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN I2C1_MspInit 1 */
/* USER CODE END I2C1_MspInit 1 */
}
}
80006e4: bf00 nop
80006e6: 3728 adds r7, #40 ; 0x28
80006e8: 46bd mov sp, r7
80006ea: bd80 pop {r7, pc}
80006ec: 40005400 .word 0x40005400
80006f0: 40021000 .word 0x40021000
80006f4: 48000400 .word 0x48000400
080006f8 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80006f8: b580 push {r7, lr}
80006fa: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80006fc: f000 f995 bl 8000a2a <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000700: f000 f807 bl 8000712 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000704: f7ff ff04 bl 8000510 <MX_GPIO_Init>
MX_LPUART1_UART_Init();
8000708: f000 f8da bl 80008c0 <MX_LPUART1_UART_Init>
MX_I2C1_Init();
800070c: f7ff ff70 bl 80005f0 <MX_I2C1_Init>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
8000710: e7fe b.n 8000710 <main+0x18>
08000712 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000712: b580 push {r7, lr}
8000714: b0a8 sub sp, #160 ; 0xa0
8000716: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000718: f107 0368 add.w r3, r7, #104 ; 0x68
800071c: 2238 movs r2, #56 ; 0x38
800071e: 2100 movs r1, #0
8000720: 4618 mov r0, r3
8000722: f002 fbc9 bl 8002eb8 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000726: f107 0354 add.w r3, r7, #84 ; 0x54
800072a: 2200 movs r2, #0
800072c: 601a str r2, [r3, #0]
800072e: 605a str r2, [r3, #4]
8000730: 609a str r2, [r3, #8]
8000732: 60da str r2, [r3, #12]
8000734: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8000736: 463b mov r3, r7
8000738: 2254 movs r2, #84 ; 0x54
800073a: 2100 movs r1, #0
800073c: 4618 mov r0, r3
800073e: f002 fbbb bl 8002eb8 <memset>
/** Configure the main internal regulator output voltage
*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
8000742: 2000 movs r0, #0
8000744: f000 fdd6 bl 80012f4 <HAL_PWREx_ControlVoltageScaling>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
8000748: 2302 movs r3, #2
800074a: 66bb str r3, [r7, #104] ; 0x68
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
800074c: f44f 7380 mov.w r3, #256 ; 0x100
8000750: 677b str r3, [r7, #116] ; 0x74
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
8000752: 2340 movs r3, #64 ; 0x40
8000754: 67bb str r3, [r7, #120] ; 0x78
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000756: 2302 movs r3, #2
8000758: f8c7 3084 str.w r3, [r7, #132] ; 0x84
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
800075c: 2302 movs r3, #2
800075e: f8c7 3088 str.w r3, [r7, #136] ; 0x88
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
8000762: 2304 movs r3, #4
8000764: f8c7 308c str.w r3, [r7, #140] ; 0x8c
RCC_OscInitStruct.PLL.PLLN = 85;
8000768: 2355 movs r3, #85 ; 0x55
800076a: f8c7 3090 str.w r3, [r7, #144] ; 0x90
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
800076e: 2302 movs r3, #2
8000770: f8c7 3094 str.w r3, [r7, #148] ; 0x94
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
8000774: 2302 movs r3, #2
8000776: f8c7 3098 str.w r3, [r7, #152] ; 0x98
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
800077a: 2302 movs r3, #2
800077c: f8c7 309c str.w r3, [r7, #156] ; 0x9c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000780: f107 0368 add.w r3, r7, #104 ; 0x68
8000784: 4618 mov r0, r3
8000786: f000 fe69 bl 800145c <HAL_RCC_OscConfig>
800078a: 4603 mov r3, r0
800078c: 2b00 cmp r3, #0
800078e: d001 beq.n 8000794 <SystemClock_Config+0x82>
{
Error_Handler();
8000790: f000 f828 bl 80007e4 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000794: 230f movs r3, #15
8000796: 657b str r3, [r7, #84] ; 0x54
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000798: 2303 movs r3, #3
800079a: 65bb str r3, [r7, #88] ; 0x58
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
800079c: 2300 movs r3, #0
800079e: 65fb str r3, [r7, #92] ; 0x5c
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80007a0: 2300 movs r3, #0
80007a2: 663b str r3, [r7, #96] ; 0x60
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80007a4: 2300 movs r3, #0
80007a6: 667b str r3, [r7, #100] ; 0x64
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
80007a8: f107 0354 add.w r3, r7, #84 ; 0x54
80007ac: 2104 movs r1, #4
80007ae: 4618 mov r0, r3
80007b0: f001 f96c bl 8001a8c <HAL_RCC_ClockConfig>
80007b4: 4603 mov r3, r0
80007b6: 2b00 cmp r3, #0
80007b8: d001 beq.n 80007be <SystemClock_Config+0xac>
{
Error_Handler();
80007ba: f000 f813 bl 80007e4 <Error_Handler>
}
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1|RCC_PERIPHCLK_I2C1;
80007be: 2360 movs r3, #96 ; 0x60
80007c0: 603b str r3, [r7, #0]
PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
80007c2: 2300 movs r3, #0
80007c4: 61bb str r3, [r7, #24]
PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
80007c6: 2300 movs r3, #0
80007c8: 61fb str r3, [r7, #28]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
80007ca: 463b mov r3, r7
80007cc: 4618 mov r0, r3
80007ce: f001 fb79 bl 8001ec4 <HAL_RCCEx_PeriphCLKConfig>
80007d2: 4603 mov r3, r0
80007d4: 2b00 cmp r3, #0
80007d6: d001 beq.n 80007dc <SystemClock_Config+0xca>
{
Error_Handler();
80007d8: f000 f804 bl 80007e4 <Error_Handler>
}
}
80007dc: bf00 nop
80007de: 37a0 adds r7, #160 ; 0xa0
80007e0: 46bd mov sp, r7
80007e2: bd80 pop {r7, pc}
080007e4 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80007e4: b480 push {r7}
80007e6: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80007e8: b672 cpsid i
}
80007ea: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80007ec: e7fe b.n 80007ec <Error_Handler+0x8>
...
080007f0 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80007f0: b580 push {r7, lr}
80007f2: b082 sub sp, #8
80007f4: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80007f6: 4b0f ldr r3, [pc, #60] ; (8000834 <HAL_MspInit+0x44>)
80007f8: 6e1b ldr r3, [r3, #96] ; 0x60
80007fa: 4a0e ldr r2, [pc, #56] ; (8000834 <HAL_MspInit+0x44>)
80007fc: f043 0301 orr.w r3, r3, #1
8000800: 6613 str r3, [r2, #96] ; 0x60
8000802: 4b0c ldr r3, [pc, #48] ; (8000834 <HAL_MspInit+0x44>)
8000804: 6e1b ldr r3, [r3, #96] ; 0x60
8000806: f003 0301 and.w r3, r3, #1
800080a: 607b str r3, [r7, #4]
800080c: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
800080e: 4b09 ldr r3, [pc, #36] ; (8000834 <HAL_MspInit+0x44>)
8000810: 6d9b ldr r3, [r3, #88] ; 0x58
8000812: 4a08 ldr r2, [pc, #32] ; (8000834 <HAL_MspInit+0x44>)
8000814: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000818: 6593 str r3, [r2, #88] ; 0x58
800081a: 4b06 ldr r3, [pc, #24] ; (8000834 <HAL_MspInit+0x44>)
800081c: 6d9b ldr r3, [r3, #88] ; 0x58
800081e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000822: 603b str r3, [r7, #0]
8000824: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
*/
HAL_PWREx_DisableUCPDDeadBattery();
8000826: f000 fe09 bl 800143c <HAL_PWREx_DisableUCPDDeadBattery>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800082a: bf00 nop
800082c: 3708 adds r7, #8
800082e: 46bd mov sp, r7
8000830: bd80 pop {r7, pc}
8000832: bf00 nop
8000834: 40021000 .word 0x40021000
08000838 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000838: b480 push {r7}
800083a: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
800083c: e7fe b.n 800083c <NMI_Handler+0x4>
0800083e <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800083e: b480 push {r7}
8000840: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000842: e7fe b.n 8000842 <HardFault_Handler+0x4>
08000844 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000844: b480 push {r7}
8000846: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000848: e7fe b.n 8000848 <MemManage_Handler+0x4>
0800084a <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
800084a: b480 push {r7}
800084c: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
800084e: e7fe b.n 800084e <BusFault_Handler+0x4>
08000850 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000850: b480 push {r7}
8000852: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000854: e7fe b.n 8000854 <UsageFault_Handler+0x4>
08000856 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000856: b480 push {r7}
8000858: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
800085a: bf00 nop
800085c: 46bd mov sp, r7
800085e: f85d 7b04 ldr.w r7, [sp], #4
8000862: 4770 bx lr
08000864 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000864: b480 push {r7}
8000866: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000868: bf00 nop
800086a: 46bd mov sp, r7
800086c: f85d 7b04 ldr.w r7, [sp], #4
8000870: 4770 bx lr
08000872 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000872: b480 push {r7}
8000874: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000876: bf00 nop
8000878: 46bd mov sp, r7
800087a: f85d 7b04 ldr.w r7, [sp], #4
800087e: 4770 bx lr
08000880 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000880: b580 push {r7, lr}
8000882: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000884: f000 f924 bl 8000ad0 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000888: bf00 nop
800088a: bd80 pop {r7, pc}
0800088c <EXTI15_10_IRQHandler>:
/**
* @brief This function handles EXTI line[15:10] interrupts.
*/
void EXTI15_10_IRQHandler(void)
{
800088c: b580 push {r7, lr}
800088e: af00 add r7, sp, #0
/* USER CODE BEGIN EXTI15_10_IRQn 0 */
/* USER CODE END EXTI15_10_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
8000890: f44f 5000 mov.w r0, #8192 ; 0x2000
8000894: f000 fbe4 bl 8001060 <HAL_GPIO_EXTI_IRQHandler>
/* USER CODE BEGIN EXTI15_10_IRQn 1 */
/* USER CODE END EXTI15_10_IRQn 1 */
}
8000898: bf00 nop
800089a: bd80 pop {r7, pc}
0800089c <SystemInit>:
* @param None
* @retval None
*/
void SystemInit(void)
{
800089c: b480 push {r7}
800089e: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
80008a0: 4b06 ldr r3, [pc, #24] ; (80008bc <SystemInit+0x20>)
80008a2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80008a6: 4a05 ldr r2, [pc, #20] ; (80008bc <SystemInit+0x20>)
80008a8: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
80008ac: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location add offset address ------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
80008b0: bf00 nop
80008b2: 46bd mov sp, r7
80008b4: f85d 7b04 ldr.w r7, [sp], #4
80008b8: 4770 bx lr
80008ba: bf00 nop
80008bc: e000ed00 .word 0xe000ed00
080008c0 <MX_LPUART1_UART_Init>:
UART_HandleTypeDef hlpuart1;
/* LPUART1 init function */
void MX_LPUART1_UART_Init(void)
{
80008c0: b580 push {r7, lr}
80008c2: af00 add r7, sp, #0
/* USER CODE END LPUART1_Init 0 */
/* USER CODE BEGIN LPUART1_Init 1 */
/* USER CODE END LPUART1_Init 1 */
hlpuart1.Instance = LPUART1;
80008c4: 4b21 ldr r3, [pc, #132] ; (800094c <MX_LPUART1_UART_Init+0x8c>)
80008c6: 4a22 ldr r2, [pc, #136] ; (8000950 <MX_LPUART1_UART_Init+0x90>)
80008c8: 601a str r2, [r3, #0]
hlpuart1.Init.BaudRate = 115200;
80008ca: 4b20 ldr r3, [pc, #128] ; (800094c <MX_LPUART1_UART_Init+0x8c>)
80008cc: f44f 32e1 mov.w r2, #115200 ; 0x1c200
80008d0: 605a str r2, [r3, #4]
hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
80008d2: 4b1e ldr r3, [pc, #120] ; (800094c <MX_LPUART1_UART_Init+0x8c>)
80008d4: 2200 movs r2, #0
80008d6: 609a str r2, [r3, #8]
hlpuart1.Init.StopBits = UART_STOPBITS_1;
80008d8: 4b1c ldr r3, [pc, #112] ; (800094c <MX_LPUART1_UART_Init+0x8c>)
80008da: 2200 movs r2, #0
80008dc: 60da str r2, [r3, #12]
hlpuart1.Init.Parity = UART_PARITY_NONE;
80008de: 4b1b ldr r3, [pc, #108] ; (800094c <MX_LPUART1_UART_Init+0x8c>)
80008e0: 2200 movs r2, #0
80008e2: 611a str r2, [r3, #16]
hlpuart1.Init.Mode = UART_MODE_TX_RX;
80008e4: 4b19 ldr r3, [pc, #100] ; (800094c <MX_LPUART1_UART_Init+0x8c>)
80008e6: 220c movs r2, #12
80008e8: 615a str r2, [r3, #20]
hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80008ea: 4b18 ldr r3, [pc, #96] ; (800094c <MX_LPUART1_UART_Init+0x8c>)
80008ec: 2200 movs r2, #0
80008ee: 619a str r2, [r3, #24]
hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
80008f0: 4b16 ldr r3, [pc, #88] ; (800094c <MX_LPUART1_UART_Init+0x8c>)
80008f2: 2200 movs r2, #0
80008f4: 621a str r2, [r3, #32]
hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
80008f6: 4b15 ldr r3, [pc, #84] ; (800094c <MX_LPUART1_UART_Init+0x8c>)
80008f8: 2200 movs r2, #0
80008fa: 625a str r2, [r3, #36] ; 0x24
hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
80008fc: 4b13 ldr r3, [pc, #76] ; (800094c <MX_LPUART1_UART_Init+0x8c>)
80008fe: 2200 movs r2, #0
8000900: 629a str r2, [r3, #40] ; 0x28
if (HAL_UART_Init(&hlpuart1) != HAL_OK)
8000902: 4812 ldr r0, [pc, #72] ; (800094c <MX_LPUART1_UART_Init+0x8c>)
8000904: f001 fd2a bl 800235c <HAL_UART_Init>
8000908: 4603 mov r3, r0
800090a: 2b00 cmp r3, #0
800090c: d001 beq.n 8000912 <MX_LPUART1_UART_Init+0x52>
{
Error_Handler();
800090e: f7ff ff69 bl 80007e4 <Error_Handler>
}
if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
8000912: 2100 movs r1, #0
8000914: 480d ldr r0, [pc, #52] ; (800094c <MX_LPUART1_UART_Init+0x8c>)
8000916: f002 f9e1 bl 8002cdc <HAL_UARTEx_SetTxFifoThreshold>
800091a: 4603 mov r3, r0
800091c: 2b00 cmp r3, #0
800091e: d001 beq.n 8000924 <MX_LPUART1_UART_Init+0x64>
{
Error_Handler();
8000920: f7ff ff60 bl 80007e4 <Error_Handler>
}
if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
8000924: 2100 movs r1, #0
8000926: 4809 ldr r0, [pc, #36] ; (800094c <MX_LPUART1_UART_Init+0x8c>)
8000928: f002 fa16 bl 8002d58 <HAL_UARTEx_SetRxFifoThreshold>
800092c: 4603 mov r3, r0
800092e: 2b00 cmp r3, #0
8000930: d001 beq.n 8000936 <MX_LPUART1_UART_Init+0x76>
{
Error_Handler();
8000932: f7ff ff57 bl 80007e4 <Error_Handler>
}
if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK)
8000936: 4805 ldr r0, [pc, #20] ; (800094c <MX_LPUART1_UART_Init+0x8c>)
8000938: f002 f997 bl 8002c6a <HAL_UARTEx_DisableFifoMode>
800093c: 4603 mov r3, r0
800093e: 2b00 cmp r3, #0
8000940: d001 beq.n 8000946 <MX_LPUART1_UART_Init+0x86>
{
Error_Handler();
8000942: f7ff ff4f bl 80007e4 <Error_Handler>
}
/* USER CODE BEGIN LPUART1_Init 2 */
/* USER CODE END LPUART1_Init 2 */
}
8000946: bf00 nop
8000948: bd80 pop {r7, pc}
800094a: bf00 nop
800094c: 20000074 .word 0x20000074
8000950: 40008000 .word 0x40008000
08000954 <HAL_UART_MspInit>:
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
{
8000954: b580 push {r7, lr}
8000956: b08a sub sp, #40 ; 0x28
8000958: af00 add r7, sp, #0
800095a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800095c: f107 0314 add.w r3, r7, #20
8000960: 2200 movs r2, #0
8000962: 601a str r2, [r3, #0]
8000964: 605a str r2, [r3, #4]
8000966: 609a str r2, [r3, #8]
8000968: 60da str r2, [r3, #12]
800096a: 611a str r2, [r3, #16]
if(uartHandle->Instance==LPUART1)
800096c: 687b ldr r3, [r7, #4]
800096e: 681b ldr r3, [r3, #0]
8000970: 4a17 ldr r2, [pc, #92] ; (80009d0 <HAL_UART_MspInit+0x7c>)
8000972: 4293 cmp r3, r2
8000974: d128 bne.n 80009c8 <HAL_UART_MspInit+0x74>
{
/* USER CODE BEGIN LPUART1_MspInit 0 */
/* USER CODE END LPUART1_MspInit 0 */
/* LPUART1 clock enable */
__HAL_RCC_LPUART1_CLK_ENABLE();
8000976: 4b17 ldr r3, [pc, #92] ; (80009d4 <HAL_UART_MspInit+0x80>)
8000978: 6ddb ldr r3, [r3, #92] ; 0x5c
800097a: 4a16 ldr r2, [pc, #88] ; (80009d4 <HAL_UART_MspInit+0x80>)
800097c: f043 0301 orr.w r3, r3, #1
8000980: 65d3 str r3, [r2, #92] ; 0x5c
8000982: 4b14 ldr r3, [pc, #80] ; (80009d4 <HAL_UART_MspInit+0x80>)
8000984: 6ddb ldr r3, [r3, #92] ; 0x5c
8000986: f003 0301 and.w r3, r3, #1
800098a: 613b str r3, [r7, #16]
800098c: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800098e: 4b11 ldr r3, [pc, #68] ; (80009d4 <HAL_UART_MspInit+0x80>)
8000990: 6cdb ldr r3, [r3, #76] ; 0x4c
8000992: 4a10 ldr r2, [pc, #64] ; (80009d4 <HAL_UART_MspInit+0x80>)
8000994: f043 0301 orr.w r3, r3, #1
8000998: 64d3 str r3, [r2, #76] ; 0x4c
800099a: 4b0e ldr r3, [pc, #56] ; (80009d4 <HAL_UART_MspInit+0x80>)
800099c: 6cdb ldr r3, [r3, #76] ; 0x4c
800099e: f003 0301 and.w r3, r3, #1
80009a2: 60fb str r3, [r7, #12]
80009a4: 68fb ldr r3, [r7, #12]
/**LPUART1 GPIO Configuration
PA2 ------> LPUART1_TX
PA3 ------> LPUART1_RX
*/
GPIO_InitStruct.Pin = LPUART1_TX_Pin|LPUART1_RX_Pin;
80009a6: 230c movs r3, #12
80009a8: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80009aa: 2302 movs r3, #2
80009ac: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80009ae: 2300 movs r3, #0
80009b0: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80009b2: 2300 movs r3, #0
80009b4: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF12_LPUART1;
80009b6: 230c movs r3, #12
80009b8: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80009ba: f107 0314 add.w r3, r7, #20
80009be: 4619 mov r1, r3
80009c0: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
80009c4: f000 f9b2 bl 8000d2c <HAL_GPIO_Init>
/* USER CODE BEGIN LPUART1_MspInit 1 */
/* USER CODE END LPUART1_MspInit 1 */
}
}
80009c8: bf00 nop
80009ca: 3728 adds r7, #40 ; 0x28
80009cc: 46bd mov sp, r7
80009ce: bd80 pop {r7, pc}
80009d0: 40008000 .word 0x40008000
80009d4: 40021000 .word 0x40021000
080009d8 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
80009d8: 480d ldr r0, [pc, #52] ; (8000a10 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
80009da: 4685 mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80009dc: 480d ldr r0, [pc, #52] ; (8000a14 <LoopForever+0x6>)
ldr r1, =_edata
80009de: 490e ldr r1, [pc, #56] ; (8000a18 <LoopForever+0xa>)
ldr r2, =_sidata
80009e0: 4a0e ldr r2, [pc, #56] ; (8000a1c <LoopForever+0xe>)
movs r3, #0
80009e2: 2300 movs r3, #0
b LoopCopyDataInit
80009e4: e002 b.n 80009ec <LoopCopyDataInit>
080009e6 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80009e6: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80009e8: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80009ea: 3304 adds r3, #4
080009ec <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80009ec: 18c4 adds r4, r0, r3
cmp r4, r1
80009ee: 428c cmp r4, r1
bcc CopyDataInit
80009f0: d3f9 bcc.n 80009e6 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80009f2: 4a0b ldr r2, [pc, #44] ; (8000a20 <LoopForever+0x12>)
ldr r4, =_ebss
80009f4: 4c0b ldr r4, [pc, #44] ; (8000a24 <LoopForever+0x16>)
movs r3, #0
80009f6: 2300 movs r3, #0
b LoopFillZerobss
80009f8: e001 b.n 80009fe <LoopFillZerobss>
080009fa <FillZerobss>:
FillZerobss:
str r3, [r2]
80009fa: 6013 str r3, [r2, #0]
adds r2, r2, #4
80009fc: 3204 adds r2, #4
080009fe <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80009fe: 42a2 cmp r2, r4
bcc FillZerobss
8000a00: d3fb bcc.n 80009fa <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
8000a02: f7ff ff4b bl 800089c <SystemInit>
/* Call static constructors */
bl __libc_init_array
8000a06: f002 fa33 bl 8002e70 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000a0a: f7ff fe75 bl 80006f8 <main>
08000a0e <LoopForever>:
LoopForever:
b LoopForever
8000a0e: e7fe b.n 8000a0e <LoopForever>
ldr r0, =_estack
8000a10: 20020000 .word 0x20020000
ldr r0, =_sdata
8000a14: 20000000 .word 0x20000000
ldr r1, =_edata
8000a18: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000a1c: 08002f30 .word 0x08002f30
ldr r2, =_sbss
8000a20: 2000000c .word 0x2000000c
ldr r4, =_ebss
8000a24: 20000108 .word 0x20000108
08000a28 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000a28: e7fe b.n 8000a28 <ADC1_2_IRQHandler>
08000a2a <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000a2a: b580 push {r7, lr}
8000a2c: b082 sub sp, #8
8000a2e: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8000a30: 2300 movs r3, #0
8000a32: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000a34: 2003 movs r0, #3
8000a36: f000 f939 bl 8000cac <HAL_NVIC_SetPriorityGrouping>
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8000a3a: 2000 movs r0, #0
8000a3c: f000 f80e bl 8000a5c <HAL_InitTick>
8000a40: 4603 mov r3, r0
8000a42: 2b00 cmp r3, #0
8000a44: d002 beq.n 8000a4c <HAL_Init+0x22>
{
status = HAL_ERROR;
8000a46: 2301 movs r3, #1
8000a48: 71fb strb r3, [r7, #7]
8000a4a: e001 b.n 8000a50 <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
8000a4c: f7ff fed0 bl 80007f0 <HAL_MspInit>
}
/* Return function status */
return status;
8000a50: 79fb ldrb r3, [r7, #7]
}
8000a52: 4618 mov r0, r3
8000a54: 3708 adds r7, #8
8000a56: 46bd mov sp, r7
8000a58: bd80 pop {r7, pc}
...
08000a5c <HAL_InitTick>:
* implementation in user file.
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000a5c: b580 push {r7, lr}
8000a5e: b084 sub sp, #16
8000a60: af00 add r7, sp, #0
8000a62: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8000a64: 2300 movs r3, #0
8000a66: 73fb strb r3, [r7, #15]
if (uwTickFreq != 0U)
8000a68: 4b16 ldr r3, [pc, #88] ; (8000ac4 <HAL_InitTick+0x68>)
8000a6a: 681b ldr r3, [r3, #0]
8000a6c: 2b00 cmp r3, #0
8000a6e: d022 beq.n 8000ab6 <HAL_InitTick+0x5a>
{
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
8000a70: 4b15 ldr r3, [pc, #84] ; (8000ac8 <HAL_InitTick+0x6c>)
8000a72: 681a ldr r2, [r3, #0]
8000a74: 4b13 ldr r3, [pc, #76] ; (8000ac4 <HAL_InitTick+0x68>)
8000a76: 681b ldr r3, [r3, #0]
8000a78: f44f 717a mov.w r1, #1000 ; 0x3e8
8000a7c: fbb1 f3f3 udiv r3, r1, r3
8000a80: fbb2 f3f3 udiv r3, r2, r3
8000a84: 4618 mov r0, r3
8000a86: f000 f944 bl 8000d12 <HAL_SYSTICK_Config>
8000a8a: 4603 mov r3, r0
8000a8c: 2b00 cmp r3, #0
8000a8e: d10f bne.n 8000ab0 <HAL_InitTick+0x54>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000a90: 687b ldr r3, [r7, #4]
8000a92: 2b0f cmp r3, #15
8000a94: d809 bhi.n 8000aaa <HAL_InitTick+0x4e>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000a96: 2200 movs r2, #0
8000a98: 6879 ldr r1, [r7, #4]
8000a9a: f04f 30ff mov.w r0, #4294967295
8000a9e: f000 f910 bl 8000cc2 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000aa2: 4a0a ldr r2, [pc, #40] ; (8000acc <HAL_InitTick+0x70>)
8000aa4: 687b ldr r3, [r7, #4]
8000aa6: 6013 str r3, [r2, #0]
8000aa8: e007 b.n 8000aba <HAL_InitTick+0x5e>
}
else
{
status = HAL_ERROR;
8000aaa: 2301 movs r3, #1
8000aac: 73fb strb r3, [r7, #15]
8000aae: e004 b.n 8000aba <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8000ab0: 2301 movs r3, #1
8000ab2: 73fb strb r3, [r7, #15]
8000ab4: e001 b.n 8000aba <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8000ab6: 2301 movs r3, #1
8000ab8: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
8000aba: 7bfb ldrb r3, [r7, #15]
}
8000abc: 4618 mov r0, r3
8000abe: 3710 adds r7, #16
8000ac0: 46bd mov sp, r7
8000ac2: bd80 pop {r7, pc}
8000ac4: 20000008 .word 0x20000008
8000ac8: 20000000 .word 0x20000000
8000acc: 20000004 .word 0x20000004
08000ad0 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000ad0: b480 push {r7}
8000ad2: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000ad4: 4b05 ldr r3, [pc, #20] ; (8000aec <HAL_IncTick+0x1c>)
8000ad6: 681a ldr r2, [r3, #0]
8000ad8: 4b05 ldr r3, [pc, #20] ; (8000af0 <HAL_IncTick+0x20>)
8000ada: 681b ldr r3, [r3, #0]
8000adc: 4413 add r3, r2
8000ade: 4a03 ldr r2, [pc, #12] ; (8000aec <HAL_IncTick+0x1c>)
8000ae0: 6013 str r3, [r2, #0]
}
8000ae2: bf00 nop
8000ae4: 46bd mov sp, r7
8000ae6: f85d 7b04 ldr.w r7, [sp], #4
8000aea: 4770 bx lr
8000aec: 20000104 .word 0x20000104
8000af0: 20000008 .word 0x20000008
08000af4 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000af4: b480 push {r7}
8000af6: af00 add r7, sp, #0
return uwTick;
8000af8: 4b03 ldr r3, [pc, #12] ; (8000b08 <HAL_GetTick+0x14>)
8000afa: 681b ldr r3, [r3, #0]
}
8000afc: 4618 mov r0, r3
8000afe: 46bd mov sp, r7
8000b00: f85d 7b04 ldr.w r7, [sp], #4
8000b04: 4770 bx lr
8000b06: bf00 nop
8000b08: 20000104 .word 0x20000104
08000b0c <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000b0c: b480 push {r7}
8000b0e: b085 sub sp, #20
8000b10: af00 add r7, sp, #0
8000b12: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000b14: 687b ldr r3, [r7, #4]
8000b16: f003 0307 and.w r3, r3, #7
8000b1a: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000b1c: 4b0c ldr r3, [pc, #48] ; (8000b50 <__NVIC_SetPriorityGrouping+0x44>)
8000b1e: 68db ldr r3, [r3, #12]
8000b20: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000b22: 68ba ldr r2, [r7, #8]
8000b24: f64f 03ff movw r3, #63743 ; 0xf8ff
8000b28: 4013 ands r3, r2
8000b2a: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8000b2c: 68fb ldr r3, [r7, #12]
8000b2e: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000b30: 68bb ldr r3, [r7, #8]
8000b32: 4313 orrs r3, r2
reg_value = (reg_value |
8000b34: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
8000b38: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8000b3c: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8000b3e: 4a04 ldr r2, [pc, #16] ; (8000b50 <__NVIC_SetPriorityGrouping+0x44>)
8000b40: 68bb ldr r3, [r7, #8]
8000b42: 60d3 str r3, [r2, #12]
}
8000b44: bf00 nop
8000b46: 3714 adds r7, #20
8000b48: 46bd mov sp, r7
8000b4a: f85d 7b04 ldr.w r7, [sp], #4
8000b4e: 4770 bx lr
8000b50: e000ed00 .word 0xe000ed00
08000b54 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000b54: b480 push {r7}
8000b56: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000b58: 4b04 ldr r3, [pc, #16] ; (8000b6c <__NVIC_GetPriorityGrouping+0x18>)
8000b5a: 68db ldr r3, [r3, #12]
8000b5c: 0a1b lsrs r3, r3, #8
8000b5e: f003 0307 and.w r3, r3, #7
}
8000b62: 4618 mov r0, r3
8000b64: 46bd mov sp, r7
8000b66: f85d 7b04 ldr.w r7, [sp], #4
8000b6a: 4770 bx lr
8000b6c: e000ed00 .word 0xe000ed00
08000b70 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8000b70: b480 push {r7}
8000b72: b083 sub sp, #12
8000b74: af00 add r7, sp, #0
8000b76: 4603 mov r3, r0
8000b78: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000b7a: f997 3007 ldrsb.w r3, [r7, #7]
8000b7e: 2b00 cmp r3, #0
8000b80: db0b blt.n 8000b9a <__NVIC_EnableIRQ+0x2a>
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8000b82: 79fb ldrb r3, [r7, #7]
8000b84: f003 021f and.w r2, r3, #31
8000b88: 4907 ldr r1, [pc, #28] ; (8000ba8 <__NVIC_EnableIRQ+0x38>)
8000b8a: f997 3007 ldrsb.w r3, [r7, #7]
8000b8e: 095b lsrs r3, r3, #5
8000b90: 2001 movs r0, #1
8000b92: fa00 f202 lsl.w r2, r0, r2
8000b96: f841 2023 str.w r2, [r1, r3, lsl #2]
__COMPILER_BARRIER();
}
}
8000b9a: bf00 nop
8000b9c: 370c adds r7, #12
8000b9e: 46bd mov sp, r7
8000ba0: f85d 7b04 ldr.w r7, [sp], #4
8000ba4: 4770 bx lr
8000ba6: bf00 nop
8000ba8: e000e100 .word 0xe000e100
08000bac <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000bac: b480 push {r7}
8000bae: b083 sub sp, #12
8000bb0: af00 add r7, sp, #0
8000bb2: 4603 mov r3, r0
8000bb4: 6039 str r1, [r7, #0]
8000bb6: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000bb8: f997 3007 ldrsb.w r3, [r7, #7]
8000bbc: 2b00 cmp r3, #0
8000bbe: db0a blt.n 8000bd6 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000bc0: 683b ldr r3, [r7, #0]
8000bc2: b2da uxtb r2, r3
8000bc4: 490c ldr r1, [pc, #48] ; (8000bf8 <__NVIC_SetPriority+0x4c>)
8000bc6: f997 3007 ldrsb.w r3, [r7, #7]
8000bca: 0112 lsls r2, r2, #4
8000bcc: b2d2 uxtb r2, r2
8000bce: 440b add r3, r1
8000bd0: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8000bd4: e00a b.n 8000bec <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000bd6: 683b ldr r3, [r7, #0]
8000bd8: b2da uxtb r2, r3
8000bda: 4908 ldr r1, [pc, #32] ; (8000bfc <__NVIC_SetPriority+0x50>)
8000bdc: 79fb ldrb r3, [r7, #7]
8000bde: f003 030f and.w r3, r3, #15
8000be2: 3b04 subs r3, #4
8000be4: 0112 lsls r2, r2, #4
8000be6: b2d2 uxtb r2, r2
8000be8: 440b add r3, r1
8000bea: 761a strb r2, [r3, #24]
}
8000bec: bf00 nop
8000bee: 370c adds r7, #12
8000bf0: 46bd mov sp, r7
8000bf2: f85d 7b04 ldr.w r7, [sp], #4
8000bf6: 4770 bx lr
8000bf8: e000e100 .word 0xe000e100
8000bfc: e000ed00 .word 0xe000ed00
08000c00 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000c00: b480 push {r7}
8000c02: b089 sub sp, #36 ; 0x24
8000c04: af00 add r7, sp, #0
8000c06: 60f8 str r0, [r7, #12]
8000c08: 60b9 str r1, [r7, #8]
8000c0a: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000c0c: 68fb ldr r3, [r7, #12]
8000c0e: f003 0307 and.w r3, r3, #7
8000c12: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8000c14: 69fb ldr r3, [r7, #28]
8000c16: f1c3 0307 rsb r3, r3, #7
8000c1a: 2b04 cmp r3, #4
8000c1c: bf28 it cs
8000c1e: 2304 movcs r3, #4
8000c20: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8000c22: 69fb ldr r3, [r7, #28]
8000c24: 3304 adds r3, #4
8000c26: 2b06 cmp r3, #6
8000c28: d902 bls.n 8000c30 <NVIC_EncodePriority+0x30>
8000c2a: 69fb ldr r3, [r7, #28]
8000c2c: 3b03 subs r3, #3
8000c2e: e000 b.n 8000c32 <NVIC_EncodePriority+0x32>
8000c30: 2300 movs r3, #0
8000c32: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000c34: f04f 32ff mov.w r2, #4294967295
8000c38: 69bb ldr r3, [r7, #24]
8000c3a: fa02 f303 lsl.w r3, r2, r3
8000c3e: 43da mvns r2, r3
8000c40: 68bb ldr r3, [r7, #8]
8000c42: 401a ands r2, r3
8000c44: 697b ldr r3, [r7, #20]
8000c46: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000c48: f04f 31ff mov.w r1, #4294967295
8000c4c: 697b ldr r3, [r7, #20]
8000c4e: fa01 f303 lsl.w r3, r1, r3
8000c52: 43d9 mvns r1, r3
8000c54: 687b ldr r3, [r7, #4]
8000c56: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000c58: 4313 orrs r3, r2
);
}
8000c5a: 4618 mov r0, r3
8000c5c: 3724 adds r7, #36 ; 0x24
8000c5e: 46bd mov sp, r7
8000c60: f85d 7b04 ldr.w r7, [sp], #4
8000c64: 4770 bx lr
...
08000c68 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000c68: b580 push {r7, lr}
8000c6a: b082 sub sp, #8
8000c6c: af00 add r7, sp, #0
8000c6e: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000c70: 687b ldr r3, [r7, #4]
8000c72: 3b01 subs r3, #1
8000c74: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8000c78: d301 bcc.n 8000c7e <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8000c7a: 2301 movs r3, #1
8000c7c: e00f b.n 8000c9e <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000c7e: 4a0a ldr r2, [pc, #40] ; (8000ca8 <SysTick_Config+0x40>)
8000c80: 687b ldr r3, [r7, #4]
8000c82: 3b01 subs r3, #1
8000c84: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000c86: 210f movs r1, #15
8000c88: f04f 30ff mov.w r0, #4294967295
8000c8c: f7ff ff8e bl 8000bac <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000c90: 4b05 ldr r3, [pc, #20] ; (8000ca8 <SysTick_Config+0x40>)
8000c92: 2200 movs r2, #0
8000c94: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000c96: 4b04 ldr r3, [pc, #16] ; (8000ca8 <SysTick_Config+0x40>)
8000c98: 2207 movs r2, #7
8000c9a: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000c9c: 2300 movs r3, #0
}
8000c9e: 4618 mov r0, r3
8000ca0: 3708 adds r7, #8
8000ca2: 46bd mov sp, r7
8000ca4: bd80 pop {r7, pc}
8000ca6: bf00 nop
8000ca8: e000e010 .word 0xe000e010
08000cac <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000cac: b580 push {r7, lr}
8000cae: b082 sub sp, #8
8000cb0: af00 add r7, sp, #0
8000cb2: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000cb4: 6878 ldr r0, [r7, #4]
8000cb6: f7ff ff29 bl 8000b0c <__NVIC_SetPriorityGrouping>
}
8000cba: bf00 nop
8000cbc: 3708 adds r7, #8
8000cbe: 46bd mov sp, r7
8000cc0: bd80 pop {r7, pc}
08000cc2 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000cc2: b580 push {r7, lr}
8000cc4: b086 sub sp, #24
8000cc6: af00 add r7, sp, #0
8000cc8: 4603 mov r3, r0
8000cca: 60b9 str r1, [r7, #8]
8000ccc: 607a str r2, [r7, #4]
8000cce: 73fb strb r3, [r7, #15]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000cd0: f7ff ff40 bl 8000b54 <__NVIC_GetPriorityGrouping>
8000cd4: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8000cd6: 687a ldr r2, [r7, #4]
8000cd8: 68b9 ldr r1, [r7, #8]
8000cda: 6978 ldr r0, [r7, #20]
8000cdc: f7ff ff90 bl 8000c00 <NVIC_EncodePriority>
8000ce0: 4602 mov r2, r0
8000ce2: f997 300f ldrsb.w r3, [r7, #15]
8000ce6: 4611 mov r1, r2
8000ce8: 4618 mov r0, r3
8000cea: f7ff ff5f bl 8000bac <__NVIC_SetPriority>
}
8000cee: bf00 nop
8000cf0: 3718 adds r7, #24
8000cf2: 46bd mov sp, r7
8000cf4: bd80 pop {r7, pc}
08000cf6 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8000cf6: b580 push {r7, lr}
8000cf8: b082 sub sp, #8
8000cfa: af00 add r7, sp, #0
8000cfc: 4603 mov r3, r0
8000cfe: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8000d00: f997 3007 ldrsb.w r3, [r7, #7]
8000d04: 4618 mov r0, r3
8000d06: f7ff ff33 bl 8000b70 <__NVIC_EnableIRQ>
}
8000d0a: bf00 nop
8000d0c: 3708 adds r7, #8
8000d0e: 46bd mov sp, r7
8000d10: bd80 pop {r7, pc}
08000d12 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8000d12: b580 push {r7, lr}
8000d14: b082 sub sp, #8
8000d16: af00 add r7, sp, #0
8000d18: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000d1a: 6878 ldr r0, [r7, #4]
8000d1c: f7ff ffa4 bl 8000c68 <SysTick_Config>
8000d20: 4603 mov r3, r0
}
8000d22: 4618 mov r0, r3
8000d24: 3708 adds r7, #8
8000d26: 46bd mov sp, r7
8000d28: bd80 pop {r7, pc}
...
08000d2c <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000d2c: b480 push {r7}
8000d2e: b087 sub sp, #28
8000d30: af00 add r7, sp, #0
8000d32: 6078 str r0, [r7, #4]
8000d34: 6039 str r1, [r7, #0]
uint32_t position = 0x00U;
8000d36: 2300 movs r3, #0
8000d38: 617b str r3, [r7, #20]
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0U)
8000d3a: e15a b.n 8000ff2 <HAL_GPIO_Init+0x2c6>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1UL << position);
8000d3c: 683b ldr r3, [r7, #0]
8000d3e: 681a ldr r2, [r3, #0]
8000d40: 2101 movs r1, #1
8000d42: 697b ldr r3, [r7, #20]
8000d44: fa01 f303 lsl.w r3, r1, r3
8000d48: 4013 ands r3, r2
8000d4a: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8000d4c: 68fb ldr r3, [r7, #12]
8000d4e: 2b00 cmp r3, #0
8000d50: f000 814c beq.w 8000fec <HAL_GPIO_Init+0x2c0>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
8000d54: 683b ldr r3, [r7, #0]
8000d56: 685b ldr r3, [r3, #4]
8000d58: 2b01 cmp r3, #1
8000d5a: d00b beq.n 8000d74 <HAL_GPIO_Init+0x48>
8000d5c: 683b ldr r3, [r7, #0]
8000d5e: 685b ldr r3, [r3, #4]
8000d60: 2b02 cmp r3, #2
8000d62: d007 beq.n 8000d74 <HAL_GPIO_Init+0x48>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
8000d64: 683b ldr r3, [r7, #0]
8000d66: 685b ldr r3, [r3, #4]
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
8000d68: 2b11 cmp r3, #17
8000d6a: d003 beq.n 8000d74 <HAL_GPIO_Init+0x48>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
8000d6c: 683b ldr r3, [r7, #0]
8000d6e: 685b ldr r3, [r3, #4]
8000d70: 2b12 cmp r3, #18
8000d72: d130 bne.n 8000dd6 <HAL_GPIO_Init+0xaa>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8000d74: 687b ldr r3, [r7, #4]
8000d76: 689b ldr r3, [r3, #8]
8000d78: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
8000d7a: 697b ldr r3, [r7, #20]
8000d7c: 005b lsls r3, r3, #1
8000d7e: 2203 movs r2, #3
8000d80: fa02 f303 lsl.w r3, r2, r3
8000d84: 43db mvns r3, r3
8000d86: 693a ldr r2, [r7, #16]
8000d88: 4013 ands r3, r2
8000d8a: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2U));
8000d8c: 683b ldr r3, [r7, #0]
8000d8e: 68da ldr r2, [r3, #12]
8000d90: 697b ldr r3, [r7, #20]
8000d92: 005b lsls r3, r3, #1
8000d94: fa02 f303 lsl.w r3, r2, r3
8000d98: 693a ldr r2, [r7, #16]
8000d9a: 4313 orrs r3, r2
8000d9c: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8000d9e: 687b ldr r3, [r7, #4]
8000da0: 693a ldr r2, [r7, #16]
8000da2: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8000da4: 687b ldr r3, [r7, #4]
8000da6: 685b ldr r3, [r3, #4]
8000da8: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
8000daa: 2201 movs r2, #1
8000dac: 697b ldr r3, [r7, #20]
8000dae: fa02 f303 lsl.w r3, r2, r3
8000db2: 43db mvns r3, r3
8000db4: 693a ldr r2, [r7, #16]
8000db6: 4013 ands r3, r2
8000db8: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
8000dba: 683b ldr r3, [r7, #0]
8000dbc: 685b ldr r3, [r3, #4]
8000dbe: 091b lsrs r3, r3, #4
8000dc0: f003 0201 and.w r2, r3, #1
8000dc4: 697b ldr r3, [r7, #20]
8000dc6: fa02 f303 lsl.w r3, r2, r3
8000dca: 693a ldr r2, [r7, #16]
8000dcc: 4313 orrs r3, r2
8000dce: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8000dd0: 687b ldr r3, [r7, #4]
8000dd2: 693a ldr r2, [r7, #16]
8000dd4: 605a str r2, [r3, #4]
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8000dd6: 687b ldr r3, [r7, #4]
8000dd8: 68db ldr r3, [r3, #12]
8000dda: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
8000ddc: 697b ldr r3, [r7, #20]
8000dde: 005b lsls r3, r3, #1
8000de0: 2203 movs r2, #3
8000de2: fa02 f303 lsl.w r3, r2, r3
8000de6: 43db mvns r3, r3
8000de8: 693a ldr r2, [r7, #16]
8000dea: 4013 ands r3, r2
8000dec: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8000dee: 683b ldr r3, [r7, #0]
8000df0: 689a ldr r2, [r3, #8]
8000df2: 697b ldr r3, [r7, #20]
8000df4: 005b lsls r3, r3, #1
8000df6: fa02 f303 lsl.w r3, r2, r3
8000dfa: 693a ldr r2, [r7, #16]
8000dfc: 4313 orrs r3, r2
8000dfe: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8000e00: 687b ldr r3, [r7, #4]
8000e02: 693a ldr r2, [r7, #16]
8000e04: 60da str r2, [r3, #12]
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
8000e06: 683b ldr r3, [r7, #0]
8000e08: 685b ldr r3, [r3, #4]
8000e0a: 2b02 cmp r3, #2
8000e0c: d003 beq.n 8000e16 <HAL_GPIO_Init+0xea>
8000e0e: 683b ldr r3, [r7, #0]
8000e10: 685b ldr r3, [r3, #4]
8000e12: 2b12 cmp r3, #18
8000e14: d123 bne.n 8000e5e <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8000e16: 697b ldr r3, [r7, #20]
8000e18: 08da lsrs r2, r3, #3
8000e1a: 687b ldr r3, [r7, #4]
8000e1c: 3208 adds r2, #8
8000e1e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8000e22: 613b str r3, [r7, #16]
temp &= ~(0xFU << ((position & 0x07U) * 4U));
8000e24: 697b ldr r3, [r7, #20]
8000e26: f003 0307 and.w r3, r3, #7
8000e2a: 009b lsls r3, r3, #2
8000e2c: 220f movs r2, #15
8000e2e: fa02 f303 lsl.w r3, r2, r3
8000e32: 43db mvns r3, r3
8000e34: 693a ldr r2, [r7, #16]
8000e36: 4013 ands r3, r2
8000e38: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
8000e3a: 683b ldr r3, [r7, #0]
8000e3c: 691a ldr r2, [r3, #16]
8000e3e: 697b ldr r3, [r7, #20]
8000e40: f003 0307 and.w r3, r3, #7
8000e44: 009b lsls r3, r3, #2
8000e46: fa02 f303 lsl.w r3, r2, r3
8000e4a: 693a ldr r2, [r7, #16]
8000e4c: 4313 orrs r3, r2
8000e4e: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3U] = temp;
8000e50: 697b ldr r3, [r7, #20]
8000e52: 08da lsrs r2, r3, #3
8000e54: 687b ldr r3, [r7, #4]
8000e56: 3208 adds r2, #8
8000e58: 6939 ldr r1, [r7, #16]
8000e5a: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8000e5e: 687b ldr r3, [r7, #4]
8000e60: 681b ldr r3, [r3, #0]
8000e62: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
8000e64: 697b ldr r3, [r7, #20]
8000e66: 005b lsls r3, r3, #1
8000e68: 2203 movs r2, #3
8000e6a: fa02 f303 lsl.w r3, r2, r3
8000e6e: 43db mvns r3, r3
8000e70: 693a ldr r2, [r7, #16]
8000e72: 4013 ands r3, r2
8000e74: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8000e76: 683b ldr r3, [r7, #0]
8000e78: 685b ldr r3, [r3, #4]
8000e7a: f003 0203 and.w r2, r3, #3
8000e7e: 697b ldr r3, [r7, #20]
8000e80: 005b lsls r3, r3, #1
8000e82: fa02 f303 lsl.w r3, r2, r3
8000e86: 693a ldr r2, [r7, #16]
8000e88: 4313 orrs r3, r2
8000e8a: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8000e8c: 687b ldr r3, [r7, #4]
8000e8e: 693a ldr r2, [r7, #16]
8000e90: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
8000e92: 683b ldr r3, [r7, #0]
8000e94: 685b ldr r3, [r3, #4]
8000e96: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000e9a: 2b00 cmp r3, #0
8000e9c: f000 80a6 beq.w 8000fec <HAL_GPIO_Init+0x2c0>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000ea0: 4b5b ldr r3, [pc, #364] ; (8001010 <HAL_GPIO_Init+0x2e4>)
8000ea2: 6e1b ldr r3, [r3, #96] ; 0x60
8000ea4: 4a5a ldr r2, [pc, #360] ; (8001010 <HAL_GPIO_Init+0x2e4>)
8000ea6: f043 0301 orr.w r3, r3, #1
8000eaa: 6613 str r3, [r2, #96] ; 0x60
8000eac: 4b58 ldr r3, [pc, #352] ; (8001010 <HAL_GPIO_Init+0x2e4>)
8000eae: 6e1b ldr r3, [r3, #96] ; 0x60
8000eb0: f003 0301 and.w r3, r3, #1
8000eb4: 60bb str r3, [r7, #8]
8000eb6: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2U];
8000eb8: 4a56 ldr r2, [pc, #344] ; (8001014 <HAL_GPIO_Init+0x2e8>)
8000eba: 697b ldr r3, [r7, #20]
8000ebc: 089b lsrs r3, r3, #2
8000ebe: 3302 adds r3, #2
8000ec0: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8000ec4: 613b str r3, [r7, #16]
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
8000ec6: 697b ldr r3, [r7, #20]
8000ec8: f003 0303 and.w r3, r3, #3
8000ecc: 009b lsls r3, r3, #2
8000ece: 220f movs r2, #15
8000ed0: fa02 f303 lsl.w r3, r2, r3
8000ed4: 43db mvns r3, r3
8000ed6: 693a ldr r2, [r7, #16]
8000ed8: 4013 ands r3, r2
8000eda: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
8000edc: 687b ldr r3, [r7, #4]
8000ede: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000
8000ee2: d01f beq.n 8000f24 <HAL_GPIO_Init+0x1f8>
8000ee4: 687b ldr r3, [r7, #4]
8000ee6: 4a4c ldr r2, [pc, #304] ; (8001018 <HAL_GPIO_Init+0x2ec>)
8000ee8: 4293 cmp r3, r2
8000eea: d019 beq.n 8000f20 <HAL_GPIO_Init+0x1f4>
8000eec: 687b ldr r3, [r7, #4]
8000eee: 4a4b ldr r2, [pc, #300] ; (800101c <HAL_GPIO_Init+0x2f0>)
8000ef0: 4293 cmp r3, r2
8000ef2: d013 beq.n 8000f1c <HAL_GPIO_Init+0x1f0>
8000ef4: 687b ldr r3, [r7, #4]
8000ef6: 4a4a ldr r2, [pc, #296] ; (8001020 <HAL_GPIO_Init+0x2f4>)
8000ef8: 4293 cmp r3, r2
8000efa: d00d beq.n 8000f18 <HAL_GPIO_Init+0x1ec>
8000efc: 687b ldr r3, [r7, #4]
8000efe: 4a49 ldr r2, [pc, #292] ; (8001024 <HAL_GPIO_Init+0x2f8>)
8000f00: 4293 cmp r3, r2
8000f02: d007 beq.n 8000f14 <HAL_GPIO_Init+0x1e8>
8000f04: 687b ldr r3, [r7, #4]
8000f06: 4a48 ldr r2, [pc, #288] ; (8001028 <HAL_GPIO_Init+0x2fc>)
8000f08: 4293 cmp r3, r2
8000f0a: d101 bne.n 8000f10 <HAL_GPIO_Init+0x1e4>
8000f0c: 2305 movs r3, #5
8000f0e: e00a b.n 8000f26 <HAL_GPIO_Init+0x1fa>
8000f10: 2306 movs r3, #6
8000f12: e008 b.n 8000f26 <HAL_GPIO_Init+0x1fa>
8000f14: 2304 movs r3, #4
8000f16: e006 b.n 8000f26 <HAL_GPIO_Init+0x1fa>
8000f18: 2303 movs r3, #3
8000f1a: e004 b.n 8000f26 <HAL_GPIO_Init+0x1fa>
8000f1c: 2302 movs r3, #2
8000f1e: e002 b.n 8000f26 <HAL_GPIO_Init+0x1fa>
8000f20: 2301 movs r3, #1
8000f22: e000 b.n 8000f26 <HAL_GPIO_Init+0x1fa>
8000f24: 2300 movs r3, #0
8000f26: 697a ldr r2, [r7, #20]
8000f28: f002 0203 and.w r2, r2, #3
8000f2c: 0092 lsls r2, r2, #2
8000f2e: 4093 lsls r3, r2
8000f30: 693a ldr r2, [r7, #16]
8000f32: 4313 orrs r3, r2
8000f34: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2U] = temp;
8000f36: 4937 ldr r1, [pc, #220] ; (8001014 <HAL_GPIO_Init+0x2e8>)
8000f38: 697b ldr r3, [r7, #20]
8000f3a: 089b lsrs r3, r3, #2
8000f3c: 3302 adds r3, #2
8000f3e: 693a ldr r2, [r7, #16]
8000f40: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear EXTI line configuration */
temp = EXTI->IMR1;
8000f44: 4b39 ldr r3, [pc, #228] ; (800102c <HAL_GPIO_Init+0x300>)
8000f46: 681b ldr r3, [r3, #0]
8000f48: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000f4a: 68fb ldr r3, [r7, #12]
8000f4c: 43db mvns r3, r3
8000f4e: 693a ldr r2, [r7, #16]
8000f50: 4013 ands r3, r2
8000f52: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8000f54: 683b ldr r3, [r7, #0]
8000f56: 685b ldr r3, [r3, #4]
8000f58: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000f5c: 2b00 cmp r3, #0
8000f5e: d003 beq.n 8000f68 <HAL_GPIO_Init+0x23c>
{
temp |= iocurrent;
8000f60: 693a ldr r2, [r7, #16]
8000f62: 68fb ldr r3, [r7, #12]
8000f64: 4313 orrs r3, r2
8000f66: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
8000f68: 4a30 ldr r2, [pc, #192] ; (800102c <HAL_GPIO_Init+0x300>)
8000f6a: 693b ldr r3, [r7, #16]
8000f6c: 6013 str r3, [r2, #0]
temp = EXTI->EMR1;
8000f6e: 4b2f ldr r3, [pc, #188] ; (800102c <HAL_GPIO_Init+0x300>)
8000f70: 685b ldr r3, [r3, #4]
8000f72: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000f74: 68fb ldr r3, [r7, #12]
8000f76: 43db mvns r3, r3
8000f78: 693a ldr r2, [r7, #16]
8000f7a: 4013 ands r3, r2
8000f7c: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8000f7e: 683b ldr r3, [r7, #0]
8000f80: 685b ldr r3, [r3, #4]
8000f82: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000f86: 2b00 cmp r3, #0
8000f88: d003 beq.n 8000f92 <HAL_GPIO_Init+0x266>
{
temp |= iocurrent;
8000f8a: 693a ldr r2, [r7, #16]
8000f8c: 68fb ldr r3, [r7, #12]
8000f8e: 4313 orrs r3, r2
8000f90: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
8000f92: 4a26 ldr r2, [pc, #152] ; (800102c <HAL_GPIO_Init+0x300>)
8000f94: 693b ldr r3, [r7, #16]
8000f96: 6053 str r3, [r2, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
8000f98: 4b24 ldr r3, [pc, #144] ; (800102c <HAL_GPIO_Init+0x300>)
8000f9a: 689b ldr r3, [r3, #8]
8000f9c: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000f9e: 68fb ldr r3, [r7, #12]
8000fa0: 43db mvns r3, r3
8000fa2: 693a ldr r2, [r7, #16]
8000fa4: 4013 ands r3, r2
8000fa6: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8000fa8: 683b ldr r3, [r7, #0]
8000faa: 685b ldr r3, [r3, #4]
8000fac: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8000fb0: 2b00 cmp r3, #0
8000fb2: d003 beq.n 8000fbc <HAL_GPIO_Init+0x290>
{
temp |= iocurrent;
8000fb4: 693a ldr r2, [r7, #16]
8000fb6: 68fb ldr r3, [r7, #12]
8000fb8: 4313 orrs r3, r2
8000fba: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
8000fbc: 4a1b ldr r2, [pc, #108] ; (800102c <HAL_GPIO_Init+0x300>)
8000fbe: 693b ldr r3, [r7, #16]
8000fc0: 6093 str r3, [r2, #8]
temp = EXTI->FTSR1;
8000fc2: 4b1a ldr r3, [pc, #104] ; (800102c <HAL_GPIO_Init+0x300>)
8000fc4: 68db ldr r3, [r3, #12]
8000fc6: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000fc8: 68fb ldr r3, [r7, #12]
8000fca: 43db mvns r3, r3
8000fcc: 693a ldr r2, [r7, #16]
8000fce: 4013 ands r3, r2
8000fd0: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8000fd2: 683b ldr r3, [r7, #0]
8000fd4: 685b ldr r3, [r3, #4]
8000fd6: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8000fda: 2b00 cmp r3, #0
8000fdc: d003 beq.n 8000fe6 <HAL_GPIO_Init+0x2ba>
{
temp |= iocurrent;
8000fde: 693a ldr r2, [r7, #16]
8000fe0: 68fb ldr r3, [r7, #12]
8000fe2: 4313 orrs r3, r2
8000fe4: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
8000fe6: 4a11 ldr r2, [pc, #68] ; (800102c <HAL_GPIO_Init+0x300>)
8000fe8: 693b ldr r3, [r7, #16]
8000fea: 60d3 str r3, [r2, #12]
}
}
position++;
8000fec: 697b ldr r3, [r7, #20]
8000fee: 3301 adds r3, #1
8000ff0: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0U)
8000ff2: 683b ldr r3, [r7, #0]
8000ff4: 681a ldr r2, [r3, #0]
8000ff6: 697b ldr r3, [r7, #20]
8000ff8: fa22 f303 lsr.w r3, r2, r3
8000ffc: 2b00 cmp r3, #0
8000ffe: f47f ae9d bne.w 8000d3c <HAL_GPIO_Init+0x10>
}
}
8001002: bf00 nop
8001004: bf00 nop
8001006: 371c adds r7, #28
8001008: 46bd mov sp, r7
800100a: f85d 7b04 ldr.w r7, [sp], #4
800100e: 4770 bx lr
8001010: 40021000 .word 0x40021000
8001014: 40010000 .word 0x40010000
8001018: 48000400 .word 0x48000400
800101c: 48000800 .word 0x48000800
8001020: 48000c00 .word 0x48000c00
8001024: 48001000 .word 0x48001000
8001028: 48001400 .word 0x48001400
800102c: 40010400 .word 0x40010400
08001030 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001030: b480 push {r7}
8001032: b083 sub sp, #12
8001034: af00 add r7, sp, #0
8001036: 6078 str r0, [r7, #4]
8001038: 460b mov r3, r1
800103a: 807b strh r3, [r7, #2]
800103c: 4613 mov r3, r2
800103e: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8001040: 787b ldrb r3, [r7, #1]
8001042: 2b00 cmp r3, #0
8001044: d003 beq.n 800104e <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8001046: 887a ldrh r2, [r7, #2]
8001048: 687b ldr r3, [r7, #4]
800104a: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
800104c: e002 b.n 8001054 <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
800104e: 887a ldrh r2, [r7, #2]
8001050: 687b ldr r3, [r7, #4]
8001052: 629a str r2, [r3, #40] ; 0x28
}
8001054: bf00 nop
8001056: 370c adds r7, #12
8001058: 46bd mov sp, r7
800105a: f85d 7b04 ldr.w r7, [sp], #4
800105e: 4770 bx lr
08001060 <HAL_GPIO_EXTI_IRQHandler>:
* @brief Handle EXTI interrupt request.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
8001060: b580 push {r7, lr}
8001062: b082 sub sp, #8
8001064: af00 add r7, sp, #0
8001066: 4603 mov r3, r0
8001068: 80fb strh r3, [r7, #6]
/* EXTI line interrupt detected */
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
800106a: 4b08 ldr r3, [pc, #32] ; (800108c <HAL_GPIO_EXTI_IRQHandler+0x2c>)
800106c: 695a ldr r2, [r3, #20]
800106e: 88fb ldrh r3, [r7, #6]
8001070: 4013 ands r3, r2
8001072: 2b00 cmp r3, #0
8001074: d006 beq.n 8001084 <HAL_GPIO_EXTI_IRQHandler+0x24>
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
8001076: 4a05 ldr r2, [pc, #20] ; (800108c <HAL_GPIO_EXTI_IRQHandler+0x2c>)
8001078: 88fb ldrh r3, [r7, #6]
800107a: 6153 str r3, [r2, #20]
HAL_GPIO_EXTI_Callback(GPIO_Pin);
800107c: 88fb ldrh r3, [r7, #6]
800107e: 4618 mov r0, r3
8001080: f000 f806 bl 8001090 <HAL_GPIO_EXTI_Callback>
}
}
8001084: bf00 nop
8001086: 3708 adds r7, #8
8001088: 46bd mov sp, r7
800108a: bd80 pop {r7, pc}
800108c: 40010400 .word 0x40010400
08001090 <HAL_GPIO_EXTI_Callback>:
* @brief EXTI line detection callback.
* @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
8001090: b480 push {r7}
8001092: b083 sub sp, #12
8001094: af00 add r7, sp, #0
8001096: 4603 mov r3, r0
8001098: 80fb strh r3, [r7, #6]
UNUSED(GPIO_Pin);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
800109a: bf00 nop
800109c: 370c adds r7, #12
800109e: 46bd mov sp, r7
80010a0: f85d 7b04 ldr.w r7, [sp], #4
80010a4: 4770 bx lr
080010a6 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
80010a6: b580 push {r7, lr}
80010a8: b082 sub sp, #8
80010aa: af00 add r7, sp, #0
80010ac: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
80010ae: 687b ldr r3, [r7, #4]
80010b0: 2b00 cmp r3, #0
80010b2: d101 bne.n 80010b8 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
80010b4: 2301 movs r3, #1
80010b6: e081 b.n 80011bc <HAL_I2C_Init+0x116>
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
80010b8: 687b ldr r3, [r7, #4]
80010ba: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
80010be: b2db uxtb r3, r3
80010c0: 2b00 cmp r3, #0
80010c2: d106 bne.n 80010d2 <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
80010c4: 687b ldr r3, [r7, #4]
80010c6: 2200 movs r2, #0
80010c8: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
80010cc: 6878 ldr r0, [r7, #4]
80010ce: f7ff facf bl 8000670 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
80010d2: 687b ldr r3, [r7, #4]
80010d4: 2224 movs r2, #36 ; 0x24
80010d6: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
80010da: 687b ldr r3, [r7, #4]
80010dc: 681b ldr r3, [r3, #0]
80010de: 681a ldr r2, [r3, #0]
80010e0: 687b ldr r3, [r7, #4]
80010e2: 681b ldr r3, [r3, #0]
80010e4: f022 0201 bic.w r2, r2, #1
80010e8: 601a str r2, [r3, #0]
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
80010ea: 687b ldr r3, [r7, #4]
80010ec: 685a ldr r2, [r3, #4]
80010ee: 687b ldr r3, [r7, #4]
80010f0: 681b ldr r3, [r3, #0]
80010f2: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
80010f6: 611a str r2, [r3, #16]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
80010f8: 687b ldr r3, [r7, #4]
80010fa: 681b ldr r3, [r3, #0]
80010fc: 689a ldr r2, [r3, #8]
80010fe: 687b ldr r3, [r7, #4]
8001100: 681b ldr r3, [r3, #0]
8001102: f422 4200 bic.w r2, r2, #32768 ; 0x8000
8001106: 609a str r2, [r3, #8]
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
8001108: 687b ldr r3, [r7, #4]
800110a: 68db ldr r3, [r3, #12]
800110c: 2b01 cmp r3, #1
800110e: d107 bne.n 8001120 <HAL_I2C_Init+0x7a>
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
8001110: 687b ldr r3, [r7, #4]
8001112: 689a ldr r2, [r3, #8]
8001114: 687b ldr r3, [r7, #4]
8001116: 681b ldr r3, [r3, #0]
8001118: f442 4200 orr.w r2, r2, #32768 ; 0x8000
800111c: 609a str r2, [r3, #8]
800111e: e006 b.n 800112e <HAL_I2C_Init+0x88>
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
8001120: 687b ldr r3, [r7, #4]
8001122: 689a ldr r2, [r3, #8]
8001124: 687b ldr r3, [r7, #4]
8001126: 681b ldr r3, [r3, #0]
8001128: f442 4204 orr.w r2, r2, #33792 ; 0x8400
800112c: 609a str r2, [r3, #8]
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
800112e: 687b ldr r3, [r7, #4]
8001130: 68db ldr r3, [r3, #12]
8001132: 2b02 cmp r3, #2
8001134: d104 bne.n 8001140 <HAL_I2C_Init+0x9a>
{
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
8001136: 687b ldr r3, [r7, #4]
8001138: 681b ldr r3, [r3, #0]
800113a: f44f 6200 mov.w r2, #2048 ; 0x800
800113e: 605a str r2, [r3, #4]
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
8001140: 687b ldr r3, [r7, #4]
8001142: 681b ldr r3, [r3, #0]
8001144: 685b ldr r3, [r3, #4]
8001146: 687a ldr r2, [r7, #4]
8001148: 6812 ldr r2, [r2, #0]
800114a: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
800114e: f443 4300 orr.w r3, r3, #32768 ; 0x8000
8001152: 6053 str r3, [r2, #4]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
8001154: 687b ldr r3, [r7, #4]
8001156: 681b ldr r3, [r3, #0]
8001158: 68da ldr r2, [r3, #12]
800115a: 687b ldr r3, [r7, #4]
800115c: 681b ldr r3, [r3, #0]
800115e: f422 4200 bic.w r2, r2, #32768 ; 0x8000
8001162: 60da str r2, [r3, #12]
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
8001164: 687b ldr r3, [r7, #4]
8001166: 691a ldr r2, [r3, #16]
8001168: 687b ldr r3, [r7, #4]
800116a: 695b ldr r3, [r3, #20]
800116c: ea42 0103 orr.w r1, r2, r3
8001170: 687b ldr r3, [r7, #4]
8001172: 699b ldr r3, [r3, #24]
8001174: 021a lsls r2, r3, #8
8001176: 687b ldr r3, [r7, #4]
8001178: 681b ldr r3, [r3, #0]
800117a: 430a orrs r2, r1
800117c: 60da str r2, [r3, #12]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
800117e: 687b ldr r3, [r7, #4]
8001180: 69d9 ldr r1, [r3, #28]
8001182: 687b ldr r3, [r7, #4]
8001184: 6a1a ldr r2, [r3, #32]
8001186: 687b ldr r3, [r7, #4]
8001188: 681b ldr r3, [r3, #0]
800118a: 430a orrs r2, r1
800118c: 601a str r2, [r3, #0]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
800118e: 687b ldr r3, [r7, #4]
8001190: 681b ldr r3, [r3, #0]
8001192: 681a ldr r2, [r3, #0]
8001194: 687b ldr r3, [r7, #4]
8001196: 681b ldr r3, [r3, #0]
8001198: f042 0201 orr.w r2, r2, #1
800119c: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
800119e: 687b ldr r3, [r7, #4]
80011a0: 2200 movs r2, #0
80011a2: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
80011a4: 687b ldr r3, [r7, #4]
80011a6: 2220 movs r2, #32
80011a8: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->PreviousState = I2C_STATE_NONE;
80011ac: 687b ldr r3, [r7, #4]
80011ae: 2200 movs r2, #0
80011b0: 631a str r2, [r3, #48] ; 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
80011b2: 687b ldr r3, [r7, #4]
80011b4: 2200 movs r2, #0
80011b6: f883 2042 strb.w r2, [r3, #66] ; 0x42
return HAL_OK;
80011ba: 2300 movs r3, #0
}
80011bc: 4618 mov r0, r3
80011be: 3708 adds r7, #8
80011c0: 46bd mov sp, r7
80011c2: bd80 pop {r7, pc}
080011c4 <HAL_I2CEx_ConfigAnalogFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
80011c4: b480 push {r7}
80011c6: b083 sub sp, #12
80011c8: af00 add r7, sp, #0
80011ca: 6078 str r0, [r7, #4]
80011cc: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
80011ce: 687b ldr r3, [r7, #4]
80011d0: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
80011d4: b2db uxtb r3, r3
80011d6: 2b20 cmp r3, #32
80011d8: d138 bne.n 800124c <HAL_I2CEx_ConfigAnalogFilter+0x88>
{
/* Process Locked */
__HAL_LOCK(hi2c);
80011da: 687b ldr r3, [r7, #4]
80011dc: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
80011e0: 2b01 cmp r3, #1
80011e2: d101 bne.n 80011e8 <HAL_I2CEx_ConfigAnalogFilter+0x24>
80011e4: 2302 movs r3, #2
80011e6: e032 b.n 800124e <HAL_I2CEx_ConfigAnalogFilter+0x8a>
80011e8: 687b ldr r3, [r7, #4]
80011ea: 2201 movs r2, #1
80011ec: f883 2040 strb.w r2, [r3, #64] ; 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
80011f0: 687b ldr r3, [r7, #4]
80011f2: 2224 movs r2, #36 ; 0x24
80011f4: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
80011f8: 687b ldr r3, [r7, #4]
80011fa: 681b ldr r3, [r3, #0]
80011fc: 681a ldr r2, [r3, #0]
80011fe: 687b ldr r3, [r7, #4]
8001200: 681b ldr r3, [r3, #0]
8001202: f022 0201 bic.w r2, r2, #1
8001206: 601a str r2, [r3, #0]
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
8001208: 687b ldr r3, [r7, #4]
800120a: 681b ldr r3, [r3, #0]
800120c: 681a ldr r2, [r3, #0]
800120e: 687b ldr r3, [r7, #4]
8001210: 681b ldr r3, [r3, #0]
8001212: f422 5280 bic.w r2, r2, #4096 ; 0x1000
8001216: 601a str r2, [r3, #0]
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
8001218: 687b ldr r3, [r7, #4]
800121a: 681b ldr r3, [r3, #0]
800121c: 6819 ldr r1, [r3, #0]
800121e: 687b ldr r3, [r7, #4]
8001220: 681b ldr r3, [r3, #0]
8001222: 683a ldr r2, [r7, #0]
8001224: 430a orrs r2, r1
8001226: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
8001228: 687b ldr r3, [r7, #4]
800122a: 681b ldr r3, [r3, #0]
800122c: 681a ldr r2, [r3, #0]
800122e: 687b ldr r3, [r7, #4]
8001230: 681b ldr r3, [r3, #0]
8001232: f042 0201 orr.w r2, r2, #1
8001236: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8001238: 687b ldr r3, [r7, #4]
800123a: 2220 movs r2, #32
800123c: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001240: 687b ldr r3, [r7, #4]
8001242: 2200 movs r2, #0
8001244: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
8001248: 2300 movs r3, #0
800124a: e000 b.n 800124e <HAL_I2CEx_ConfigAnalogFilter+0x8a>
}
else
{
return HAL_BUSY;
800124c: 2302 movs r3, #2
}
}
800124e: 4618 mov r0, r3
8001250: 370c adds r7, #12
8001252: 46bd mov sp, r7
8001254: f85d 7b04 ldr.w r7, [sp], #4
8001258: 4770 bx lr
0800125a <HAL_I2CEx_ConfigDigitalFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
800125a: b480 push {r7}
800125c: b085 sub sp, #20
800125e: af00 add r7, sp, #0
8001260: 6078 str r0, [r7, #4]
8001262: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
8001264: 687b ldr r3, [r7, #4]
8001266: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
800126a: b2db uxtb r3, r3
800126c: 2b20 cmp r3, #32
800126e: d139 bne.n 80012e4 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8001270: 687b ldr r3, [r7, #4]
8001272: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
8001276: 2b01 cmp r3, #1
8001278: d101 bne.n 800127e <HAL_I2CEx_ConfigDigitalFilter+0x24>
800127a: 2302 movs r3, #2
800127c: e033 b.n 80012e6 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
800127e: 687b ldr r3, [r7, #4]
8001280: 2201 movs r2, #1
8001282: f883 2040 strb.w r2, [r3, #64] ; 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
8001286: 687b ldr r3, [r7, #4]
8001288: 2224 movs r2, #36 ; 0x24
800128a: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
800128e: 687b ldr r3, [r7, #4]
8001290: 681b ldr r3, [r3, #0]
8001292: 681a ldr r2, [r3, #0]
8001294: 687b ldr r3, [r7, #4]
8001296: 681b ldr r3, [r3, #0]
8001298: f022 0201 bic.w r2, r2, #1
800129c: 601a str r2, [r3, #0]
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
800129e: 687b ldr r3, [r7, #4]
80012a0: 681b ldr r3, [r3, #0]
80012a2: 681b ldr r3, [r3, #0]
80012a4: 60fb str r3, [r7, #12]
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
80012a6: 68fb ldr r3, [r7, #12]
80012a8: f423 6370 bic.w r3, r3, #3840 ; 0xf00
80012ac: 60fb str r3, [r7, #12]
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
80012ae: 683b ldr r3, [r7, #0]
80012b0: 021b lsls r3, r3, #8
80012b2: 68fa ldr r2, [r7, #12]
80012b4: 4313 orrs r3, r2
80012b6: 60fb str r3, [r7, #12]
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
80012b8: 687b ldr r3, [r7, #4]
80012ba: 681b ldr r3, [r3, #0]
80012bc: 68fa ldr r2, [r7, #12]
80012be: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
80012c0: 687b ldr r3, [r7, #4]
80012c2: 681b ldr r3, [r3, #0]
80012c4: 681a ldr r2, [r3, #0]
80012c6: 687b ldr r3, [r7, #4]
80012c8: 681b ldr r3, [r3, #0]
80012ca: f042 0201 orr.w r2, r2, #1
80012ce: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
80012d0: 687b ldr r3, [r7, #4]
80012d2: 2220 movs r2, #32
80012d4: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80012d8: 687b ldr r3, [r7, #4]
80012da: 2200 movs r2, #0
80012dc: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
80012e0: 2300 movs r3, #0
80012e2: e000 b.n 80012e6 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
}
else
{
return HAL_BUSY;
80012e4: 2302 movs r3, #2
}
}
80012e6: 4618 mov r0, r3
80012e8: 3714 adds r7, #20
80012ea: 46bd mov sp, r7
80012ec: f85d 7b04 ldr.w r7, [sp], #4
80012f0: 4770 bx lr
...
080012f4 <HAL_PWREx_ControlVoltageScaling>:
* cleared before returning the status. If the flag is not cleared within
* 50 microseconds, HAL_TIMEOUT status is reported.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
80012f4: b480 push {r7}
80012f6: b085 sub sp, #20
80012f8: af00 add r7, sp, #0
80012fa: 6078 str r0, [r7, #4]
uint32_t wait_loop_index;
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
80012fc: 687b ldr r3, [r7, #4]
80012fe: 2b00 cmp r3, #0
8001300: d141 bne.n 8001386 <HAL_PWREx_ControlVoltageScaling+0x92>
{
/* If current range is range 2 */
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
8001302: 4b4b ldr r3, [pc, #300] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8001304: 681b ldr r3, [r3, #0]
8001306: f403 63c0 and.w r3, r3, #1536 ; 0x600
800130a: f5b3 6f80 cmp.w r3, #1024 ; 0x400
800130e: d131 bne.n 8001374 <HAL_PWREx_ControlVoltageScaling+0x80>
{
/* Make sure Range 1 Boost is enabled */
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
8001310: 4b47 ldr r3, [pc, #284] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8001312: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8001316: 4a46 ldr r2, [pc, #280] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8001318: f423 7380 bic.w r3, r3, #256 ; 0x100
800131c: f8c2 3080 str.w r3, [r2, #128] ; 0x80
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
8001320: 4b43 ldr r3, [pc, #268] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8001322: 681b ldr r3, [r3, #0]
8001324: f423 63c0 bic.w r3, r3, #1536 ; 0x600
8001328: 4a41 ldr r2, [pc, #260] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800132a: f443 7300 orr.w r3, r3, #512 ; 0x200
800132e: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
8001330: 4b40 ldr r3, [pc, #256] ; (8001434 <HAL_PWREx_ControlVoltageScaling+0x140>)
8001332: 681b ldr r3, [r3, #0]
8001334: 2232 movs r2, #50 ; 0x32
8001336: fb02 f303 mul.w r3, r2, r3
800133a: 4a3f ldr r2, [pc, #252] ; (8001438 <HAL_PWREx_ControlVoltageScaling+0x144>)
800133c: fba2 2303 umull r2, r3, r2, r3
8001340: 0c9b lsrs r3, r3, #18
8001342: 3301 adds r3, #1
8001344: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8001346: e002 b.n 800134e <HAL_PWREx_ControlVoltageScaling+0x5a>
{
wait_loop_index--;
8001348: 68fb ldr r3, [r7, #12]
800134a: 3b01 subs r3, #1
800134c: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
800134e: 4b38 ldr r3, [pc, #224] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8001350: 695b ldr r3, [r3, #20]
8001352: f403 6380 and.w r3, r3, #1024 ; 0x400
8001356: f5b3 6f80 cmp.w r3, #1024 ; 0x400
800135a: d102 bne.n 8001362 <HAL_PWREx_ControlVoltageScaling+0x6e>
800135c: 68fb ldr r3, [r7, #12]
800135e: 2b00 cmp r3, #0
8001360: d1f2 bne.n 8001348 <HAL_PWREx_ControlVoltageScaling+0x54>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
8001362: 4b33 ldr r3, [pc, #204] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8001364: 695b ldr r3, [r3, #20]
8001366: f403 6380 and.w r3, r3, #1024 ; 0x400
800136a: f5b3 6f80 cmp.w r3, #1024 ; 0x400
800136e: d158 bne.n 8001422 <HAL_PWREx_ControlVoltageScaling+0x12e>
{
return HAL_TIMEOUT;
8001370: 2303 movs r3, #3
8001372: e057 b.n 8001424 <HAL_PWREx_ControlVoltageScaling+0x130>
}
/* If current range is range 1 normal or boost mode */
else
{
/* Enable Range 1 Boost (no issue if bit already reset) */
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
8001374: 4b2e ldr r3, [pc, #184] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8001376: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
800137a: 4a2d ldr r2, [pc, #180] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800137c: f423 7380 bic.w r3, r3, #256 ; 0x100
8001380: f8c2 3080 str.w r3, [r2, #128] ; 0x80
8001384: e04d b.n 8001422 <HAL_PWREx_ControlVoltageScaling+0x12e>
}
}
else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
8001386: 687b ldr r3, [r7, #4]
8001388: f5b3 7f00 cmp.w r3, #512 ; 0x200
800138c: d141 bne.n 8001412 <HAL_PWREx_ControlVoltageScaling+0x11e>
{
/* If current range is range 2 */
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
800138e: 4b28 ldr r3, [pc, #160] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8001390: 681b ldr r3, [r3, #0]
8001392: f403 63c0 and.w r3, r3, #1536 ; 0x600
8001396: f5b3 6f80 cmp.w r3, #1024 ; 0x400
800139a: d131 bne.n 8001400 <HAL_PWREx_ControlVoltageScaling+0x10c>
{
/* Make sure Range 1 Boost is disabled */
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
800139c: 4b24 ldr r3, [pc, #144] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800139e: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
80013a2: 4a23 ldr r2, [pc, #140] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80013a4: f443 7380 orr.w r3, r3, #256 ; 0x100
80013a8: f8c2 3080 str.w r3, [r2, #128] ; 0x80
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
80013ac: 4b20 ldr r3, [pc, #128] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80013ae: 681b ldr r3, [r3, #0]
80013b0: f423 63c0 bic.w r3, r3, #1536 ; 0x600
80013b4: 4a1e ldr r2, [pc, #120] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80013b6: f443 7300 orr.w r3, r3, #512 ; 0x200
80013ba: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
80013bc: 4b1d ldr r3, [pc, #116] ; (8001434 <HAL_PWREx_ControlVoltageScaling+0x140>)
80013be: 681b ldr r3, [r3, #0]
80013c0: 2232 movs r2, #50 ; 0x32
80013c2: fb02 f303 mul.w r3, r2, r3
80013c6: 4a1c ldr r2, [pc, #112] ; (8001438 <HAL_PWREx_ControlVoltageScaling+0x144>)
80013c8: fba2 2303 umull r2, r3, r2, r3
80013cc: 0c9b lsrs r3, r3, #18
80013ce: 3301 adds r3, #1
80013d0: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
80013d2: e002 b.n 80013da <HAL_PWREx_ControlVoltageScaling+0xe6>
{
wait_loop_index--;
80013d4: 68fb ldr r3, [r7, #12]
80013d6: 3b01 subs r3, #1
80013d8: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
80013da: 4b15 ldr r3, [pc, #84] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80013dc: 695b ldr r3, [r3, #20]
80013de: f403 6380 and.w r3, r3, #1024 ; 0x400
80013e2: f5b3 6f80 cmp.w r3, #1024 ; 0x400
80013e6: d102 bne.n 80013ee <HAL_PWREx_ControlVoltageScaling+0xfa>
80013e8: 68fb ldr r3, [r7, #12]
80013ea: 2b00 cmp r3, #0
80013ec: d1f2 bne.n 80013d4 <HAL_PWREx_ControlVoltageScaling+0xe0>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
80013ee: 4b10 ldr r3, [pc, #64] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80013f0: 695b ldr r3, [r3, #20]
80013f2: f403 6380 and.w r3, r3, #1024 ; 0x400
80013f6: f5b3 6f80 cmp.w r3, #1024 ; 0x400
80013fa: d112 bne.n 8001422 <HAL_PWREx_ControlVoltageScaling+0x12e>
{
return HAL_TIMEOUT;
80013fc: 2303 movs r3, #3
80013fe: e011 b.n 8001424 <HAL_PWREx_ControlVoltageScaling+0x130>
}
/* If current range is range 1 normal or boost mode */
else
{
/* Disable Range 1 Boost (no issue if bit already set) */
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
8001400: 4b0b ldr r3, [pc, #44] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8001402: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8001406: 4a0a ldr r2, [pc, #40] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8001408: f443 7380 orr.w r3, r3, #256 ; 0x100
800140c: f8c2 3080 str.w r3, [r2, #128] ; 0x80
8001410: e007 b.n 8001422 <HAL_PWREx_ControlVoltageScaling+0x12e>
}
}
else
{
/* Set Range 2 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
8001412: 4b07 ldr r3, [pc, #28] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8001414: 681b ldr r3, [r3, #0]
8001416: f423 63c0 bic.w r3, r3, #1536 ; 0x600
800141a: 4a05 ldr r2, [pc, #20] ; (8001430 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800141c: f443 6380 orr.w r3, r3, #1024 ; 0x400
8001420: 6013 str r3, [r2, #0]
/* No need to wait for VOSF to be cleared for this transition */
/* PWR_CR5_R1MODE bit setting has no effect in Range 2 */
}
return HAL_OK;
8001422: 2300 movs r3, #0
}
8001424: 4618 mov r0, r3
8001426: 3714 adds r7, #20
8001428: 46bd mov sp, r7
800142a: f85d 7b04 ldr.w r7, [sp], #4
800142e: 4770 bx lr
8001430: 40007000 .word 0x40007000
8001434: 20000000 .word 0x20000000
8001438: 431bde83 .word 0x431bde83
0800143c <HAL_PWREx_DisableUCPDDeadBattery>:
* or to hand over control to the UCPD (which should therefore be
* initialized before doing the disable).
* @retval None
*/
void HAL_PWREx_DisableUCPDDeadBattery(void)
{
800143c: b480 push {r7}
800143e: af00 add r7, sp, #0
/* Write 1 to disable the USB Type-C dead battery pull-down behavior */
SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
8001440: 4b05 ldr r3, [pc, #20] ; (8001458 <HAL_PWREx_DisableUCPDDeadBattery+0x1c>)
8001442: 689b ldr r3, [r3, #8]
8001444: 4a04 ldr r2, [pc, #16] ; (8001458 <HAL_PWREx_DisableUCPDDeadBattery+0x1c>)
8001446: f443 4380 orr.w r3, r3, #16384 ; 0x4000
800144a: 6093 str r3, [r2, #8]
}
800144c: bf00 nop
800144e: 46bd mov sp, r7
8001450: f85d 7b04 ldr.w r7, [sp], #4
8001454: 4770 bx lr
8001456: bf00 nop
8001458: 40007000 .word 0x40007000
0800145c <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
800145c: b580 push {r7, lr}
800145e: b088 sub sp, #32
8001460: af00 add r7, sp, #0
8001462: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t temp_sysclksrc;
uint32_t temp_pllckcfg;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8001464: 687b ldr r3, [r7, #4]
8001466: 2b00 cmp r3, #0
8001468: d101 bne.n 800146e <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
800146a: 2301 movs r3, #1
800146c: e308 b.n 8001a80 <HAL_RCC_OscConfig+0x624>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
800146e: 687b ldr r3, [r7, #4]
8001470: 681b ldr r3, [r3, #0]
8001472: f003 0301 and.w r3, r3, #1
8001476: 2b00 cmp r3, #0
8001478: d075 beq.n 8001566 <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
800147a: 4ba3 ldr r3, [pc, #652] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
800147c: 689b ldr r3, [r3, #8]
800147e: f003 030c and.w r3, r3, #12
8001482: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
8001484: 4ba0 ldr r3, [pc, #640] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
8001486: 68db ldr r3, [r3, #12]
8001488: f003 0303 and.w r3, r3, #3
800148c: 617b str r3, [r7, #20]
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE))
800148e: 69bb ldr r3, [r7, #24]
8001490: 2b0c cmp r3, #12
8001492: d102 bne.n 800149a <HAL_RCC_OscConfig+0x3e>
8001494: 697b ldr r3, [r7, #20]
8001496: 2b03 cmp r3, #3
8001498: d002 beq.n 80014a0 <HAL_RCC_OscConfig+0x44>
800149a: 69bb ldr r3, [r7, #24]
800149c: 2b08 cmp r3, #8
800149e: d10b bne.n 80014b8 <HAL_RCC_OscConfig+0x5c>
{
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80014a0: 4b99 ldr r3, [pc, #612] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80014a2: 681b ldr r3, [r3, #0]
80014a4: f403 3300 and.w r3, r3, #131072 ; 0x20000
80014a8: 2b00 cmp r3, #0
80014aa: d05b beq.n 8001564 <HAL_RCC_OscConfig+0x108>
80014ac: 687b ldr r3, [r7, #4]
80014ae: 685b ldr r3, [r3, #4]
80014b0: 2b00 cmp r3, #0
80014b2: d157 bne.n 8001564 <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
80014b4: 2301 movs r3, #1
80014b6: e2e3 b.n 8001a80 <HAL_RCC_OscConfig+0x624>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80014b8: 687b ldr r3, [r7, #4]
80014ba: 685b ldr r3, [r3, #4]
80014bc: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80014c0: d106 bne.n 80014d0 <HAL_RCC_OscConfig+0x74>
80014c2: 4b91 ldr r3, [pc, #580] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80014c4: 681b ldr r3, [r3, #0]
80014c6: 4a90 ldr r2, [pc, #576] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80014c8: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80014cc: 6013 str r3, [r2, #0]
80014ce: e01d b.n 800150c <HAL_RCC_OscConfig+0xb0>
80014d0: 687b ldr r3, [r7, #4]
80014d2: 685b ldr r3, [r3, #4]
80014d4: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
80014d8: d10c bne.n 80014f4 <HAL_RCC_OscConfig+0x98>
80014da: 4b8b ldr r3, [pc, #556] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80014dc: 681b ldr r3, [r3, #0]
80014de: 4a8a ldr r2, [pc, #552] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80014e0: f443 2380 orr.w r3, r3, #262144 ; 0x40000
80014e4: 6013 str r3, [r2, #0]
80014e6: 4b88 ldr r3, [pc, #544] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80014e8: 681b ldr r3, [r3, #0]
80014ea: 4a87 ldr r2, [pc, #540] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80014ec: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80014f0: 6013 str r3, [r2, #0]
80014f2: e00b b.n 800150c <HAL_RCC_OscConfig+0xb0>
80014f4: 4b84 ldr r3, [pc, #528] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80014f6: 681b ldr r3, [r3, #0]
80014f8: 4a83 ldr r2, [pc, #524] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80014fa: f423 3380 bic.w r3, r3, #65536 ; 0x10000
80014fe: 6013 str r3, [r2, #0]
8001500: 4b81 ldr r3, [pc, #516] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
8001502: 681b ldr r3, [r3, #0]
8001504: 4a80 ldr r2, [pc, #512] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
8001506: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800150a: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
800150c: 687b ldr r3, [r7, #4]
800150e: 685b ldr r3, [r3, #4]
8001510: 2b00 cmp r3, #0
8001512: d013 beq.n 800153c <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001514: f7ff faee bl 8000af4 <HAL_GetTick>
8001518: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
800151a: e008 b.n 800152e <HAL_RCC_OscConfig+0xd2>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800151c: f7ff faea bl 8000af4 <HAL_GetTick>
8001520: 4602 mov r2, r0
8001522: 693b ldr r3, [r7, #16]
8001524: 1ad3 subs r3, r2, r3
8001526: 2b64 cmp r3, #100 ; 0x64
8001528: d901 bls.n 800152e <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
800152a: 2303 movs r3, #3
800152c: e2a8 b.n 8001a80 <HAL_RCC_OscConfig+0x624>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
800152e: 4b76 ldr r3, [pc, #472] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
8001530: 681b ldr r3, [r3, #0]
8001532: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001536: 2b00 cmp r3, #0
8001538: d0f0 beq.n 800151c <HAL_RCC_OscConfig+0xc0>
800153a: e014 b.n 8001566 <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800153c: f7ff fada bl 8000af4 <HAL_GetTick>
8001540: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8001542: e008 b.n 8001556 <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8001544: f7ff fad6 bl 8000af4 <HAL_GetTick>
8001548: 4602 mov r2, r0
800154a: 693b ldr r3, [r7, #16]
800154c: 1ad3 subs r3, r2, r3
800154e: 2b64 cmp r3, #100 ; 0x64
8001550: d901 bls.n 8001556 <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
8001552: 2303 movs r3, #3
8001554: e294 b.n 8001a80 <HAL_RCC_OscConfig+0x624>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8001556: 4b6c ldr r3, [pc, #432] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
8001558: 681b ldr r3, [r3, #0]
800155a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800155e: 2b00 cmp r3, #0
8001560: d1f0 bne.n 8001544 <HAL_RCC_OscConfig+0xe8>
8001562: e000 b.n 8001566 <HAL_RCC_OscConfig+0x10a>
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001564: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8001566: 687b ldr r3, [r7, #4]
8001568: 681b ldr r3, [r3, #0]
800156a: f003 0302 and.w r3, r3, #2
800156e: 2b00 cmp r3, #0
8001570: d075 beq.n 800165e <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8001572: 4b65 ldr r3, [pc, #404] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
8001574: 689b ldr r3, [r3, #8]
8001576: f003 030c and.w r3, r3, #12
800157a: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
800157c: 4b62 ldr r3, [pc, #392] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
800157e: 68db ldr r3, [r3, #12]
8001580: f003 0303 and.w r3, r3, #3
8001584: 617b str r3, [r7, #20]
if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI))
8001586: 69bb ldr r3, [r7, #24]
8001588: 2b0c cmp r3, #12
800158a: d102 bne.n 8001592 <HAL_RCC_OscConfig+0x136>
800158c: 697b ldr r3, [r7, #20]
800158e: 2b02 cmp r3, #2
8001590: d002 beq.n 8001598 <HAL_RCC_OscConfig+0x13c>
8001592: 69bb ldr r3, [r7, #24]
8001594: 2b04 cmp r3, #4
8001596: d11f bne.n 80015d8 <HAL_RCC_OscConfig+0x17c>
{
/* When HSI is used as system clock it will not be disabled */
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8001598: 4b5b ldr r3, [pc, #364] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
800159a: 681b ldr r3, [r3, #0]
800159c: f403 6380 and.w r3, r3, #1024 ; 0x400
80015a0: 2b00 cmp r3, #0
80015a2: d005 beq.n 80015b0 <HAL_RCC_OscConfig+0x154>
80015a4: 687b ldr r3, [r7, #4]
80015a6: 68db ldr r3, [r3, #12]
80015a8: 2b00 cmp r3, #0
80015aa: d101 bne.n 80015b0 <HAL_RCC_OscConfig+0x154>
{
return HAL_ERROR;
80015ac: 2301 movs r3, #1
80015ae: e267 b.n 8001a80 <HAL_RCC_OscConfig+0x624>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80015b0: 4b55 ldr r3, [pc, #340] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80015b2: 685b ldr r3, [r3, #4]
80015b4: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000
80015b8: 687b ldr r3, [r7, #4]
80015ba: 691b ldr r3, [r3, #16]
80015bc: 061b lsls r3, r3, #24
80015be: 4952 ldr r1, [pc, #328] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80015c0: 4313 orrs r3, r2
80015c2: 604b str r3, [r1, #4]
/* Adapt Systick interrupt period */
if (HAL_InitTick(uwTickPrio) != HAL_OK)
80015c4: 4b51 ldr r3, [pc, #324] ; (800170c <HAL_RCC_OscConfig+0x2b0>)
80015c6: 681b ldr r3, [r3, #0]
80015c8: 4618 mov r0, r3
80015ca: f7ff fa47 bl 8000a5c <HAL_InitTick>
80015ce: 4603 mov r3, r0
80015d0: 2b00 cmp r3, #0
80015d2: d043 beq.n 800165c <HAL_RCC_OscConfig+0x200>
{
return HAL_ERROR;
80015d4: 2301 movs r3, #1
80015d6: e253 b.n 8001a80 <HAL_RCC_OscConfig+0x624>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
80015d8: 687b ldr r3, [r7, #4]
80015da: 68db ldr r3, [r3, #12]
80015dc: 2b00 cmp r3, #0
80015de: d023 beq.n 8001628 <HAL_RCC_OscConfig+0x1cc>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
80015e0: 4b49 ldr r3, [pc, #292] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80015e2: 681b ldr r3, [r3, #0]
80015e4: 4a48 ldr r2, [pc, #288] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80015e6: f443 7380 orr.w r3, r3, #256 ; 0x100
80015ea: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80015ec: f7ff fa82 bl 8000af4 <HAL_GetTick>
80015f0: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
80015f2: e008 b.n 8001606 <HAL_RCC_OscConfig+0x1aa>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80015f4: f7ff fa7e bl 8000af4 <HAL_GetTick>
80015f8: 4602 mov r2, r0
80015fa: 693b ldr r3, [r7, #16]
80015fc: 1ad3 subs r3, r2, r3
80015fe: 2b02 cmp r3, #2
8001600: d901 bls.n 8001606 <HAL_RCC_OscConfig+0x1aa>
{
return HAL_TIMEOUT;
8001602: 2303 movs r3, #3
8001604: e23c b.n 8001a80 <HAL_RCC_OscConfig+0x624>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8001606: 4b40 ldr r3, [pc, #256] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
8001608: 681b ldr r3, [r3, #0]
800160a: f403 6380 and.w r3, r3, #1024 ; 0x400
800160e: 2b00 cmp r3, #0
8001610: d0f0 beq.n 80015f4 <HAL_RCC_OscConfig+0x198>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001612: 4b3d ldr r3, [pc, #244] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
8001614: 685b ldr r3, [r3, #4]
8001616: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000
800161a: 687b ldr r3, [r7, #4]
800161c: 691b ldr r3, [r3, #16]
800161e: 061b lsls r3, r3, #24
8001620: 4939 ldr r1, [pc, #228] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
8001622: 4313 orrs r3, r2
8001624: 604b str r3, [r1, #4]
8001626: e01a b.n 800165e <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001628: 4b37 ldr r3, [pc, #220] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
800162a: 681b ldr r3, [r3, #0]
800162c: 4a36 ldr r2, [pc, #216] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
800162e: f423 7380 bic.w r3, r3, #256 ; 0x100
8001632: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001634: f7ff fa5e bl 8000af4 <HAL_GetTick>
8001638: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
800163a: e008 b.n 800164e <HAL_RCC_OscConfig+0x1f2>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800163c: f7ff fa5a bl 8000af4 <HAL_GetTick>
8001640: 4602 mov r2, r0
8001642: 693b ldr r3, [r7, #16]
8001644: 1ad3 subs r3, r2, r3
8001646: 2b02 cmp r3, #2
8001648: d901 bls.n 800164e <HAL_RCC_OscConfig+0x1f2>
{
return HAL_TIMEOUT;
800164a: 2303 movs r3, #3
800164c: e218 b.n 8001a80 <HAL_RCC_OscConfig+0x624>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
800164e: 4b2e ldr r3, [pc, #184] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
8001650: 681b ldr r3, [r3, #0]
8001652: f403 6380 and.w r3, r3, #1024 ; 0x400
8001656: 2b00 cmp r3, #0
8001658: d1f0 bne.n 800163c <HAL_RCC_OscConfig+0x1e0>
800165a: e000 b.n 800165e <HAL_RCC_OscConfig+0x202>
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
800165c: bf00 nop
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
800165e: 687b ldr r3, [r7, #4]
8001660: 681b ldr r3, [r3, #0]
8001662: f003 0308 and.w r3, r3, #8
8001666: 2b00 cmp r3, #0
8001668: d03c beq.n 80016e4 <HAL_RCC_OscConfig+0x288>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
800166a: 687b ldr r3, [r7, #4]
800166c: 695b ldr r3, [r3, #20]
800166e: 2b00 cmp r3, #0
8001670: d01c beq.n 80016ac <HAL_RCC_OscConfig+0x250>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001672: 4b25 ldr r3, [pc, #148] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
8001674: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
8001678: 4a23 ldr r2, [pc, #140] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
800167a: f043 0301 orr.w r3, r3, #1
800167e: f8c2 3094 str.w r3, [r2, #148] ; 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001682: f7ff fa37 bl 8000af4 <HAL_GetTick>
8001686: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8001688: e008 b.n 800169c <HAL_RCC_OscConfig+0x240>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800168a: f7ff fa33 bl 8000af4 <HAL_GetTick>
800168e: 4602 mov r2, r0
8001690: 693b ldr r3, [r7, #16]
8001692: 1ad3 subs r3, r2, r3
8001694: 2b02 cmp r3, #2
8001696: d901 bls.n 800169c <HAL_RCC_OscConfig+0x240>
{
return HAL_TIMEOUT;
8001698: 2303 movs r3, #3
800169a: e1f1 b.n 8001a80 <HAL_RCC_OscConfig+0x624>
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
800169c: 4b1a ldr r3, [pc, #104] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
800169e: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
80016a2: f003 0302 and.w r3, r3, #2
80016a6: 2b00 cmp r3, #0
80016a8: d0ef beq.n 800168a <HAL_RCC_OscConfig+0x22e>
80016aa: e01b b.n 80016e4 <HAL_RCC_OscConfig+0x288>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80016ac: 4b16 ldr r3, [pc, #88] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80016ae: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
80016b2: 4a15 ldr r2, [pc, #84] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80016b4: f023 0301 bic.w r3, r3, #1
80016b8: f8c2 3094 str.w r3, [r2, #148] ; 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
80016bc: f7ff fa1a bl 8000af4 <HAL_GetTick>
80016c0: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
80016c2: e008 b.n 80016d6 <HAL_RCC_OscConfig+0x27a>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80016c4: f7ff fa16 bl 8000af4 <HAL_GetTick>
80016c8: 4602 mov r2, r0
80016ca: 693b ldr r3, [r7, #16]
80016cc: 1ad3 subs r3, r2, r3
80016ce: 2b02 cmp r3, #2
80016d0: d901 bls.n 80016d6 <HAL_RCC_OscConfig+0x27a>
{
return HAL_TIMEOUT;
80016d2: 2303 movs r3, #3
80016d4: e1d4 b.n 8001a80 <HAL_RCC_OscConfig+0x624>
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
80016d6: 4b0c ldr r3, [pc, #48] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80016d8: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
80016dc: f003 0302 and.w r3, r3, #2
80016e0: 2b00 cmp r3, #0
80016e2: d1ef bne.n 80016c4 <HAL_RCC_OscConfig+0x268>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
80016e4: 687b ldr r3, [r7, #4]
80016e6: 681b ldr r3, [r3, #0]
80016e8: f003 0304 and.w r3, r3, #4
80016ec: 2b00 cmp r3, #0
80016ee: f000 80ab beq.w 8001848 <HAL_RCC_OscConfig+0x3ec>
{
FlagStatus pwrclkchanged = RESET;
80016f2: 2300 movs r3, #0
80016f4: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain if necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
80016f6: 4b04 ldr r3, [pc, #16] ; (8001708 <HAL_RCC_OscConfig+0x2ac>)
80016f8: 6d9b ldr r3, [r3, #88] ; 0x58
80016fa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80016fe: 2b00 cmp r3, #0
8001700: d106 bne.n 8001710 <HAL_RCC_OscConfig+0x2b4>
8001702: 2301 movs r3, #1
8001704: e005 b.n 8001712 <HAL_RCC_OscConfig+0x2b6>
8001706: bf00 nop
8001708: 40021000 .word 0x40021000
800170c: 20000004 .word 0x20000004
8001710: 2300 movs r3, #0
8001712: 2b00 cmp r3, #0
8001714: d00d beq.n 8001732 <HAL_RCC_OscConfig+0x2d6>
{
__HAL_RCC_PWR_CLK_ENABLE();
8001716: 4baf ldr r3, [pc, #700] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
8001718: 6d9b ldr r3, [r3, #88] ; 0x58
800171a: 4aae ldr r2, [pc, #696] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
800171c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8001720: 6593 str r3, [r2, #88] ; 0x58
8001722: 4bac ldr r3, [pc, #688] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
8001724: 6d9b ldr r3, [r3, #88] ; 0x58
8001726: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800172a: 60fb str r3, [r7, #12]
800172c: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
800172e: 2301 movs r3, #1
8001730: 77fb strb r3, [r7, #31]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001732: 4ba9 ldr r3, [pc, #676] ; (80019d8 <HAL_RCC_OscConfig+0x57c>)
8001734: 681b ldr r3, [r3, #0]
8001736: f403 7380 and.w r3, r3, #256 ; 0x100
800173a: 2b00 cmp r3, #0
800173c: d118 bne.n 8001770 <HAL_RCC_OscConfig+0x314>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
800173e: 4ba6 ldr r3, [pc, #664] ; (80019d8 <HAL_RCC_OscConfig+0x57c>)
8001740: 681b ldr r3, [r3, #0]
8001742: 4aa5 ldr r2, [pc, #660] ; (80019d8 <HAL_RCC_OscConfig+0x57c>)
8001744: f443 7380 orr.w r3, r3, #256 ; 0x100
8001748: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800174a: f7ff f9d3 bl 8000af4 <HAL_GetTick>
800174e: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001750: e008 b.n 8001764 <HAL_RCC_OscConfig+0x308>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001752: f7ff f9cf bl 8000af4 <HAL_GetTick>
8001756: 4602 mov r2, r0
8001758: 693b ldr r3, [r7, #16]
800175a: 1ad3 subs r3, r2, r3
800175c: 2b02 cmp r3, #2
800175e: d901 bls.n 8001764 <HAL_RCC_OscConfig+0x308>
{
return HAL_TIMEOUT;
8001760: 2303 movs r3, #3
8001762: e18d b.n 8001a80 <HAL_RCC_OscConfig+0x624>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001764: 4b9c ldr r3, [pc, #624] ; (80019d8 <HAL_RCC_OscConfig+0x57c>)
8001766: 681b ldr r3, [r3, #0]
8001768: f403 7380 and.w r3, r3, #256 ; 0x100
800176c: 2b00 cmp r3, #0
800176e: d0f0 beq.n 8001752 <HAL_RCC_OscConfig+0x2f6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001770: 687b ldr r3, [r7, #4]
8001772: 689b ldr r3, [r3, #8]
8001774: 2b01 cmp r3, #1
8001776: d108 bne.n 800178a <HAL_RCC_OscConfig+0x32e>
8001778: 4b96 ldr r3, [pc, #600] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
800177a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800177e: 4a95 ldr r2, [pc, #596] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
8001780: f043 0301 orr.w r3, r3, #1
8001784: f8c2 3090 str.w r3, [r2, #144] ; 0x90
8001788: e024 b.n 80017d4 <HAL_RCC_OscConfig+0x378>
800178a: 687b ldr r3, [r7, #4]
800178c: 689b ldr r3, [r3, #8]
800178e: 2b05 cmp r3, #5
8001790: d110 bne.n 80017b4 <HAL_RCC_OscConfig+0x358>
8001792: 4b90 ldr r3, [pc, #576] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
8001794: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8001798: 4a8e ldr r2, [pc, #568] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
800179a: f043 0304 orr.w r3, r3, #4
800179e: f8c2 3090 str.w r3, [r2, #144] ; 0x90
80017a2: 4b8c ldr r3, [pc, #560] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80017a4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80017a8: 4a8a ldr r2, [pc, #552] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80017aa: f043 0301 orr.w r3, r3, #1
80017ae: f8c2 3090 str.w r3, [r2, #144] ; 0x90
80017b2: e00f b.n 80017d4 <HAL_RCC_OscConfig+0x378>
80017b4: 4b87 ldr r3, [pc, #540] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80017b6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80017ba: 4a86 ldr r2, [pc, #536] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80017bc: f023 0301 bic.w r3, r3, #1
80017c0: f8c2 3090 str.w r3, [r2, #144] ; 0x90
80017c4: 4b83 ldr r3, [pc, #524] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80017c6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80017ca: 4a82 ldr r2, [pc, #520] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80017cc: f023 0304 bic.w r3, r3, #4
80017d0: f8c2 3090 str.w r3, [r2, #144] ; 0x90
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
80017d4: 687b ldr r3, [r7, #4]
80017d6: 689b ldr r3, [r3, #8]
80017d8: 2b00 cmp r3, #0
80017da: d016 beq.n 800180a <HAL_RCC_OscConfig+0x3ae>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80017dc: f7ff f98a bl 8000af4 <HAL_GetTick>
80017e0: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
80017e2: e00a b.n 80017fa <HAL_RCC_OscConfig+0x39e>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80017e4: f7ff f986 bl 8000af4 <HAL_GetTick>
80017e8: 4602 mov r2, r0
80017ea: 693b ldr r3, [r7, #16]
80017ec: 1ad3 subs r3, r2, r3
80017ee: f241 3288 movw r2, #5000 ; 0x1388
80017f2: 4293 cmp r3, r2
80017f4: d901 bls.n 80017fa <HAL_RCC_OscConfig+0x39e>
{
return HAL_TIMEOUT;
80017f6: 2303 movs r3, #3
80017f8: e142 b.n 8001a80 <HAL_RCC_OscConfig+0x624>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
80017fa: 4b76 ldr r3, [pc, #472] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80017fc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8001800: f003 0302 and.w r3, r3, #2
8001804: 2b00 cmp r3, #0
8001806: d0ed beq.n 80017e4 <HAL_RCC_OscConfig+0x388>
8001808: e015 b.n 8001836 <HAL_RCC_OscConfig+0x3da>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800180a: f7ff f973 bl 8000af4 <HAL_GetTick>
800180e: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8001810: e00a b.n 8001828 <HAL_RCC_OscConfig+0x3cc>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8001812: f7ff f96f bl 8000af4 <HAL_GetTick>
8001816: 4602 mov r2, r0
8001818: 693b ldr r3, [r7, #16]
800181a: 1ad3 subs r3, r2, r3
800181c: f241 3288 movw r2, #5000 ; 0x1388
8001820: 4293 cmp r3, r2
8001822: d901 bls.n 8001828 <HAL_RCC_OscConfig+0x3cc>
{
return HAL_TIMEOUT;
8001824: 2303 movs r3, #3
8001826: e12b b.n 8001a80 <HAL_RCC_OscConfig+0x624>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8001828: 4b6a ldr r3, [pc, #424] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
800182a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800182e: f003 0302 and.w r3, r3, #2
8001832: 2b00 cmp r3, #0
8001834: d1ed bne.n 8001812 <HAL_RCC_OscConfig+0x3b6>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
8001836: 7ffb ldrb r3, [r7, #31]
8001838: 2b01 cmp r3, #1
800183a: d105 bne.n 8001848 <HAL_RCC_OscConfig+0x3ec>
{
__HAL_RCC_PWR_CLK_DISABLE();
800183c: 4b65 ldr r3, [pc, #404] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
800183e: 6d9b ldr r3, [r3, #88] ; 0x58
8001840: 4a64 ldr r2, [pc, #400] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
8001842: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8001846: 6593 str r3, [r2, #88] ; 0x58
}
}
/*------------------------------ HSI48 Configuration -----------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
8001848: 687b ldr r3, [r7, #4]
800184a: 681b ldr r3, [r3, #0]
800184c: f003 0320 and.w r3, r3, #32
8001850: 2b00 cmp r3, #0
8001852: d03c beq.n 80018ce <HAL_RCC_OscConfig+0x472>
{
/* Check the parameters */
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
/* Check the HSI48 State */
if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
8001854: 687b ldr r3, [r7, #4]
8001856: 699b ldr r3, [r3, #24]
8001858: 2b00 cmp r3, #0
800185a: d01c beq.n 8001896 <HAL_RCC_OscConfig+0x43a>
{
/* Enable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_ENABLE();
800185c: 4b5d ldr r3, [pc, #372] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
800185e: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
8001862: 4a5c ldr r2, [pc, #368] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
8001864: f043 0301 orr.w r3, r3, #1
8001868: f8c2 3098 str.w r3, [r2, #152] ; 0x98
/* Get Start Tick*/
tickstart = HAL_GetTick();
800186c: f7ff f942 bl 8000af4 <HAL_GetTick>
8001870: 6138 str r0, [r7, #16]
/* Wait till HSI48 is ready */
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
8001872: e008 b.n 8001886 <HAL_RCC_OscConfig+0x42a>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
8001874: f7ff f93e bl 8000af4 <HAL_GetTick>
8001878: 4602 mov r2, r0
800187a: 693b ldr r3, [r7, #16]
800187c: 1ad3 subs r3, r2, r3
800187e: 2b02 cmp r3, #2
8001880: d901 bls.n 8001886 <HAL_RCC_OscConfig+0x42a>
{
return HAL_TIMEOUT;
8001882: 2303 movs r3, #3
8001884: e0fc b.n 8001a80 <HAL_RCC_OscConfig+0x624>
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
8001886: 4b53 ldr r3, [pc, #332] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
8001888: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
800188c: f003 0302 and.w r3, r3, #2
8001890: 2b00 cmp r3, #0
8001892: d0ef beq.n 8001874 <HAL_RCC_OscConfig+0x418>
8001894: e01b b.n 80018ce <HAL_RCC_OscConfig+0x472>
}
}
else
{
/* Disable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_DISABLE();
8001896: 4b4f ldr r3, [pc, #316] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
8001898: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
800189c: 4a4d ldr r2, [pc, #308] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
800189e: f023 0301 bic.w r3, r3, #1
80018a2: f8c2 3098 str.w r3, [r2, #152] ; 0x98
/* Get Start Tick*/
tickstart = HAL_GetTick();
80018a6: f7ff f925 bl 8000af4 <HAL_GetTick>
80018aa: 6138 str r0, [r7, #16]
/* Wait till HSI48 is disabled */
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
80018ac: e008 b.n 80018c0 <HAL_RCC_OscConfig+0x464>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
80018ae: f7ff f921 bl 8000af4 <HAL_GetTick>
80018b2: 4602 mov r2, r0
80018b4: 693b ldr r3, [r7, #16]
80018b6: 1ad3 subs r3, r2, r3
80018b8: 2b02 cmp r3, #2
80018ba: d901 bls.n 80018c0 <HAL_RCC_OscConfig+0x464>
{
return HAL_TIMEOUT;
80018bc: 2303 movs r3, #3
80018be: e0df b.n 8001a80 <HAL_RCC_OscConfig+0x624>
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
80018c0: 4b44 ldr r3, [pc, #272] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80018c2: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
80018c6: f003 0302 and.w r3, r3, #2
80018ca: 2b00 cmp r3, #0
80018cc: d1ef bne.n 80018ae <HAL_RCC_OscConfig+0x452>
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
80018ce: 687b ldr r3, [r7, #4]
80018d0: 69db ldr r3, [r3, #28]
80018d2: 2b00 cmp r3, #0
80018d4: f000 80d3 beq.w 8001a7e <HAL_RCC_OscConfig+0x622>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
80018d8: 4b3e ldr r3, [pc, #248] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80018da: 689b ldr r3, [r3, #8]
80018dc: f003 030c and.w r3, r3, #12
80018e0: 2b0c cmp r3, #12
80018e2: f000 808d beq.w 8001a00 <HAL_RCC_OscConfig+0x5a4>
{
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
80018e6: 687b ldr r3, [r7, #4]
80018e8: 69db ldr r3, [r3, #28]
80018ea: 2b02 cmp r3, #2
80018ec: d15a bne.n 80019a4 <HAL_RCC_OscConfig+0x548>
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80018ee: 4b39 ldr r3, [pc, #228] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80018f0: 681b ldr r3, [r3, #0]
80018f2: 4a38 ldr r2, [pc, #224] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80018f4: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
80018f8: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80018fa: f7ff f8fb bl 8000af4 <HAL_GetTick>
80018fe: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8001900: e008 b.n 8001914 <HAL_RCC_OscConfig+0x4b8>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001902: f7ff f8f7 bl 8000af4 <HAL_GetTick>
8001906: 4602 mov r2, r0
8001908: 693b ldr r3, [r7, #16]
800190a: 1ad3 subs r3, r2, r3
800190c: 2b02 cmp r3, #2
800190e: d901 bls.n 8001914 <HAL_RCC_OscConfig+0x4b8>
{
return HAL_TIMEOUT;
8001910: 2303 movs r3, #3
8001912: e0b5 b.n 8001a80 <HAL_RCC_OscConfig+0x624>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8001914: 4b2f ldr r3, [pc, #188] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
8001916: 681b ldr r3, [r3, #0]
8001918: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800191c: 2b00 cmp r3, #0
800191e: d1f0 bne.n 8001902 <HAL_RCC_OscConfig+0x4a6>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001920: 4b2c ldr r3, [pc, #176] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
8001922: 68da ldr r2, [r3, #12]
8001924: 4b2d ldr r3, [pc, #180] ; (80019dc <HAL_RCC_OscConfig+0x580>)
8001926: 4013 ands r3, r2
8001928: 687a ldr r2, [r7, #4]
800192a: 6a11 ldr r1, [r2, #32]
800192c: 687a ldr r2, [r7, #4]
800192e: 6a52 ldr r2, [r2, #36] ; 0x24
8001930: 3a01 subs r2, #1
8001932: 0112 lsls r2, r2, #4
8001934: 4311 orrs r1, r2
8001936: 687a ldr r2, [r7, #4]
8001938: 6a92 ldr r2, [r2, #40] ; 0x28
800193a: 0212 lsls r2, r2, #8
800193c: 4311 orrs r1, r2
800193e: 687a ldr r2, [r7, #4]
8001940: 6b12 ldr r2, [r2, #48] ; 0x30
8001942: 0852 lsrs r2, r2, #1
8001944: 3a01 subs r2, #1
8001946: 0552 lsls r2, r2, #21
8001948: 4311 orrs r1, r2
800194a: 687a ldr r2, [r7, #4]
800194c: 6b52 ldr r2, [r2, #52] ; 0x34
800194e: 0852 lsrs r2, r2, #1
8001950: 3a01 subs r2, #1
8001952: 0652 lsls r2, r2, #25
8001954: 4311 orrs r1, r2
8001956: 687a ldr r2, [r7, #4]
8001958: 6ad2 ldr r2, [r2, #44] ; 0x2c
800195a: 06d2 lsls r2, r2, #27
800195c: 430a orrs r2, r1
800195e: 491d ldr r1, [pc, #116] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
8001960: 4313 orrs r3, r2
8001962: 60cb str r3, [r1, #12]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001964: 4b1b ldr r3, [pc, #108] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
8001966: 681b ldr r3, [r3, #0]
8001968: 4a1a ldr r2, [pc, #104] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
800196a: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
800196e: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
8001970: 4b18 ldr r3, [pc, #96] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
8001972: 68db ldr r3, [r3, #12]
8001974: 4a17 ldr r2, [pc, #92] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
8001976: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
800197a: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800197c: f7ff f8ba bl 8000af4 <HAL_GetTick>
8001980: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8001982: e008 b.n 8001996 <HAL_RCC_OscConfig+0x53a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001984: f7ff f8b6 bl 8000af4 <HAL_GetTick>
8001988: 4602 mov r2, r0
800198a: 693b ldr r3, [r7, #16]
800198c: 1ad3 subs r3, r2, r3
800198e: 2b02 cmp r3, #2
8001990: d901 bls.n 8001996 <HAL_RCC_OscConfig+0x53a>
{
return HAL_TIMEOUT;
8001992: 2303 movs r3, #3
8001994: e074 b.n 8001a80 <HAL_RCC_OscConfig+0x624>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8001996: 4b0f ldr r3, [pc, #60] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
8001998: 681b ldr r3, [r3, #0]
800199a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800199e: 2b00 cmp r3, #0
80019a0: d0f0 beq.n 8001984 <HAL_RCC_OscConfig+0x528>
80019a2: e06c b.n 8001a7e <HAL_RCC_OscConfig+0x622>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80019a4: 4b0b ldr r3, [pc, #44] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80019a6: 681b ldr r3, [r3, #0]
80019a8: 4a0a ldr r2, [pc, #40] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80019aa: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
80019ae: 6013 str r3, [r2, #0]
/* Disable all PLL outputs to save power if no PLLs on */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
80019b0: 4b08 ldr r3, [pc, #32] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80019b2: 68db ldr r3, [r3, #12]
80019b4: 4a07 ldr r2, [pc, #28] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80019b6: f023 0303 bic.w r3, r3, #3
80019ba: 60d3 str r3, [r2, #12]
__HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK);
80019bc: 4b05 ldr r3, [pc, #20] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80019be: 68db ldr r3, [r3, #12]
80019c0: 4a04 ldr r2, [pc, #16] ; (80019d4 <HAL_RCC_OscConfig+0x578>)
80019c2: f023 7388 bic.w r3, r3, #17825792 ; 0x1100000
80019c6: f423 3380 bic.w r3, r3, #65536 ; 0x10000
80019ca: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80019cc: f7ff f892 bl 8000af4 <HAL_GetTick>
80019d0: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
80019d2: e00e b.n 80019f2 <HAL_RCC_OscConfig+0x596>
80019d4: 40021000 .word 0x40021000
80019d8: 40007000 .word 0x40007000
80019dc: 019f800c .word 0x019f800c
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80019e0: f7ff f888 bl 8000af4 <HAL_GetTick>
80019e4: 4602 mov r2, r0
80019e6: 693b ldr r3, [r7, #16]
80019e8: 1ad3 subs r3, r2, r3
80019ea: 2b02 cmp r3, #2
80019ec: d901 bls.n 80019f2 <HAL_RCC_OscConfig+0x596>
{
return HAL_TIMEOUT;
80019ee: 2303 movs r3, #3
80019f0: e046 b.n 8001a80 <HAL_RCC_OscConfig+0x624>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
80019f2: 4b25 ldr r3, [pc, #148] ; (8001a88 <HAL_RCC_OscConfig+0x62c>)
80019f4: 681b ldr r3, [r3, #0]
80019f6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80019fa: 2b00 cmp r3, #0
80019fc: d1f0 bne.n 80019e0 <HAL_RCC_OscConfig+0x584>
80019fe: e03e b.n 8001a7e <HAL_RCC_OscConfig+0x622>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001a00: 687b ldr r3, [r7, #4]
8001a02: 69db ldr r3, [r3, #28]
8001a04: 2b01 cmp r3, #1
8001a06: d101 bne.n 8001a0c <HAL_RCC_OscConfig+0x5b0>
{
return HAL_ERROR;
8001a08: 2301 movs r3, #1
8001a0a: e039 b.n 8001a80 <HAL_RCC_OscConfig+0x624>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
temp_pllckcfg = RCC->PLLCFGR;
8001a0c: 4b1e ldr r3, [pc, #120] ; (8001a88 <HAL_RCC_OscConfig+0x62c>)
8001a0e: 68db ldr r3, [r3, #12]
8001a10: 617b str r3, [r7, #20]
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001a12: 697b ldr r3, [r7, #20]
8001a14: f003 0203 and.w r2, r3, #3
8001a18: 687b ldr r3, [r7, #4]
8001a1a: 6a1b ldr r3, [r3, #32]
8001a1c: 429a cmp r2, r3
8001a1e: d12c bne.n 8001a7a <HAL_RCC_OscConfig+0x61e>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
8001a20: 697b ldr r3, [r7, #20]
8001a22: f003 02f0 and.w r2, r3, #240 ; 0xf0
8001a26: 687b ldr r3, [r7, #4]
8001a28: 6a5b ldr r3, [r3, #36] ; 0x24
8001a2a: 3b01 subs r3, #1
8001a2c: 011b lsls r3, r3, #4
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001a2e: 429a cmp r2, r3
8001a30: d123 bne.n 8001a7a <HAL_RCC_OscConfig+0x61e>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
8001a32: 697b ldr r3, [r7, #20]
8001a34: f403 42fe and.w r2, r3, #32512 ; 0x7f00
8001a38: 687b ldr r3, [r7, #4]
8001a3a: 6a9b ldr r3, [r3, #40] ; 0x28
8001a3c: 021b lsls r3, r3, #8
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
8001a3e: 429a cmp r2, r3
8001a40: d11b bne.n 8001a7a <HAL_RCC_OscConfig+0x61e>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
8001a42: 697b ldr r3, [r7, #20]
8001a44: f003 4278 and.w r2, r3, #4160749568 ; 0xf8000000
8001a48: 687b ldr r3, [r7, #4]
8001a4a: 6adb ldr r3, [r3, #44] ; 0x2c
8001a4c: 06db lsls r3, r3, #27
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
8001a4e: 429a cmp r2, r3
8001a50: d113 bne.n 8001a7a <HAL_RCC_OscConfig+0x61e>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8001a52: 697b ldr r3, [r7, #20]
8001a54: f403 02c0 and.w r2, r3, #6291456 ; 0x600000
8001a58: 687b ldr r3, [r7, #4]
8001a5a: 6b1b ldr r3, [r3, #48] ; 0x30
8001a5c: 085b lsrs r3, r3, #1
8001a5e: 3b01 subs r3, #1
8001a60: 055b lsls r3, r3, #21
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
8001a62: 429a cmp r2, r3
8001a64: d109 bne.n 8001a7a <HAL_RCC_OscConfig+0x61e>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
8001a66: 697b ldr r3, [r7, #20]
8001a68: f003 62c0 and.w r2, r3, #100663296 ; 0x6000000
8001a6c: 687b ldr r3, [r7, #4]
8001a6e: 6b5b ldr r3, [r3, #52] ; 0x34
8001a70: 085b lsrs r3, r3, #1
8001a72: 3b01 subs r3, #1
8001a74: 065b lsls r3, r3, #25
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8001a76: 429a cmp r2, r3
8001a78: d001 beq.n 8001a7e <HAL_RCC_OscConfig+0x622>
{
return HAL_ERROR;
8001a7a: 2301 movs r3, #1
8001a7c: e000 b.n 8001a80 <HAL_RCC_OscConfig+0x624>
}
}
}
}
return HAL_OK;
8001a7e: 2300 movs r3, #0
}
8001a80: 4618 mov r0, r3
8001a82: 3720 adds r7, #32
8001a84: 46bd mov sp, r7
8001a86: bd80 pop {r7, pc}
8001a88: 40021000 .word 0x40021000
08001a8c <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001a8c: b580 push {r7, lr}
8001a8e: b086 sub sp, #24
8001a90: af00 add r7, sp, #0
8001a92: 6078 str r0, [r7, #4]
8001a94: 6039 str r1, [r7, #0]
uint32_t tickstart;
uint32_t pllfreq;
uint32_t hpre = RCC_SYSCLK_DIV1;
8001a96: 2300 movs r3, #0
8001a98: 617b str r3, [r7, #20]
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8001a9a: 687b ldr r3, [r7, #4]
8001a9c: 2b00 cmp r3, #0
8001a9e: d101 bne.n 8001aa4 <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8001aa0: 2301 movs r3, #1
8001aa2: e11e b.n 8001ce2 <HAL_RCC_ClockConfig+0x256>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8001aa4: 4b91 ldr r3, [pc, #580] ; (8001cec <HAL_RCC_ClockConfig+0x260>)
8001aa6: 681b ldr r3, [r3, #0]
8001aa8: f003 030f and.w r3, r3, #15
8001aac: 683a ldr r2, [r7, #0]
8001aae: 429a cmp r2, r3
8001ab0: d910 bls.n 8001ad4 <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001ab2: 4b8e ldr r3, [pc, #568] ; (8001cec <HAL_RCC_ClockConfig+0x260>)
8001ab4: 681b ldr r3, [r3, #0]
8001ab6: f023 020f bic.w r2, r3, #15
8001aba: 498c ldr r1, [pc, #560] ; (8001cec <HAL_RCC_ClockConfig+0x260>)
8001abc: 683b ldr r3, [r7, #0]
8001abe: 4313 orrs r3, r2
8001ac0: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8001ac2: 4b8a ldr r3, [pc, #552] ; (8001cec <HAL_RCC_ClockConfig+0x260>)
8001ac4: 681b ldr r3, [r3, #0]
8001ac6: f003 030f and.w r3, r3, #15
8001aca: 683a ldr r2, [r7, #0]
8001acc: 429a cmp r2, r3
8001ace: d001 beq.n 8001ad4 <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
8001ad0: 2301 movs r3, #1
8001ad2: e106 b.n 8001ce2 <HAL_RCC_ClockConfig+0x256>
}
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001ad4: 687b ldr r3, [r7, #4]
8001ad6: 681b ldr r3, [r3, #0]
8001ad8: f003 0301 and.w r3, r3, #1
8001adc: 2b00 cmp r3, #0
8001ade: d073 beq.n 8001bc8 <HAL_RCC_ClockConfig+0x13c>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* PLL is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8001ae0: 687b ldr r3, [r7, #4]
8001ae2: 685b ldr r3, [r3, #4]
8001ae4: 2b03 cmp r3, #3
8001ae6: d129 bne.n 8001b3c <HAL_RCC_ClockConfig+0xb0>
{
/* Check the PLL ready flag */
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8001ae8: 4b81 ldr r3, [pc, #516] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001aea: 681b ldr r3, [r3, #0]
8001aec: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001af0: 2b00 cmp r3, #0
8001af2: d101 bne.n 8001af8 <HAL_RCC_ClockConfig+0x6c>
{
return HAL_ERROR;
8001af4: 2301 movs r3, #1
8001af6: e0f4 b.n 8001ce2 <HAL_RCC_ClockConfig+0x256>
}
/* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */
/* Compute target PLL output frequency */
pllfreq = RCC_GetSysClockFreqFromPLLSource();
8001af8: f000 f99e bl 8001e38 <RCC_GetSysClockFreqFromPLLSource>
8001afc: 6138 str r0, [r7, #16]
/* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */
if(pllfreq > 80000000U)
8001afe: 693b ldr r3, [r7, #16]
8001b00: 4a7c ldr r2, [pc, #496] ; (8001cf4 <HAL_RCC_ClockConfig+0x268>)
8001b02: 4293 cmp r3, r2
8001b04: d93f bls.n 8001b86 <HAL_RCC_ClockConfig+0xfa>
{
if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
8001b06: 4b7a ldr r3, [pc, #488] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001b08: 689b ldr r3, [r3, #8]
8001b0a: f003 03f0 and.w r3, r3, #240 ; 0xf0
8001b0e: 2b00 cmp r3, #0
8001b10: d009 beq.n 8001b26 <HAL_RCC_ClockConfig+0x9a>
(((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
8001b12: 687b ldr r3, [r7, #4]
8001b14: 681b ldr r3, [r3, #0]
8001b16: f003 0302 and.w r3, r3, #2
if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
8001b1a: 2b00 cmp r3, #0
8001b1c: d033 beq.n 8001b86 <HAL_RCC_ClockConfig+0xfa>
(RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))))
8001b1e: 687b ldr r3, [r7, #4]
8001b20: 689b ldr r3, [r3, #8]
(((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
8001b22: 2b00 cmp r3, #0
8001b24: d12f bne.n 8001b86 <HAL_RCC_ClockConfig+0xfa>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
8001b26: 4b72 ldr r3, [pc, #456] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001b28: 689b ldr r3, [r3, #8]
8001b2a: f023 03f0 bic.w r3, r3, #240 ; 0xf0
8001b2e: 4a70 ldr r2, [pc, #448] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001b30: f043 0380 orr.w r3, r3, #128 ; 0x80
8001b34: 6093 str r3, [r2, #8]
hpre = RCC_SYSCLK_DIV2;
8001b36: 2380 movs r3, #128 ; 0x80
8001b38: 617b str r3, [r7, #20]
8001b3a: e024 b.n 8001b86 <HAL_RCC_ClockConfig+0xfa>
}
}
else
{
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001b3c: 687b ldr r3, [r7, #4]
8001b3e: 685b ldr r3, [r3, #4]
8001b40: 2b02 cmp r3, #2
8001b42: d107 bne.n 8001b54 <HAL_RCC_ClockConfig+0xc8>
{
/* Check the HSE ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8001b44: 4b6a ldr r3, [pc, #424] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001b46: 681b ldr r3, [r3, #0]
8001b48: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001b4c: 2b00 cmp r3, #0
8001b4e: d109 bne.n 8001b64 <HAL_RCC_ClockConfig+0xd8>
{
return HAL_ERROR;
8001b50: 2301 movs r3, #1
8001b52: e0c6 b.n 8001ce2 <HAL_RCC_ClockConfig+0x256>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8001b54: 4b66 ldr r3, [pc, #408] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001b56: 681b ldr r3, [r3, #0]
8001b58: f403 6380 and.w r3, r3, #1024 ; 0x400
8001b5c: 2b00 cmp r3, #0
8001b5e: d101 bne.n 8001b64 <HAL_RCC_ClockConfig+0xd8>
{
return HAL_ERROR;
8001b60: 2301 movs r3, #1
8001b62: e0be b.n 8001ce2 <HAL_RCC_ClockConfig+0x256>
}
}
/* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */
pllfreq = HAL_RCC_GetSysClockFreq();
8001b64: f000 f8ce bl 8001d04 <HAL_RCC_GetSysClockFreq>
8001b68: 6138 str r0, [r7, #16]
/* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */
if(pllfreq > 80000000U)
8001b6a: 693b ldr r3, [r7, #16]
8001b6c: 4a61 ldr r2, [pc, #388] ; (8001cf4 <HAL_RCC_ClockConfig+0x268>)
8001b6e: 4293 cmp r3, r2
8001b70: d909 bls.n 8001b86 <HAL_RCC_ClockConfig+0xfa>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
8001b72: 4b5f ldr r3, [pc, #380] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001b74: 689b ldr r3, [r3, #8]
8001b76: f023 03f0 bic.w r3, r3, #240 ; 0xf0
8001b7a: 4a5d ldr r2, [pc, #372] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001b7c: f043 0380 orr.w r3, r3, #128 ; 0x80
8001b80: 6093 str r3, [r2, #8]
hpre = RCC_SYSCLK_DIV2;
8001b82: 2380 movs r3, #128 ; 0x80
8001b84: 617b str r3, [r7, #20]
}
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
8001b86: 4b5a ldr r3, [pc, #360] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001b88: 689b ldr r3, [r3, #8]
8001b8a: f023 0203 bic.w r2, r3, #3
8001b8e: 687b ldr r3, [r7, #4]
8001b90: 685b ldr r3, [r3, #4]
8001b92: 4957 ldr r1, [pc, #348] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001b94: 4313 orrs r3, r2
8001b96: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001b98: f7fe ffac bl 8000af4 <HAL_GetTick>
8001b9c: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001b9e: e00a b.n 8001bb6 <HAL_RCC_ClockConfig+0x12a>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8001ba0: f7fe ffa8 bl 8000af4 <HAL_GetTick>
8001ba4: 4602 mov r2, r0
8001ba6: 68fb ldr r3, [r7, #12]
8001ba8: 1ad3 subs r3, r2, r3
8001baa: f241 3288 movw r2, #5000 ; 0x1388
8001bae: 4293 cmp r3, r2
8001bb0: d901 bls.n 8001bb6 <HAL_RCC_ClockConfig+0x12a>
{
return HAL_TIMEOUT;
8001bb2: 2303 movs r3, #3
8001bb4: e095 b.n 8001ce2 <HAL_RCC_ClockConfig+0x256>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001bb6: 4b4e ldr r3, [pc, #312] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001bb8: 689b ldr r3, [r3, #8]
8001bba: f003 020c and.w r2, r3, #12
8001bbe: 687b ldr r3, [r7, #4]
8001bc0: 685b ldr r3, [r3, #4]
8001bc2: 009b lsls r3, r3, #2
8001bc4: 429a cmp r2, r3
8001bc6: d1eb bne.n 8001ba0 <HAL_RCC_ClockConfig+0x114>
}
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8001bc8: 687b ldr r3, [r7, #4]
8001bca: 681b ldr r3, [r3, #0]
8001bcc: f003 0302 and.w r3, r3, #2
8001bd0: 2b00 cmp r3, #0
8001bd2: d023 beq.n 8001c1c <HAL_RCC_ClockConfig+0x190>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001bd4: 687b ldr r3, [r7, #4]
8001bd6: 681b ldr r3, [r3, #0]
8001bd8: f003 0304 and.w r3, r3, #4
8001bdc: 2b00 cmp r3, #0
8001bde: d005 beq.n 8001bec <HAL_RCC_ClockConfig+0x160>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8001be0: 4b43 ldr r3, [pc, #268] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001be2: 689b ldr r3, [r3, #8]
8001be4: 4a42 ldr r2, [pc, #264] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001be6: f443 63e0 orr.w r3, r3, #1792 ; 0x700
8001bea: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001bec: 687b ldr r3, [r7, #4]
8001bee: 681b ldr r3, [r3, #0]
8001bf0: f003 0308 and.w r3, r3, #8
8001bf4: 2b00 cmp r3, #0
8001bf6: d007 beq.n 8001c08 <HAL_RCC_ClockConfig+0x17c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16);
8001bf8: 4b3d ldr r3, [pc, #244] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001bfa: 689b ldr r3, [r3, #8]
8001bfc: f423 537c bic.w r3, r3, #16128 ; 0x3f00
8001c00: 4a3b ldr r2, [pc, #236] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001c02: f443 63e0 orr.w r3, r3, #1792 ; 0x700
8001c06: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001c08: 4b39 ldr r3, [pc, #228] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001c0a: 689b ldr r3, [r3, #8]
8001c0c: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8001c10: 687b ldr r3, [r7, #4]
8001c12: 689b ldr r3, [r3, #8]
8001c14: 4936 ldr r1, [pc, #216] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001c16: 4313 orrs r3, r2
8001c18: 608b str r3, [r1, #8]
8001c1a: e008 b.n 8001c2e <HAL_RCC_ClockConfig+0x1a2>
}
else
{
/* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */
if(hpre == RCC_SYSCLK_DIV2)
8001c1c: 697b ldr r3, [r7, #20]
8001c1e: 2b80 cmp r3, #128 ; 0x80
8001c20: d105 bne.n 8001c2e <HAL_RCC_ClockConfig+0x1a2>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
8001c22: 4b33 ldr r3, [pc, #204] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001c24: 689b ldr r3, [r3, #8]
8001c26: 4a32 ldr r2, [pc, #200] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001c28: f023 03f0 bic.w r3, r3, #240 ; 0xf0
8001c2c: 6093 str r3, [r2, #8]
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8001c2e: 4b2f ldr r3, [pc, #188] ; (8001cec <HAL_RCC_ClockConfig+0x260>)
8001c30: 681b ldr r3, [r3, #0]
8001c32: f003 030f and.w r3, r3, #15
8001c36: 683a ldr r2, [r7, #0]
8001c38: 429a cmp r2, r3
8001c3a: d21d bcs.n 8001c78 <HAL_RCC_ClockConfig+0x1ec>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001c3c: 4b2b ldr r3, [pc, #172] ; (8001cec <HAL_RCC_ClockConfig+0x260>)
8001c3e: 681b ldr r3, [r3, #0]
8001c40: f023 020f bic.w r2, r3, #15
8001c44: 4929 ldr r1, [pc, #164] ; (8001cec <HAL_RCC_ClockConfig+0x260>)
8001c46: 683b ldr r3, [r7, #0]
8001c48: 4313 orrs r3, r2
8001c4a: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
8001c4c: f7fe ff52 bl 8000af4 <HAL_GetTick>
8001c50: 60f8 str r0, [r7, #12]
while (__HAL_FLASH_GET_LATENCY() != FLatency)
8001c52: e00a b.n 8001c6a <HAL_RCC_ClockConfig+0x1de>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8001c54: f7fe ff4e bl 8000af4 <HAL_GetTick>
8001c58: 4602 mov r2, r0
8001c5a: 68fb ldr r3, [r7, #12]
8001c5c: 1ad3 subs r3, r2, r3
8001c5e: f241 3288 movw r2, #5000 ; 0x1388
8001c62: 4293 cmp r3, r2
8001c64: d901 bls.n 8001c6a <HAL_RCC_ClockConfig+0x1de>
{
return HAL_TIMEOUT;
8001c66: 2303 movs r3, #3
8001c68: e03b b.n 8001ce2 <HAL_RCC_ClockConfig+0x256>
while (__HAL_FLASH_GET_LATENCY() != FLatency)
8001c6a: 4b20 ldr r3, [pc, #128] ; (8001cec <HAL_RCC_ClockConfig+0x260>)
8001c6c: 681b ldr r3, [r3, #0]
8001c6e: f003 030f and.w r3, r3, #15
8001c72: 683a ldr r2, [r7, #0]
8001c74: 429a cmp r2, r3
8001c76: d1ed bne.n 8001c54 <HAL_RCC_ClockConfig+0x1c8>
}
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001c78: 687b ldr r3, [r7, #4]
8001c7a: 681b ldr r3, [r3, #0]
8001c7c: f003 0304 and.w r3, r3, #4
8001c80: 2b00 cmp r3, #0
8001c82: d008 beq.n 8001c96 <HAL_RCC_ClockConfig+0x20a>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8001c84: 4b1a ldr r3, [pc, #104] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001c86: 689b ldr r3, [r3, #8]
8001c88: f423 62e0 bic.w r2, r3, #1792 ; 0x700
8001c8c: 687b ldr r3, [r7, #4]
8001c8e: 68db ldr r3, [r3, #12]
8001c90: 4917 ldr r1, [pc, #92] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001c92: 4313 orrs r3, r2
8001c94: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001c96: 687b ldr r3, [r7, #4]
8001c98: 681b ldr r3, [r3, #0]
8001c9a: f003 0308 and.w r3, r3, #8
8001c9e: 2b00 cmp r3, #0
8001ca0: d009 beq.n 8001cb6 <HAL_RCC_ClockConfig+0x22a>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8001ca2: 4b13 ldr r3, [pc, #76] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001ca4: 689b ldr r3, [r3, #8]
8001ca6: f423 5260 bic.w r2, r3, #14336 ; 0x3800
8001caa: 687b ldr r3, [r7, #4]
8001cac: 691b ldr r3, [r3, #16]
8001cae: 00db lsls r3, r3, #3
8001cb0: 490f ldr r1, [pc, #60] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001cb2: 4313 orrs r3, r2
8001cb4: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
8001cb6: f000 f825 bl 8001d04 <HAL_RCC_GetSysClockFreq>
8001cba: 4602 mov r2, r0
8001cbc: 4b0c ldr r3, [pc, #48] ; (8001cf0 <HAL_RCC_ClockConfig+0x264>)
8001cbe: 689b ldr r3, [r3, #8]
8001cc0: 091b lsrs r3, r3, #4
8001cc2: f003 030f and.w r3, r3, #15
8001cc6: 490c ldr r1, [pc, #48] ; (8001cf8 <HAL_RCC_ClockConfig+0x26c>)
8001cc8: 5ccb ldrb r3, [r1, r3]
8001cca: f003 031f and.w r3, r3, #31
8001cce: fa22 f303 lsr.w r3, r2, r3
8001cd2: 4a0a ldr r2, [pc, #40] ; (8001cfc <HAL_RCC_ClockConfig+0x270>)
8001cd4: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick(uwTickPrio);
8001cd6: 4b0a ldr r3, [pc, #40] ; (8001d00 <HAL_RCC_ClockConfig+0x274>)
8001cd8: 681b ldr r3, [r3, #0]
8001cda: 4618 mov r0, r3
8001cdc: f7fe febe bl 8000a5c <HAL_InitTick>
8001ce0: 4603 mov r3, r0
}
8001ce2: 4618 mov r0, r3
8001ce4: 3718 adds r7, #24
8001ce6: 46bd mov sp, r7
8001ce8: bd80 pop {r7, pc}
8001cea: bf00 nop
8001cec: 40022000 .word 0x40022000
8001cf0: 40021000 .word 0x40021000
8001cf4: 04c4b400 .word 0x04c4b400
8001cf8: 08002ee0 .word 0x08002ee0
8001cfc: 20000000 .word 0x20000000
8001d00: 20000004 .word 0x20000004
08001d04 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001d04: b480 push {r7}
8001d06: b087 sub sp, #28
8001d08: af00 add r7, sp, #0
uint32_t pllvco, pllsource, pllr, pllm;
uint32_t sysclockfreq;
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
8001d0a: 4b2c ldr r3, [pc, #176] ; (8001dbc <HAL_RCC_GetSysClockFreq+0xb8>)
8001d0c: 689b ldr r3, [r3, #8]
8001d0e: f003 030c and.w r3, r3, #12
8001d12: 2b04 cmp r3, #4
8001d14: d102 bne.n 8001d1c <HAL_RCC_GetSysClockFreq+0x18>
{
/* HSI used as system clock source */
sysclockfreq = HSI_VALUE;
8001d16: 4b2a ldr r3, [pc, #168] ; (8001dc0 <HAL_RCC_GetSysClockFreq+0xbc>)
8001d18: 613b str r3, [r7, #16]
8001d1a: e047 b.n 8001dac <HAL_RCC_GetSysClockFreq+0xa8>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
8001d1c: 4b27 ldr r3, [pc, #156] ; (8001dbc <HAL_RCC_GetSysClockFreq+0xb8>)
8001d1e: 689b ldr r3, [r3, #8]
8001d20: f003 030c and.w r3, r3, #12
8001d24: 2b08 cmp r3, #8
8001d26: d102 bne.n 8001d2e <HAL_RCC_GetSysClockFreq+0x2a>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
8001d28: 4b26 ldr r3, [pc, #152] ; (8001dc4 <HAL_RCC_GetSysClockFreq+0xc0>)
8001d2a: 613b str r3, [r7, #16]
8001d2c: e03e b.n 8001dac <HAL_RCC_GetSysClockFreq+0xa8>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
8001d2e: 4b23 ldr r3, [pc, #140] ; (8001dbc <HAL_RCC_GetSysClockFreq+0xb8>)
8001d30: 689b ldr r3, [r3, #8]
8001d32: f003 030c and.w r3, r3, #12
8001d36: 2b0c cmp r3, #12
8001d38: d136 bne.n 8001da8 <HAL_RCC_GetSysClockFreq+0xa4>
/* PLL used as system clock source */
/* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
8001d3a: 4b20 ldr r3, [pc, #128] ; (8001dbc <HAL_RCC_GetSysClockFreq+0xb8>)
8001d3c: 68db ldr r3, [r3, #12]
8001d3e: f003 0303 and.w r3, r3, #3
8001d42: 60fb str r3, [r7, #12]
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
8001d44: 4b1d ldr r3, [pc, #116] ; (8001dbc <HAL_RCC_GetSysClockFreq+0xb8>)
8001d46: 68db ldr r3, [r3, #12]
8001d48: 091b lsrs r3, r3, #4
8001d4a: f003 030f and.w r3, r3, #15
8001d4e: 3301 adds r3, #1
8001d50: 60bb str r3, [r7, #8]
switch (pllsource)
8001d52: 68fb ldr r3, [r7, #12]
8001d54: 2b03 cmp r3, #3
8001d56: d10c bne.n 8001d72 <HAL_RCC_GetSysClockFreq+0x6e>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8001d58: 4a1a ldr r2, [pc, #104] ; (8001dc4 <HAL_RCC_GetSysClockFreq+0xc0>)
8001d5a: 68bb ldr r3, [r7, #8]
8001d5c: fbb2 f3f3 udiv r3, r2, r3
8001d60: 4a16 ldr r2, [pc, #88] ; (8001dbc <HAL_RCC_GetSysClockFreq+0xb8>)
8001d62: 68d2 ldr r2, [r2, #12]
8001d64: 0a12 lsrs r2, r2, #8
8001d66: f002 027f and.w r2, r2, #127 ; 0x7f
8001d6a: fb02 f303 mul.w r3, r2, r3
8001d6e: 617b str r3, [r7, #20]
break;
8001d70: e00c b.n 8001d8c <HAL_RCC_GetSysClockFreq+0x88>
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
default:
pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8001d72: 4a13 ldr r2, [pc, #76] ; (8001dc0 <HAL_RCC_GetSysClockFreq+0xbc>)
8001d74: 68bb ldr r3, [r7, #8]
8001d76: fbb2 f3f3 udiv r3, r2, r3
8001d7a: 4a10 ldr r2, [pc, #64] ; (8001dbc <HAL_RCC_GetSysClockFreq+0xb8>)
8001d7c: 68d2 ldr r2, [r2, #12]
8001d7e: 0a12 lsrs r2, r2, #8
8001d80: f002 027f and.w r2, r2, #127 ; 0x7f
8001d84: fb02 f303 mul.w r3, r2, r3
8001d88: 617b str r3, [r7, #20]
break;
8001d8a: bf00 nop
}
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
8001d8c: 4b0b ldr r3, [pc, #44] ; (8001dbc <HAL_RCC_GetSysClockFreq+0xb8>)
8001d8e: 68db ldr r3, [r3, #12]
8001d90: 0e5b lsrs r3, r3, #25
8001d92: f003 0303 and.w r3, r3, #3
8001d96: 3301 adds r3, #1
8001d98: 005b lsls r3, r3, #1
8001d9a: 607b str r3, [r7, #4]
sysclockfreq = pllvco/pllr;
8001d9c: 697a ldr r2, [r7, #20]
8001d9e: 687b ldr r3, [r7, #4]
8001da0: fbb2 f3f3 udiv r3, r2, r3
8001da4: 613b str r3, [r7, #16]
8001da6: e001 b.n 8001dac <HAL_RCC_GetSysClockFreq+0xa8>
}
else
{
sysclockfreq = 0U;
8001da8: 2300 movs r3, #0
8001daa: 613b str r3, [r7, #16]
}
return sysclockfreq;
8001dac: 693b ldr r3, [r7, #16]
}
8001dae: 4618 mov r0, r3
8001db0: 371c adds r7, #28
8001db2: 46bd mov sp, r7
8001db4: f85d 7b04 ldr.w r7, [sp], #4
8001db8: 4770 bx lr
8001dba: bf00 nop
8001dbc: 40021000 .word 0x40021000
8001dc0: 00f42400 .word 0x00f42400
8001dc4: 016e3600 .word 0x016e3600
08001dc8 <HAL_RCC_GetHCLKFreq>:
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8001dc8: b480 push {r7}
8001dca: af00 add r7, sp, #0
return SystemCoreClock;
8001dcc: 4b03 ldr r3, [pc, #12] ; (8001ddc <HAL_RCC_GetHCLKFreq+0x14>)
8001dce: 681b ldr r3, [r3, #0]
}
8001dd0: 4618 mov r0, r3
8001dd2: 46bd mov sp, r7
8001dd4: f85d 7b04 ldr.w r7, [sp], #4
8001dd8: 4770 bx lr
8001dda: bf00 nop
8001ddc: 20000000 .word 0x20000000
08001de0 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8001de0: b580 push {r7, lr}
8001de2: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
8001de4: f7ff fff0 bl 8001dc8 <HAL_RCC_GetHCLKFreq>
8001de8: 4602 mov r2, r0
8001dea: 4b06 ldr r3, [pc, #24] ; (8001e04 <HAL_RCC_GetPCLK1Freq+0x24>)
8001dec: 689b ldr r3, [r3, #8]
8001dee: 0a1b lsrs r3, r3, #8
8001df0: f003 0307 and.w r3, r3, #7
8001df4: 4904 ldr r1, [pc, #16] ; (8001e08 <HAL_RCC_GetPCLK1Freq+0x28>)
8001df6: 5ccb ldrb r3, [r1, r3]
8001df8: f003 031f and.w r3, r3, #31
8001dfc: fa22 f303 lsr.w r3, r2, r3
}
8001e00: 4618 mov r0, r3
8001e02: bd80 pop {r7, pc}
8001e04: 40021000 .word 0x40021000
8001e08: 08002ef0 .word 0x08002ef0
08001e0c <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8001e0c: b580 push {r7, lr}
8001e0e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
8001e10: f7ff ffda bl 8001dc8 <HAL_RCC_GetHCLKFreq>
8001e14: 4602 mov r2, r0
8001e16: 4b06 ldr r3, [pc, #24] ; (8001e30 <HAL_RCC_GetPCLK2Freq+0x24>)
8001e18: 689b ldr r3, [r3, #8]
8001e1a: 0adb lsrs r3, r3, #11
8001e1c: f003 0307 and.w r3, r3, #7
8001e20: 4904 ldr r1, [pc, #16] ; (8001e34 <HAL_RCC_GetPCLK2Freq+0x28>)
8001e22: 5ccb ldrb r3, [r1, r3]
8001e24: f003 031f and.w r3, r3, #31
8001e28: fa22 f303 lsr.w r3, r2, r3
}
8001e2c: 4618 mov r0, r3
8001e2e: bd80 pop {r7, pc}
8001e30: 40021000 .word 0x40021000
8001e34: 08002ef0 .word 0x08002ef0
08001e38 <RCC_GetSysClockFreqFromPLLSource>:
/**
* @brief Compute SYSCLK frequency based on PLL SYSCLK source.
* @retval SYSCLK frequency
*/
static uint32_t RCC_GetSysClockFreqFromPLLSource(void)
{
8001e38: b480 push {r7}
8001e3a: b087 sub sp, #28
8001e3c: af00 add r7, sp, #0
uint32_t sysclockfreq;
/* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
8001e3e: 4b1e ldr r3, [pc, #120] ; (8001eb8 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8001e40: 68db ldr r3, [r3, #12]
8001e42: f003 0303 and.w r3, r3, #3
8001e46: 613b str r3, [r7, #16]
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
8001e48: 4b1b ldr r3, [pc, #108] ; (8001eb8 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8001e4a: 68db ldr r3, [r3, #12]
8001e4c: 091b lsrs r3, r3, #4
8001e4e: f003 030f and.w r3, r3, #15
8001e52: 3301 adds r3, #1
8001e54: 60fb str r3, [r7, #12]
switch (pllsource)
8001e56: 693b ldr r3, [r7, #16]
8001e58: 2b03 cmp r3, #3
8001e5a: d10c bne.n 8001e76 <RCC_GetSysClockFreqFromPLLSource+0x3e>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8001e5c: 4a17 ldr r2, [pc, #92] ; (8001ebc <RCC_GetSysClockFreqFromPLLSource+0x84>)
8001e5e: 68fb ldr r3, [r7, #12]
8001e60: fbb2 f3f3 udiv r3, r2, r3
8001e64: 4a14 ldr r2, [pc, #80] ; (8001eb8 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8001e66: 68d2 ldr r2, [r2, #12]
8001e68: 0a12 lsrs r2, r2, #8
8001e6a: f002 027f and.w r2, r2, #127 ; 0x7f
8001e6e: fb02 f303 mul.w r3, r2, r3
8001e72: 617b str r3, [r7, #20]
break;
8001e74: e00c b.n 8001e90 <RCC_GetSysClockFreqFromPLLSource+0x58>
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
default:
pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8001e76: 4a12 ldr r2, [pc, #72] ; (8001ec0 <RCC_GetSysClockFreqFromPLLSource+0x88>)
8001e78: 68fb ldr r3, [r7, #12]
8001e7a: fbb2 f3f3 udiv r3, r2, r3
8001e7e: 4a0e ldr r2, [pc, #56] ; (8001eb8 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8001e80: 68d2 ldr r2, [r2, #12]
8001e82: 0a12 lsrs r2, r2, #8
8001e84: f002 027f and.w r2, r2, #127 ; 0x7f
8001e88: fb02 f303 mul.w r3, r2, r3
8001e8c: 617b str r3, [r7, #20]
break;
8001e8e: bf00 nop
}
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
8001e90: 4b09 ldr r3, [pc, #36] ; (8001eb8 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8001e92: 68db ldr r3, [r3, #12]
8001e94: 0e5b lsrs r3, r3, #25
8001e96: f003 0303 and.w r3, r3, #3
8001e9a: 3301 adds r3, #1
8001e9c: 005b lsls r3, r3, #1
8001e9e: 60bb str r3, [r7, #8]
sysclockfreq = pllvco/pllr;
8001ea0: 697a ldr r2, [r7, #20]
8001ea2: 68bb ldr r3, [r7, #8]
8001ea4: fbb2 f3f3 udiv r3, r2, r3
8001ea8: 607b str r3, [r7, #4]
return sysclockfreq;
8001eaa: 687b ldr r3, [r7, #4]
}
8001eac: 4618 mov r0, r3
8001eae: 371c adds r7, #28
8001eb0: 46bd mov sp, r7
8001eb2: f85d 7b04 ldr.w r7, [sp], #4
8001eb6: 4770 bx lr
8001eb8: 40021000 .word 0x40021000
8001ebc: 016e3600 .word 0x016e3600
8001ec0: 00f42400 .word 0x00f42400
08001ec4 <HAL_RCCEx_PeriphCLKConfig>:
* the RTC clock source: in this case the access to Backup domain is enabled.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8001ec4: b580 push {r7, lr}
8001ec6: b086 sub sp, #24
8001ec8: af00 add r7, sp, #0
8001eca: 6078 str r0, [r7, #4]
uint32_t tmpregister;
uint32_t tickstart;
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
8001ecc: 2300 movs r3, #0
8001ece: 74fb strb r3, [r7, #19]
HAL_StatusTypeDef status = HAL_OK; /* Final status */
8001ed0: 2300 movs r3, #0
8001ed2: 74bb strb r3, [r7, #18]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*-------------------------- RTC clock source configuration ----------------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
8001ed4: 687b ldr r3, [r7, #4]
8001ed6: 681b ldr r3, [r3, #0]
8001ed8: f403 2300 and.w r3, r3, #524288 ; 0x80000
8001edc: 2b00 cmp r3, #0
8001ede: f000 8098 beq.w 8002012 <HAL_RCCEx_PeriphCLKConfig+0x14e>
{
FlagStatus pwrclkchanged = RESET;
8001ee2: 2300 movs r3, #0
8001ee4: 747b strb r3, [r7, #17]
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8001ee6: 4b43 ldr r3, [pc, #268] ; (8001ff4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8001ee8: 6d9b ldr r3, [r3, #88] ; 0x58
8001eea: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001eee: 2b00 cmp r3, #0
8001ef0: d10d bne.n 8001f0e <HAL_RCCEx_PeriphCLKConfig+0x4a>
{
__HAL_RCC_PWR_CLK_ENABLE();
8001ef2: 4b40 ldr r3, [pc, #256] ; (8001ff4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8001ef4: 6d9b ldr r3, [r3, #88] ; 0x58
8001ef6: 4a3f ldr r2, [pc, #252] ; (8001ff4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8001ef8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8001efc: 6593 str r3, [r2, #88] ; 0x58
8001efe: 4b3d ldr r3, [pc, #244] ; (8001ff4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8001f00: 6d9b ldr r3, [r3, #88] ; 0x58
8001f02: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001f06: 60bb str r3, [r7, #8]
8001f08: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8001f0a: 2301 movs r3, #1
8001f0c: 747b strb r3, [r7, #17]
}
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8001f0e: 4b3a ldr r3, [pc, #232] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x134>)
8001f10: 681b ldr r3, [r3, #0]
8001f12: 4a39 ldr r2, [pc, #228] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x134>)
8001f14: f443 7380 orr.w r3, r3, #256 ; 0x100
8001f18: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8001f1a: f7fe fdeb bl 8000af4 <HAL_GetTick>
8001f1e: 60f8 str r0, [r7, #12]
while((PWR->CR1 & PWR_CR1_DBP) == 0U)
8001f20: e009 b.n 8001f36 <HAL_RCCEx_PeriphCLKConfig+0x72>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001f22: f7fe fde7 bl 8000af4 <HAL_GetTick>
8001f26: 4602 mov r2, r0
8001f28: 68fb ldr r3, [r7, #12]
8001f2a: 1ad3 subs r3, r2, r3
8001f2c: 2b02 cmp r3, #2
8001f2e: d902 bls.n 8001f36 <HAL_RCCEx_PeriphCLKConfig+0x72>
{
ret = HAL_TIMEOUT;
8001f30: 2303 movs r3, #3
8001f32: 74fb strb r3, [r7, #19]
break;
8001f34: e005 b.n 8001f42 <HAL_RCCEx_PeriphCLKConfig+0x7e>
while((PWR->CR1 & PWR_CR1_DBP) == 0U)
8001f36: 4b30 ldr r3, [pc, #192] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x134>)
8001f38: 681b ldr r3, [r3, #0]
8001f3a: f403 7380 and.w r3, r3, #256 ; 0x100
8001f3e: 2b00 cmp r3, #0
8001f40: d0ef beq.n 8001f22 <HAL_RCCEx_PeriphCLKConfig+0x5e>
}
}
if(ret == HAL_OK)
8001f42: 7cfb ldrb r3, [r7, #19]
8001f44: 2b00 cmp r3, #0
8001f46: d159 bne.n 8001ffc <HAL_RCCEx_PeriphCLKConfig+0x138>
{
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
8001f48: 4b2a ldr r3, [pc, #168] ; (8001ff4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8001f4a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8001f4e: f403 7340 and.w r3, r3, #768 ; 0x300
8001f52: 617b str r3, [r7, #20]
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
8001f54: 697b ldr r3, [r7, #20]
8001f56: 2b00 cmp r3, #0
8001f58: d01e beq.n 8001f98 <HAL_RCCEx_PeriphCLKConfig+0xd4>
8001f5a: 687b ldr r3, [r7, #4]
8001f5c: 6d1b ldr r3, [r3, #80] ; 0x50
8001f5e: 697a ldr r2, [r7, #20]
8001f60: 429a cmp r2, r3
8001f62: d019 beq.n 8001f98 <HAL_RCCEx_PeriphCLKConfig+0xd4>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
8001f64: 4b23 ldr r3, [pc, #140] ; (8001ff4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8001f66: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8001f6a: f423 7340 bic.w r3, r3, #768 ; 0x300
8001f6e: 617b str r3, [r7, #20]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8001f70: 4b20 ldr r3, [pc, #128] ; (8001ff4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8001f72: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8001f76: 4a1f ldr r2, [pc, #124] ; (8001ff4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8001f78: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8001f7c: f8c2 3090 str.w r3, [r2, #144] ; 0x90
__HAL_RCC_BACKUPRESET_RELEASE();
8001f80: 4b1c ldr r3, [pc, #112] ; (8001ff4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8001f82: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8001f86: 4a1b ldr r2, [pc, #108] ; (8001ff4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8001f88: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8001f8c: f8c2 3090 str.w r3, [r2, #144] ; 0x90
/* Restore the Content of BDCR register */
RCC->BDCR = tmpregister;
8001f90: 4a18 ldr r2, [pc, #96] ; (8001ff4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8001f92: 697b ldr r3, [r7, #20]
8001f94: f8c2 3090 str.w r3, [r2, #144] ; 0x90
}
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
8001f98: 697b ldr r3, [r7, #20]
8001f9a: f003 0301 and.w r3, r3, #1
8001f9e: 2b00 cmp r3, #0
8001fa0: d016 beq.n 8001fd0 <HAL_RCCEx_PeriphCLKConfig+0x10c>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001fa2: f7fe fda7 bl 8000af4 <HAL_GetTick>
8001fa6: 60f8 str r0, [r7, #12]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8001fa8: e00b b.n 8001fc2 <HAL_RCCEx_PeriphCLKConfig+0xfe>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8001faa: f7fe fda3 bl 8000af4 <HAL_GetTick>
8001fae: 4602 mov r2, r0
8001fb0: 68fb ldr r3, [r7, #12]
8001fb2: 1ad3 subs r3, r2, r3
8001fb4: f241 3288 movw r2, #5000 ; 0x1388
8001fb8: 4293 cmp r3, r2
8001fba: d902 bls.n 8001fc2 <HAL_RCCEx_PeriphCLKConfig+0xfe>
{
ret = HAL_TIMEOUT;
8001fbc: 2303 movs r3, #3
8001fbe: 74fb strb r3, [r7, #19]
break;
8001fc0: e006 b.n 8001fd0 <HAL_RCCEx_PeriphCLKConfig+0x10c>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8001fc2: 4b0c ldr r3, [pc, #48] ; (8001ff4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8001fc4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8001fc8: f003 0302 and.w r3, r3, #2
8001fcc: 2b00 cmp r3, #0
8001fce: d0ec beq.n 8001faa <HAL_RCCEx_PeriphCLKConfig+0xe6>
}
}
}
if(ret == HAL_OK)
8001fd0: 7cfb ldrb r3, [r7, #19]
8001fd2: 2b00 cmp r3, #0
8001fd4: d10b bne.n 8001fee <HAL_RCCEx_PeriphCLKConfig+0x12a>
{
/* Apply new RTC clock source selection */
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8001fd6: 4b07 ldr r3, [pc, #28] ; (8001ff4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8001fd8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8001fdc: f423 7240 bic.w r2, r3, #768 ; 0x300
8001fe0: 687b ldr r3, [r7, #4]
8001fe2: 6d1b ldr r3, [r3, #80] ; 0x50
8001fe4: 4903 ldr r1, [pc, #12] ; (8001ff4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8001fe6: 4313 orrs r3, r2
8001fe8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
8001fec: e008 b.n 8002000 <HAL_RCCEx_PeriphCLKConfig+0x13c>
}
else
{
/* set overall return value */
status = ret;
8001fee: 7cfb ldrb r3, [r7, #19]
8001ff0: 74bb strb r3, [r7, #18]
8001ff2: e005 b.n 8002000 <HAL_RCCEx_PeriphCLKConfig+0x13c>
8001ff4: 40021000 .word 0x40021000
8001ff8: 40007000 .word 0x40007000
}
}
else
{
/* set overall return value */
status = ret;
8001ffc: 7cfb ldrb r3, [r7, #19]
8001ffe: 74bb strb r3, [r7, #18]
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8002000: 7c7b ldrb r3, [r7, #17]
8002002: 2b01 cmp r3, #1
8002004: d105 bne.n 8002012 <HAL_RCCEx_PeriphCLKConfig+0x14e>
{
__HAL_RCC_PWR_CLK_DISABLE();
8002006: 4baf ldr r3, [pc, #700] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002008: 6d9b ldr r3, [r3, #88] ; 0x58
800200a: 4aae ldr r2, [pc, #696] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
800200c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8002010: 6593 str r3, [r2, #88] ; 0x58
}
}
/*-------------------------- USART1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
8002012: 687b ldr r3, [r7, #4]
8002014: 681b ldr r3, [r3, #0]
8002016: f003 0301 and.w r3, r3, #1
800201a: 2b00 cmp r3, #0
800201c: d00a beq.n 8002034 <HAL_RCCEx_PeriphCLKConfig+0x170>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
800201e: 4ba9 ldr r3, [pc, #676] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002020: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8002024: f023 0203 bic.w r2, r3, #3
8002028: 687b ldr r3, [r7, #4]
800202a: 685b ldr r3, [r3, #4]
800202c: 49a5 ldr r1, [pc, #660] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
800202e: 4313 orrs r3, r2
8002030: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
/*-------------------------- USART2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
8002034: 687b ldr r3, [r7, #4]
8002036: 681b ldr r3, [r3, #0]
8002038: f003 0302 and.w r3, r3, #2
800203c: 2b00 cmp r3, #0
800203e: d00a beq.n 8002056 <HAL_RCCEx_PeriphCLKConfig+0x192>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
8002040: 4ba0 ldr r3, [pc, #640] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002042: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8002046: f023 020c bic.w r2, r3, #12
800204a: 687b ldr r3, [r7, #4]
800204c: 689b ldr r3, [r3, #8]
800204e: 499d ldr r1, [pc, #628] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002050: 4313 orrs r3, r2
8002052: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
/*-------------------------- USART3 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
8002056: 687b ldr r3, [r7, #4]
8002058: 681b ldr r3, [r3, #0]
800205a: f003 0304 and.w r3, r3, #4
800205e: 2b00 cmp r3, #0
8002060: d00a beq.n 8002078 <HAL_RCCEx_PeriphCLKConfig+0x1b4>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
8002062: 4b98 ldr r3, [pc, #608] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002064: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8002068: f023 0230 bic.w r2, r3, #48 ; 0x30
800206c: 687b ldr r3, [r7, #4]
800206e: 68db ldr r3, [r3, #12]
8002070: 4994 ldr r1, [pc, #592] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002072: 4313 orrs r3, r2
8002074: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
#if defined(UART4)
/*-------------------------- UART4 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
8002078: 687b ldr r3, [r7, #4]
800207a: 681b ldr r3, [r3, #0]
800207c: f003 0308 and.w r3, r3, #8
8002080: 2b00 cmp r3, #0
8002082: d00a beq.n 800209a <HAL_RCCEx_PeriphCLKConfig+0x1d6>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
8002084: 4b8f ldr r3, [pc, #572] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002086: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800208a: f023 02c0 bic.w r2, r3, #192 ; 0xc0
800208e: 687b ldr r3, [r7, #4]
8002090: 691b ldr r3, [r3, #16]
8002092: 498c ldr r1, [pc, #560] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002094: 4313 orrs r3, r2
8002096: f8c1 3088 str.w r3, [r1, #136] ; 0x88
#endif /* UART4 */
#if defined(UART5)
/*-------------------------- UART5 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
800209a: 687b ldr r3, [r7, #4]
800209c: 681b ldr r3, [r3, #0]
800209e: f003 0310 and.w r3, r3, #16
80020a2: 2b00 cmp r3, #0
80020a4: d00a beq.n 80020bc <HAL_RCCEx_PeriphCLKConfig+0x1f8>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
80020a6: 4b87 ldr r3, [pc, #540] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
80020a8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80020ac: f423 7240 bic.w r2, r3, #768 ; 0x300
80020b0: 687b ldr r3, [r7, #4]
80020b2: 695b ldr r3, [r3, #20]
80020b4: 4983 ldr r1, [pc, #524] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
80020b6: 4313 orrs r3, r2
80020b8: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
#endif /* UART5 */
/*-------------------------- LPUART1 clock source configuration ------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
80020bc: 687b ldr r3, [r7, #4]
80020be: 681b ldr r3, [r3, #0]
80020c0: f003 0320 and.w r3, r3, #32
80020c4: 2b00 cmp r3, #0
80020c6: d00a beq.n 80020de <HAL_RCCEx_PeriphCLKConfig+0x21a>
{
/* Check the parameters */
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
/* Configure the LPUAR1 clock source */
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
80020c8: 4b7e ldr r3, [pc, #504] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
80020ca: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80020ce: f423 6240 bic.w r2, r3, #3072 ; 0xc00
80020d2: 687b ldr r3, [r7, #4]
80020d4: 699b ldr r3, [r3, #24]
80020d6: 497b ldr r1, [pc, #492] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
80020d8: 4313 orrs r3, r2
80020da: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
/*-------------------------- I2C1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
80020de: 687b ldr r3, [r7, #4]
80020e0: 681b ldr r3, [r3, #0]
80020e2: f003 0340 and.w r3, r3, #64 ; 0x40
80020e6: 2b00 cmp r3, #0
80020e8: d00a beq.n 8002100 <HAL_RCCEx_PeriphCLKConfig+0x23c>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
80020ea: 4b76 ldr r3, [pc, #472] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
80020ec: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80020f0: f423 5240 bic.w r2, r3, #12288 ; 0x3000
80020f4: 687b ldr r3, [r7, #4]
80020f6: 69db ldr r3, [r3, #28]
80020f8: 4972 ldr r1, [pc, #456] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
80020fa: 4313 orrs r3, r2
80020fc: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
/*-------------------------- I2C2 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
8002100: 687b ldr r3, [r7, #4]
8002102: 681b ldr r3, [r3, #0]
8002104: f003 0380 and.w r3, r3, #128 ; 0x80
8002108: 2b00 cmp r3, #0
800210a: d00a beq.n 8002122 <HAL_RCCEx_PeriphCLKConfig+0x25e>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
800210c: 4b6d ldr r3, [pc, #436] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
800210e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8002112: f423 4240 bic.w r2, r3, #49152 ; 0xc000
8002116: 687b ldr r3, [r7, #4]
8002118: 6a1b ldr r3, [r3, #32]
800211a: 496a ldr r1, [pc, #424] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
800211c: 4313 orrs r3, r2
800211e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
/*-------------------------- I2C3 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
8002122: 687b ldr r3, [r7, #4]
8002124: 681b ldr r3, [r3, #0]
8002126: f403 7380 and.w r3, r3, #256 ; 0x100
800212a: 2b00 cmp r3, #0
800212c: d00a beq.n 8002144 <HAL_RCCEx_PeriphCLKConfig+0x280>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
800212e: 4b65 ldr r3, [pc, #404] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002130: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8002134: f423 3240 bic.w r2, r3, #196608 ; 0x30000
8002138: 687b ldr r3, [r7, #4]
800213a: 6a5b ldr r3, [r3, #36] ; 0x24
800213c: 4961 ldr r1, [pc, #388] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
800213e: 4313 orrs r3, r2
8002140: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
#if defined(I2C4)
/*-------------------------- I2C4 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
8002144: 687b ldr r3, [r7, #4]
8002146: 681b ldr r3, [r3, #0]
8002148: f403 3300 and.w r3, r3, #131072 ; 0x20000
800214c: 2b00 cmp r3, #0
800214e: d00a beq.n 8002166 <HAL_RCCEx_PeriphCLKConfig+0x2a2>
{
/* Check the parameters */
assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
/* Configure the I2C4 clock source */
__HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
8002150: 4b5c ldr r3, [pc, #368] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002152: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c
8002156: f023 0203 bic.w r2, r3, #3
800215a: 687b ldr r3, [r7, #4]
800215c: 6a9b ldr r3, [r3, #40] ; 0x28
800215e: 4959 ldr r1, [pc, #356] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002160: 4313 orrs r3, r2
8002162: f8c1 309c str.w r3, [r1, #156] ; 0x9c
}
#endif /* I2C4 */
/*-------------------------- LPTIM1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
8002166: 687b ldr r3, [r7, #4]
8002168: 681b ldr r3, [r3, #0]
800216a: f403 7300 and.w r3, r3, #512 ; 0x200
800216e: 2b00 cmp r3, #0
8002170: d00a beq.n 8002188 <HAL_RCCEx_PeriphCLKConfig+0x2c4>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LPTIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
8002172: 4b54 ldr r3, [pc, #336] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002174: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8002178: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
800217c: 687b ldr r3, [r7, #4]
800217e: 6adb ldr r3, [r3, #44] ; 0x2c
8002180: 4950 ldr r1, [pc, #320] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002182: 4313 orrs r3, r2
8002184: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
/*-------------------------- SAI1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
8002188: 687b ldr r3, [r7, #4]
800218a: 681b ldr r3, [r3, #0]
800218c: f403 6380 and.w r3, r3, #1024 ; 0x400
8002190: 2b00 cmp r3, #0
8002192: d015 beq.n 80021c0 <HAL_RCCEx_PeriphCLKConfig+0x2fc>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure the SAI1 interface clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
8002194: 4b4b ldr r3, [pc, #300] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002196: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800219a: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
800219e: 687b ldr r3, [r7, #4]
80021a0: 6b1b ldr r3, [r3, #48] ; 0x30
80021a2: 4948 ldr r1, [pc, #288] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
80021a4: 4313 orrs r3, r2
80021a6: f8c1 3088 str.w r3, [r1, #136] ; 0x88
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL)
80021aa: 687b ldr r3, [r7, #4]
80021ac: 6b1b ldr r3, [r3, #48] ; 0x30
80021ae: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
80021b2: d105 bne.n 80021c0 <HAL_RCCEx_PeriphCLKConfig+0x2fc>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
80021b4: 4b43 ldr r3, [pc, #268] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
80021b6: 68db ldr r3, [r3, #12]
80021b8: 4a42 ldr r2, [pc, #264] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
80021ba: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
80021be: 60d3 str r3, [r2, #12]
}
}
/*-------------------------- I2S clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
80021c0: 687b ldr r3, [r7, #4]
80021c2: 681b ldr r3, [r3, #0]
80021c4: f403 6300 and.w r3, r3, #2048 ; 0x800
80021c8: 2b00 cmp r3, #0
80021ca: d015 beq.n 80021f8 <HAL_RCCEx_PeriphCLKConfig+0x334>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure the I2S interface clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
80021cc: 4b3d ldr r3, [pc, #244] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
80021ce: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80021d2: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
80021d6: 687b ldr r3, [r7, #4]
80021d8: 6b5b ldr r3, [r3, #52] ; 0x34
80021da: 493a ldr r1, [pc, #232] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
80021dc: 4313 orrs r3, r2
80021de: f8c1 3088 str.w r3, [r1, #136] ; 0x88
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
80021e2: 687b ldr r3, [r7, #4]
80021e4: 6b5b ldr r3, [r3, #52] ; 0x34
80021e6: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
80021ea: d105 bne.n 80021f8 <HAL_RCCEx_PeriphCLKConfig+0x334>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
80021ec: 4b35 ldr r3, [pc, #212] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
80021ee: 68db ldr r3, [r3, #12]
80021f0: 4a34 ldr r2, [pc, #208] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
80021f2: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
80021f6: 60d3 str r3, [r2, #12]
}
}
#if defined(FDCAN1)
/*-------------------------- FDCAN clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
80021f8: 687b ldr r3, [r7, #4]
80021fa: 681b ldr r3, [r3, #0]
80021fc: f403 5380 and.w r3, r3, #4096 ; 0x1000
8002200: 2b00 cmp r3, #0
8002202: d015 beq.n 8002230 <HAL_RCCEx_PeriphCLKConfig+0x36c>
{
/* Check the parameters */
assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
/* Configure the FDCAN interface clock source */
__HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
8002204: 4b2f ldr r3, [pc, #188] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002206: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800220a: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
800220e: 687b ldr r3, [r7, #4]
8002210: 6b9b ldr r3, [r3, #56] ; 0x38
8002212: 492c ldr r1, [pc, #176] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002214: 4313 orrs r3, r2
8002216: f8c1 3088 str.w r3, [r1, #136] ; 0x88
if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL)
800221a: 687b ldr r3, [r7, #4]
800221c: 6b9b ldr r3, [r3, #56] ; 0x38
800221e: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8002222: d105 bne.n 8002230 <HAL_RCCEx_PeriphCLKConfig+0x36c>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8002224: 4b27 ldr r3, [pc, #156] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002226: 68db ldr r3, [r3, #12]
8002228: 4a26 ldr r2, [pc, #152] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
800222a: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
800222e: 60d3 str r3, [r2, #12]
#endif /* FDCAN1 */
#if defined(USB)
/*-------------------------- USB clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
8002230: 687b ldr r3, [r7, #4]
8002232: 681b ldr r3, [r3, #0]
8002234: f403 5300 and.w r3, r3, #8192 ; 0x2000
8002238: 2b00 cmp r3, #0
800223a: d015 beq.n 8002268 <HAL_RCCEx_PeriphCLKConfig+0x3a4>
{
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
800223c: 4b21 ldr r3, [pc, #132] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
800223e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8002242: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000
8002246: 687b ldr r3, [r7, #4]
8002248: 6bdb ldr r3, [r3, #60] ; 0x3c
800224a: 491e ldr r1, [pc, #120] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
800224c: 4313 orrs r3, r2
800224e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
8002252: 687b ldr r3, [r7, #4]
8002254: 6bdb ldr r3, [r3, #60] ; 0x3c
8002256: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
800225a: d105 bne.n 8002268 <HAL_RCCEx_PeriphCLKConfig+0x3a4>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
800225c: 4b19 ldr r3, [pc, #100] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
800225e: 68db ldr r3, [r3, #12]
8002260: 4a18 ldr r2, [pc, #96] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002262: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
8002266: 60d3 str r3, [r2, #12]
}
#endif /* USB */
/*-------------------------- RNG clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
8002268: 687b ldr r3, [r7, #4]
800226a: 681b ldr r3, [r3, #0]
800226c: f403 4380 and.w r3, r3, #16384 ; 0x4000
8002270: 2b00 cmp r3, #0
8002272: d015 beq.n 80022a0 <HAL_RCCEx_PeriphCLKConfig+0x3dc>
{
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
8002274: 4b13 ldr r3, [pc, #76] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002276: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800227a: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000
800227e: 687b ldr r3, [r7, #4]
8002280: 6c1b ldr r3, [r3, #64] ; 0x40
8002282: 4910 ldr r1, [pc, #64] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002284: 4313 orrs r3, r2
8002286: f8c1 3088 str.w r3, [r1, #136] ; 0x88
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
800228a: 687b ldr r3, [r7, #4]
800228c: 6c1b ldr r3, [r3, #64] ; 0x40
800228e: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
8002292: d105 bne.n 80022a0 <HAL_RCCEx_PeriphCLKConfig+0x3dc>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8002294: 4b0b ldr r3, [pc, #44] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
8002296: 68db ldr r3, [r3, #12]
8002298: 4a0a ldr r2, [pc, #40] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
800229a: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
800229e: 60d3 str r3, [r2, #12]
}
}
/*-------------------------- ADC12 clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
80022a0: 687b ldr r3, [r7, #4]
80022a2: 681b ldr r3, [r3, #0]
80022a4: f403 4300 and.w r3, r3, #32768 ; 0x8000
80022a8: 2b00 cmp r3, #0
80022aa: d018 beq.n 80022de <HAL_RCCEx_PeriphCLKConfig+0x41a>
{
/* Check the parameters */
assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection));
/* Configure the ADC12 interface clock source */
__HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
80022ac: 4b05 ldr r3, [pc, #20] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
80022ae: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80022b2: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000
80022b6: 687b ldr r3, [r7, #4]
80022b8: 6c5b ldr r3, [r3, #68] ; 0x44
80022ba: 4902 ldr r1, [pc, #8] ; (80022c4 <HAL_RCCEx_PeriphCLKConfig+0x400>)
80022bc: 4313 orrs r3, r2
80022be: f8c1 3088 str.w r3, [r1, #136] ; 0x88
80022c2: e001 b.n 80022c8 <HAL_RCCEx_PeriphCLKConfig+0x404>
80022c4: 40021000 .word 0x40021000
if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL)
80022c8: 687b ldr r3, [r7, #4]
80022ca: 6c5b ldr r3, [r3, #68] ; 0x44
80022cc: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
80022d0: d105 bne.n 80022de <HAL_RCCEx_PeriphCLKConfig+0x41a>
{
/* Enable PLLADCCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
80022d2: 4b21 ldr r3, [pc, #132] ; (8002358 <HAL_RCCEx_PeriphCLKConfig+0x494>)
80022d4: 68db ldr r3, [r3, #12]
80022d6: 4a20 ldr r2, [pc, #128] ; (8002358 <HAL_RCCEx_PeriphCLKConfig+0x494>)
80022d8: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80022dc: 60d3 str r3, [r2, #12]
}
}
#if defined(ADC345_COMMON)
/*-------------------------- ADC345 clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345)
80022de: 687b ldr r3, [r7, #4]
80022e0: 681b ldr r3, [r3, #0]
80022e2: f403 3380 and.w r3, r3, #65536 ; 0x10000
80022e6: 2b00 cmp r3, #0
80022e8: d015 beq.n 8002316 <HAL_RCCEx_PeriphCLKConfig+0x452>
{
/* Check the parameters */
assert_param(IS_RCC_ADC345CLKSOURCE(PeriphClkInit->Adc345ClockSelection));
/* Configure the ADC345 interface clock source */
__HAL_RCC_ADC345_CONFIG(PeriphClkInit->Adc345ClockSelection);
80022ea: 4b1b ldr r3, [pc, #108] ; (8002358 <HAL_RCCEx_PeriphCLKConfig+0x494>)
80022ec: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80022f0: f023 4240 bic.w r2, r3, #3221225472 ; 0xc0000000
80022f4: 687b ldr r3, [r7, #4]
80022f6: 6c9b ldr r3, [r3, #72] ; 0x48
80022f8: 4917 ldr r1, [pc, #92] ; (8002358 <HAL_RCCEx_PeriphCLKConfig+0x494>)
80022fa: 4313 orrs r3, r2
80022fc: f8c1 3088 str.w r3, [r1, #136] ; 0x88
if(PeriphClkInit->Adc345ClockSelection == RCC_ADC345CLKSOURCE_PLL)
8002300: 687b ldr r3, [r7, #4]
8002302: 6c9b ldr r3, [r3, #72] ; 0x48
8002304: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8002308: d105 bne.n 8002316 <HAL_RCCEx_PeriphCLKConfig+0x452>
{
/* Enable PLLADCCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
800230a: 4b13 ldr r3, [pc, #76] ; (8002358 <HAL_RCCEx_PeriphCLKConfig+0x494>)
800230c: 68db ldr r3, [r3, #12]
800230e: 4a12 ldr r2, [pc, #72] ; (8002358 <HAL_RCCEx_PeriphCLKConfig+0x494>)
8002310: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8002314: 60d3 str r3, [r2, #12]
#endif /* ADC345_COMMON */
#if defined(QUADSPI)
/*-------------------------- QuadSPIx clock source configuration ----------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
8002316: 687b ldr r3, [r7, #4]
8002318: 681b ldr r3, [r3, #0]
800231a: f403 2380 and.w r3, r3, #262144 ; 0x40000
800231e: 2b00 cmp r3, #0
8002320: d015 beq.n 800234e <HAL_RCCEx_PeriphCLKConfig+0x48a>
{
/* Check the parameters */
assert_param(IS_RCC_QSPICLKSOURCE(PeriphClkInit->QspiClockSelection));
/* Configure the QuadSPI clock source */
__HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
8002322: 4b0d ldr r3, [pc, #52] ; (8002358 <HAL_RCCEx_PeriphCLKConfig+0x494>)
8002324: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c
8002328: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
800232c: 687b ldr r3, [r7, #4]
800232e: 6cdb ldr r3, [r3, #76] ; 0x4c
8002330: 4909 ldr r1, [pc, #36] ; (8002358 <HAL_RCCEx_PeriphCLKConfig+0x494>)
8002332: 4313 orrs r3, r2
8002334: f8c1 309c str.w r3, [r1, #156] ; 0x9c
if(PeriphClkInit->QspiClockSelection == RCC_QSPICLKSOURCE_PLL)
8002338: 687b ldr r3, [r7, #4]
800233a: 6cdb ldr r3, [r3, #76] ; 0x4c
800233c: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000
8002340: d105 bne.n 800234e <HAL_RCCEx_PeriphCLKConfig+0x48a>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8002342: 4b05 ldr r3, [pc, #20] ; (8002358 <HAL_RCCEx_PeriphCLKConfig+0x494>)
8002344: 68db ldr r3, [r3, #12]
8002346: 4a04 ldr r2, [pc, #16] ; (8002358 <HAL_RCCEx_PeriphCLKConfig+0x494>)
8002348: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
800234c: 60d3 str r3, [r2, #12]
}
}
#endif /* QUADSPI */
return status;
800234e: 7cbb ldrb r3, [r7, #18]
}
8002350: 4618 mov r0, r3
8002352: 3718 adds r7, #24
8002354: 46bd mov sp, r7
8002356: bd80 pop {r7, pc}
8002358: 40021000 .word 0x40021000
0800235c <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
800235c: b580 push {r7, lr}
800235e: b082 sub sp, #8
8002360: af00 add r7, sp, #0
8002362: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8002364: 687b ldr r3, [r7, #4]
8002366: 2b00 cmp r3, #0
8002368: d101 bne.n 800236e <HAL_UART_Init+0x12>
{
return HAL_ERROR;
800236a: 2301 movs r3, #1
800236c: e042 b.n 80023f4 <HAL_UART_Init+0x98>
{
/* Check the parameters */
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
}
if (huart->gState == HAL_UART_STATE_RESET)
800236e: 687b ldr r3, [r7, #4]
8002370: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8002374: 2b00 cmp r3, #0
8002376: d106 bne.n 8002386 <HAL_UART_Init+0x2a>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8002378: 687b ldr r3, [r7, #4]
800237a: 2200 movs r2, #0
800237c: f883 2080 strb.w r2, [r3, #128] ; 0x80
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8002380: 6878 ldr r0, [r7, #4]
8002382: f7fe fae7 bl 8000954 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8002386: 687b ldr r3, [r7, #4]
8002388: 2224 movs r2, #36 ; 0x24
800238a: f8c3 2084 str.w r2, [r3, #132] ; 0x84
__HAL_UART_DISABLE(huart);
800238e: 687b ldr r3, [r7, #4]
8002390: 681b ldr r3, [r3, #0]
8002392: 681a ldr r2, [r3, #0]
8002394: 687b ldr r3, [r7, #4]
8002396: 681b ldr r3, [r3, #0]
8002398: f022 0201 bic.w r2, r2, #1
800239c: 601a str r2, [r3, #0]
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
800239e: 6878 ldr r0, [r7, #4]
80023a0: f000 f82c bl 80023fc <UART_SetConfig>
80023a4: 4603 mov r3, r0
80023a6: 2b01 cmp r3, #1
80023a8: d101 bne.n 80023ae <HAL_UART_Init+0x52>
{
return HAL_ERROR;
80023aa: 2301 movs r3, #1
80023ac: e022 b.n 80023f4 <HAL_UART_Init+0x98>
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
80023ae: 687b ldr r3, [r7, #4]
80023b0: 6a9b ldr r3, [r3, #40] ; 0x28
80023b2: 2b00 cmp r3, #0
80023b4: d002 beq.n 80023bc <HAL_UART_Init+0x60>
{
UART_AdvFeatureConfig(huart);
80023b6: 6878 ldr r0, [r7, #4]
80023b8: f000 faea bl 8002990 <UART_AdvFeatureConfig>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
80023bc: 687b ldr r3, [r7, #4]
80023be: 681b ldr r3, [r3, #0]
80023c0: 685a ldr r2, [r3, #4]
80023c2: 687b ldr r3, [r7, #4]
80023c4: 681b ldr r3, [r3, #0]
80023c6: f422 4290 bic.w r2, r2, #18432 ; 0x4800
80023ca: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
80023cc: 687b ldr r3, [r7, #4]
80023ce: 681b ldr r3, [r3, #0]
80023d0: 689a ldr r2, [r3, #8]
80023d2: 687b ldr r3, [r7, #4]
80023d4: 681b ldr r3, [r3, #0]
80023d6: f022 022a bic.w r2, r2, #42 ; 0x2a
80023da: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
80023dc: 687b ldr r3, [r7, #4]
80023de: 681b ldr r3, [r3, #0]
80023e0: 681a ldr r2, [r3, #0]
80023e2: 687b ldr r3, [r7, #4]
80023e4: 681b ldr r3, [r3, #0]
80023e6: f042 0201 orr.w r2, r2, #1
80023ea: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
80023ec: 6878 ldr r0, [r7, #4]
80023ee: f000 fb71 bl 8002ad4 <UART_CheckIdleState>
80023f2: 4603 mov r3, r0
}
80023f4: 4618 mov r0, r3
80023f6: 3708 adds r7, #8
80023f8: 46bd mov sp, r7
80023fa: bd80 pop {r7, pc}
080023fc <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
80023fc: b5b0 push {r4, r5, r7, lr}
80023fe: b088 sub sp, #32
8002400: af00 add r7, sp, #0
8002402: 6078 str r0, [r7, #4]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
8002404: 2300 movs r3, #0
8002406: 76bb strb r3, [r7, #26]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8002408: 687b ldr r3, [r7, #4]
800240a: 689a ldr r2, [r3, #8]
800240c: 687b ldr r3, [r7, #4]
800240e: 691b ldr r3, [r3, #16]
8002410: 431a orrs r2, r3
8002412: 687b ldr r3, [r7, #4]
8002414: 695b ldr r3, [r3, #20]
8002416: 431a orrs r2, r3
8002418: 687b ldr r3, [r7, #4]
800241a: 69db ldr r3, [r3, #28]
800241c: 4313 orrs r3, r2
800241e: 61fb str r3, [r7, #28]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8002420: 687b ldr r3, [r7, #4]
8002422: 681b ldr r3, [r3, #0]
8002424: 681a ldr r2, [r3, #0]
8002426: 4bb1 ldr r3, [pc, #708] ; (80026ec <UART_SetConfig+0x2f0>)
8002428: 4013 ands r3, r2
800242a: 687a ldr r2, [r7, #4]
800242c: 6812 ldr r2, [r2, #0]
800242e: 69f9 ldr r1, [r7, #28]
8002430: 430b orrs r3, r1
8002432: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8002434: 687b ldr r3, [r7, #4]
8002436: 681b ldr r3, [r3, #0]
8002438: 685b ldr r3, [r3, #4]
800243a: f423 5140 bic.w r1, r3, #12288 ; 0x3000
800243e: 687b ldr r3, [r7, #4]
8002440: 68da ldr r2, [r3, #12]
8002442: 687b ldr r3, [r7, #4]
8002444: 681b ldr r3, [r3, #0]
8002446: 430a orrs r2, r1
8002448: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
800244a: 687b ldr r3, [r7, #4]
800244c: 699b ldr r3, [r3, #24]
800244e: 61fb str r3, [r7, #28]
if (!(UART_INSTANCE_LOWPOWER(huart)))
8002450: 687b ldr r3, [r7, #4]
8002452: 681b ldr r3, [r3, #0]
8002454: 4aa6 ldr r2, [pc, #664] ; (80026f0 <UART_SetConfig+0x2f4>)
8002456: 4293 cmp r3, r2
8002458: d004 beq.n 8002464 <UART_SetConfig+0x68>
{
tmpreg |= huart->Init.OneBitSampling;
800245a: 687b ldr r3, [r7, #4]
800245c: 6a1b ldr r3, [r3, #32]
800245e: 69fa ldr r2, [r7, #28]
8002460: 4313 orrs r3, r2
8002462: 61fb str r3, [r7, #28]
}
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8002464: 687b ldr r3, [r7, #4]
8002466: 681b ldr r3, [r3, #0]
8002468: 689b ldr r3, [r3, #8]
800246a: f023 436e bic.w r3, r3, #3992977408 ; 0xee000000
800246e: f423 6330 bic.w r3, r3, #2816 ; 0xb00
8002472: 687a ldr r2, [r7, #4]
8002474: 6812 ldr r2, [r2, #0]
8002476: 69f9 ldr r1, [r7, #28]
8002478: 430b orrs r3, r1
800247a: 6093 str r3, [r2, #8]
/*-------------------------- USART PRESC Configuration -----------------------*/
/* Configure
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
800247c: 687b ldr r3, [r7, #4]
800247e: 681b ldr r3, [r3, #0]
8002480: 6adb ldr r3, [r3, #44] ; 0x2c
8002482: f023 010f bic.w r1, r3, #15
8002486: 687b ldr r3, [r7, #4]
8002488: 6a5a ldr r2, [r3, #36] ; 0x24
800248a: 687b ldr r3, [r7, #4]
800248c: 681b ldr r3, [r3, #0]
800248e: 430a orrs r2, r1
8002490: 62da str r2, [r3, #44] ; 0x2c
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
8002492: 687b ldr r3, [r7, #4]
8002494: 681b ldr r3, [r3, #0]
8002496: 4a97 ldr r2, [pc, #604] ; (80026f4 <UART_SetConfig+0x2f8>)
8002498: 4293 cmp r3, r2
800249a: d120 bne.n 80024de <UART_SetConfig+0xe2>
800249c: 4b96 ldr r3, [pc, #600] ; (80026f8 <UART_SetConfig+0x2fc>)
800249e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80024a2: f003 0303 and.w r3, r3, #3
80024a6: 2b03 cmp r3, #3
80024a8: d816 bhi.n 80024d8 <UART_SetConfig+0xdc>
80024aa: a201 add r2, pc, #4 ; (adr r2, 80024b0 <UART_SetConfig+0xb4>)
80024ac: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80024b0: 080024c1 .word 0x080024c1
80024b4: 080024cd .word 0x080024cd
80024b8: 080024c7 .word 0x080024c7
80024bc: 080024d3 .word 0x080024d3
80024c0: 2301 movs r3, #1
80024c2: 76fb strb r3, [r7, #27]
80024c4: e0e7 b.n 8002696 <UART_SetConfig+0x29a>
80024c6: 2302 movs r3, #2
80024c8: 76fb strb r3, [r7, #27]
80024ca: e0e4 b.n 8002696 <UART_SetConfig+0x29a>
80024cc: 2304 movs r3, #4
80024ce: 76fb strb r3, [r7, #27]
80024d0: e0e1 b.n 8002696 <UART_SetConfig+0x29a>
80024d2: 2308 movs r3, #8
80024d4: 76fb strb r3, [r7, #27]
80024d6: e0de b.n 8002696 <UART_SetConfig+0x29a>
80024d8: 2310 movs r3, #16
80024da: 76fb strb r3, [r7, #27]
80024dc: e0db b.n 8002696 <UART_SetConfig+0x29a>
80024de: 687b ldr r3, [r7, #4]
80024e0: 681b ldr r3, [r3, #0]
80024e2: 4a86 ldr r2, [pc, #536] ; (80026fc <UART_SetConfig+0x300>)
80024e4: 4293 cmp r3, r2
80024e6: d132 bne.n 800254e <UART_SetConfig+0x152>
80024e8: 4b83 ldr r3, [pc, #524] ; (80026f8 <UART_SetConfig+0x2fc>)
80024ea: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80024ee: f003 030c and.w r3, r3, #12
80024f2: 2b0c cmp r3, #12
80024f4: d828 bhi.n 8002548 <UART_SetConfig+0x14c>
80024f6: a201 add r2, pc, #4 ; (adr r2, 80024fc <UART_SetConfig+0x100>)
80024f8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80024fc: 08002531 .word 0x08002531
8002500: 08002549 .word 0x08002549
8002504: 08002549 .word 0x08002549
8002508: 08002549 .word 0x08002549
800250c: 0800253d .word 0x0800253d
8002510: 08002549 .word 0x08002549
8002514: 08002549 .word 0x08002549
8002518: 08002549 .word 0x08002549
800251c: 08002537 .word 0x08002537
8002520: 08002549 .word 0x08002549
8002524: 08002549 .word 0x08002549
8002528: 08002549 .word 0x08002549
800252c: 08002543 .word 0x08002543
8002530: 2300 movs r3, #0
8002532: 76fb strb r3, [r7, #27]
8002534: e0af b.n 8002696 <UART_SetConfig+0x29a>
8002536: 2302 movs r3, #2
8002538: 76fb strb r3, [r7, #27]
800253a: e0ac b.n 8002696 <UART_SetConfig+0x29a>
800253c: 2304 movs r3, #4
800253e: 76fb strb r3, [r7, #27]
8002540: e0a9 b.n 8002696 <UART_SetConfig+0x29a>
8002542: 2308 movs r3, #8
8002544: 76fb strb r3, [r7, #27]
8002546: e0a6 b.n 8002696 <UART_SetConfig+0x29a>
8002548: 2310 movs r3, #16
800254a: 76fb strb r3, [r7, #27]
800254c: e0a3 b.n 8002696 <UART_SetConfig+0x29a>
800254e: 687b ldr r3, [r7, #4]
8002550: 681b ldr r3, [r3, #0]
8002552: 4a6b ldr r2, [pc, #428] ; (8002700 <UART_SetConfig+0x304>)
8002554: 4293 cmp r3, r2
8002556: d120 bne.n 800259a <UART_SetConfig+0x19e>
8002558: 4b67 ldr r3, [pc, #412] ; (80026f8 <UART_SetConfig+0x2fc>)
800255a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800255e: f003 0330 and.w r3, r3, #48 ; 0x30
8002562: 2b30 cmp r3, #48 ; 0x30
8002564: d013 beq.n 800258e <UART_SetConfig+0x192>
8002566: 2b30 cmp r3, #48 ; 0x30
8002568: d814 bhi.n 8002594 <UART_SetConfig+0x198>
800256a: 2b20 cmp r3, #32
800256c: d009 beq.n 8002582 <UART_SetConfig+0x186>
800256e: 2b20 cmp r3, #32
8002570: d810 bhi.n 8002594 <UART_SetConfig+0x198>
8002572: 2b00 cmp r3, #0
8002574: d002 beq.n 800257c <UART_SetConfig+0x180>
8002576: 2b10 cmp r3, #16
8002578: d006 beq.n 8002588 <UART_SetConfig+0x18c>
800257a: e00b b.n 8002594 <UART_SetConfig+0x198>
800257c: 2300 movs r3, #0
800257e: 76fb strb r3, [r7, #27]
8002580: e089 b.n 8002696 <UART_SetConfig+0x29a>
8002582: 2302 movs r3, #2
8002584: 76fb strb r3, [r7, #27]
8002586: e086 b.n 8002696 <UART_SetConfig+0x29a>
8002588: 2304 movs r3, #4
800258a: 76fb strb r3, [r7, #27]
800258c: e083 b.n 8002696 <UART_SetConfig+0x29a>
800258e: 2308 movs r3, #8
8002590: 76fb strb r3, [r7, #27]
8002592: e080 b.n 8002696 <UART_SetConfig+0x29a>
8002594: 2310 movs r3, #16
8002596: 76fb strb r3, [r7, #27]
8002598: e07d b.n 8002696 <UART_SetConfig+0x29a>
800259a: 687b ldr r3, [r7, #4]
800259c: 681b ldr r3, [r3, #0]
800259e: 4a59 ldr r2, [pc, #356] ; (8002704 <UART_SetConfig+0x308>)
80025a0: 4293 cmp r3, r2
80025a2: d120 bne.n 80025e6 <UART_SetConfig+0x1ea>
80025a4: 4b54 ldr r3, [pc, #336] ; (80026f8 <UART_SetConfig+0x2fc>)
80025a6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80025aa: f003 03c0 and.w r3, r3, #192 ; 0xc0
80025ae: 2bc0 cmp r3, #192 ; 0xc0
80025b0: d013 beq.n 80025da <UART_SetConfig+0x1de>
80025b2: 2bc0 cmp r3, #192 ; 0xc0
80025b4: d814 bhi.n 80025e0 <UART_SetConfig+0x1e4>
80025b6: 2b80 cmp r3, #128 ; 0x80
80025b8: d009 beq.n 80025ce <UART_SetConfig+0x1d2>
80025ba: 2b80 cmp r3, #128 ; 0x80
80025bc: d810 bhi.n 80025e0 <UART_SetConfig+0x1e4>
80025be: 2b00 cmp r3, #0
80025c0: d002 beq.n 80025c8 <UART_SetConfig+0x1cc>
80025c2: 2b40 cmp r3, #64 ; 0x40
80025c4: d006 beq.n 80025d4 <UART_SetConfig+0x1d8>
80025c6: e00b b.n 80025e0 <UART_SetConfig+0x1e4>
80025c8: 2300 movs r3, #0
80025ca: 76fb strb r3, [r7, #27]
80025cc: e063 b.n 8002696 <UART_SetConfig+0x29a>
80025ce: 2302 movs r3, #2
80025d0: 76fb strb r3, [r7, #27]
80025d2: e060 b.n 8002696 <UART_SetConfig+0x29a>
80025d4: 2304 movs r3, #4
80025d6: 76fb strb r3, [r7, #27]
80025d8: e05d b.n 8002696 <UART_SetConfig+0x29a>
80025da: 2308 movs r3, #8
80025dc: 76fb strb r3, [r7, #27]
80025de: e05a b.n 8002696 <UART_SetConfig+0x29a>
80025e0: 2310 movs r3, #16
80025e2: 76fb strb r3, [r7, #27]
80025e4: e057 b.n 8002696 <UART_SetConfig+0x29a>
80025e6: 687b ldr r3, [r7, #4]
80025e8: 681b ldr r3, [r3, #0]
80025ea: 4a47 ldr r2, [pc, #284] ; (8002708 <UART_SetConfig+0x30c>)
80025ec: 4293 cmp r3, r2
80025ee: d125 bne.n 800263c <UART_SetConfig+0x240>
80025f0: 4b41 ldr r3, [pc, #260] ; (80026f8 <UART_SetConfig+0x2fc>)
80025f2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80025f6: f403 7340 and.w r3, r3, #768 ; 0x300
80025fa: f5b3 7f40 cmp.w r3, #768 ; 0x300
80025fe: d017 beq.n 8002630 <UART_SetConfig+0x234>
8002600: f5b3 7f40 cmp.w r3, #768 ; 0x300
8002604: d817 bhi.n 8002636 <UART_SetConfig+0x23a>
8002606: f5b3 7f00 cmp.w r3, #512 ; 0x200
800260a: d00b beq.n 8002624 <UART_SetConfig+0x228>
800260c: f5b3 7f00 cmp.w r3, #512 ; 0x200
8002610: d811 bhi.n 8002636 <UART_SetConfig+0x23a>
8002612: 2b00 cmp r3, #0
8002614: d003 beq.n 800261e <UART_SetConfig+0x222>
8002616: f5b3 7f80 cmp.w r3, #256 ; 0x100
800261a: d006 beq.n 800262a <UART_SetConfig+0x22e>
800261c: e00b b.n 8002636 <UART_SetConfig+0x23a>
800261e: 2300 movs r3, #0
8002620: 76fb strb r3, [r7, #27]
8002622: e038 b.n 8002696 <UART_SetConfig+0x29a>
8002624: 2302 movs r3, #2
8002626: 76fb strb r3, [r7, #27]
8002628: e035 b.n 8002696 <UART_SetConfig+0x29a>
800262a: 2304 movs r3, #4
800262c: 76fb strb r3, [r7, #27]
800262e: e032 b.n 8002696 <UART_SetConfig+0x29a>
8002630: 2308 movs r3, #8
8002632: 76fb strb r3, [r7, #27]
8002634: e02f b.n 8002696 <UART_SetConfig+0x29a>
8002636: 2310 movs r3, #16
8002638: 76fb strb r3, [r7, #27]
800263a: e02c b.n 8002696 <UART_SetConfig+0x29a>
800263c: 687b ldr r3, [r7, #4]
800263e: 681b ldr r3, [r3, #0]
8002640: 4a2b ldr r2, [pc, #172] ; (80026f0 <UART_SetConfig+0x2f4>)
8002642: 4293 cmp r3, r2
8002644: d125 bne.n 8002692 <UART_SetConfig+0x296>
8002646: 4b2c ldr r3, [pc, #176] ; (80026f8 <UART_SetConfig+0x2fc>)
8002648: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800264c: f403 6340 and.w r3, r3, #3072 ; 0xc00
8002650: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
8002654: d017 beq.n 8002686 <UART_SetConfig+0x28a>
8002656: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
800265a: d817 bhi.n 800268c <UART_SetConfig+0x290>
800265c: f5b3 6f00 cmp.w r3, #2048 ; 0x800
8002660: d00b beq.n 800267a <UART_SetConfig+0x27e>
8002662: f5b3 6f00 cmp.w r3, #2048 ; 0x800
8002666: d811 bhi.n 800268c <UART_SetConfig+0x290>
8002668: 2b00 cmp r3, #0
800266a: d003 beq.n 8002674 <UART_SetConfig+0x278>
800266c: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8002670: d006 beq.n 8002680 <UART_SetConfig+0x284>
8002672: e00b b.n 800268c <UART_SetConfig+0x290>
8002674: 2300 movs r3, #0
8002676: 76fb strb r3, [r7, #27]
8002678: e00d b.n 8002696 <UART_SetConfig+0x29a>
800267a: 2302 movs r3, #2
800267c: 76fb strb r3, [r7, #27]
800267e: e00a b.n 8002696 <UART_SetConfig+0x29a>
8002680: 2304 movs r3, #4
8002682: 76fb strb r3, [r7, #27]
8002684: e007 b.n 8002696 <UART_SetConfig+0x29a>
8002686: 2308 movs r3, #8
8002688: 76fb strb r3, [r7, #27]
800268a: e004 b.n 8002696 <UART_SetConfig+0x29a>
800268c: 2310 movs r3, #16
800268e: 76fb strb r3, [r7, #27]
8002690: e001 b.n 8002696 <UART_SetConfig+0x29a>
8002692: 2310 movs r3, #16
8002694: 76fb strb r3, [r7, #27]
/* Check LPUART instance */
if (UART_INSTANCE_LOWPOWER(huart))
8002696: 687b ldr r3, [r7, #4]
8002698: 681b ldr r3, [r3, #0]
800269a: 4a15 ldr r2, [pc, #84] ; (80026f0 <UART_SetConfig+0x2f4>)
800269c: 4293 cmp r3, r2
800269e: f040 809f bne.w 80027e0 <UART_SetConfig+0x3e4>
{
/* Retrieve frequency clock */
switch (clocksource)
80026a2: 7efb ldrb r3, [r7, #27]
80026a4: 2b08 cmp r3, #8
80026a6: d837 bhi.n 8002718 <UART_SetConfig+0x31c>
80026a8: a201 add r2, pc, #4 ; (adr r2, 80026b0 <UART_SetConfig+0x2b4>)
80026aa: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80026ae: bf00 nop
80026b0: 080026d5 .word 0x080026d5
80026b4: 08002719 .word 0x08002719
80026b8: 080026dd .word 0x080026dd
80026bc: 08002719 .word 0x08002719
80026c0: 080026e3 .word 0x080026e3
80026c4: 08002719 .word 0x08002719
80026c8: 08002719 .word 0x08002719
80026cc: 08002719 .word 0x08002719
80026d0: 08002711 .word 0x08002711
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
80026d4: f7ff fb84 bl 8001de0 <HAL_RCC_GetPCLK1Freq>
80026d8: 6178 str r0, [r7, #20]
break;
80026da: e022 b.n 8002722 <UART_SetConfig+0x326>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
80026dc: 4b0b ldr r3, [pc, #44] ; (800270c <UART_SetConfig+0x310>)
80026de: 617b str r3, [r7, #20]
break;
80026e0: e01f b.n 8002722 <UART_SetConfig+0x326>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80026e2: f7ff fb0f bl 8001d04 <HAL_RCC_GetSysClockFreq>
80026e6: 6178 str r0, [r7, #20]
break;
80026e8: e01b b.n 8002722 <UART_SetConfig+0x326>
80026ea: bf00 nop
80026ec: cfff69f3 .word 0xcfff69f3
80026f0: 40008000 .word 0x40008000
80026f4: 40013800 .word 0x40013800
80026f8: 40021000 .word 0x40021000
80026fc: 40004400 .word 0x40004400
8002700: 40004800 .word 0x40004800
8002704: 40004c00 .word 0x40004c00
8002708: 40005000 .word 0x40005000
800270c: 00f42400 .word 0x00f42400
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8002710: f44f 4300 mov.w r3, #32768 ; 0x8000
8002714: 617b str r3, [r7, #20]
break;
8002716: e004 b.n 8002722 <UART_SetConfig+0x326>
default:
pclk = 0U;
8002718: 2300 movs r3, #0
800271a: 617b str r3, [r7, #20]
ret = HAL_ERROR;
800271c: 2301 movs r3, #1
800271e: 76bb strb r3, [r7, #26]
break;
8002720: bf00 nop
}
/* If proper clock source reported */
if (pclk != 0U)
8002722: 697b ldr r3, [r7, #20]
8002724: 2b00 cmp r3, #0
8002726: f000 811b beq.w 8002960 <UART_SetConfig+0x564>
{
/* Compute clock after Prescaler */
lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
800272a: 687b ldr r3, [r7, #4]
800272c: 6a5b ldr r3, [r3, #36] ; 0x24
800272e: 4a96 ldr r2, [pc, #600] ; (8002988 <UART_SetConfig+0x58c>)
8002730: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
8002734: 461a mov r2, r3
8002736: 697b ldr r3, [r7, #20]
8002738: fbb3 f3f2 udiv r3, r3, r2
800273c: 60bb str r3, [r7, #8]
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
800273e: 687b ldr r3, [r7, #4]
8002740: 685a ldr r2, [r3, #4]
8002742: 4613 mov r3, r2
8002744: 005b lsls r3, r3, #1
8002746: 4413 add r3, r2
8002748: 68ba ldr r2, [r7, #8]
800274a: 429a cmp r2, r3
800274c: d305 bcc.n 800275a <UART_SetConfig+0x35e>
(lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
800274e: 687b ldr r3, [r7, #4]
8002750: 685b ldr r3, [r3, #4]
8002752: 031b lsls r3, r3, #12
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
8002754: 68ba ldr r2, [r7, #8]
8002756: 429a cmp r2, r3
8002758: d902 bls.n 8002760 <UART_SetConfig+0x364>
{
ret = HAL_ERROR;
800275a: 2301 movs r3, #1
800275c: 76bb strb r3, [r7, #26]
800275e: e0ff b.n 8002960 <UART_SetConfig+0x564>
}
else
{
/* Check computed UsartDiv value is in allocated range
(it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8002760: 697b ldr r3, [r7, #20]
8002762: 4618 mov r0, r3
8002764: f04f 0100 mov.w r1, #0
8002768: 687b ldr r3, [r7, #4]
800276a: 6a5b ldr r3, [r3, #36] ; 0x24
800276c: 4a86 ldr r2, [pc, #536] ; (8002988 <UART_SetConfig+0x58c>)
800276e: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
8002772: b29a uxth r2, r3
8002774: f04f 0300 mov.w r3, #0
8002778: f7fd fd4e bl 8000218 <__aeabi_uldivmod>
800277c: 4602 mov r2, r0
800277e: 460b mov r3, r1
8002780: 4610 mov r0, r2
8002782: 4619 mov r1, r3
8002784: f04f 0200 mov.w r2, #0
8002788: f04f 0300 mov.w r3, #0
800278c: 020b lsls r3, r1, #8
800278e: ea43 6310 orr.w r3, r3, r0, lsr #24
8002792: 0202 lsls r2, r0, #8
8002794: 6879 ldr r1, [r7, #4]
8002796: 6849 ldr r1, [r1, #4]
8002798: 0849 lsrs r1, r1, #1
800279a: 4608 mov r0, r1
800279c: f04f 0100 mov.w r1, #0
80027a0: 1814 adds r4, r2, r0
80027a2: eb43 0501 adc.w r5, r3, r1
80027a6: 687b ldr r3, [r7, #4]
80027a8: 685b ldr r3, [r3, #4]
80027aa: 461a mov r2, r3
80027ac: f04f 0300 mov.w r3, #0
80027b0: 4620 mov r0, r4
80027b2: 4629 mov r1, r5
80027b4: f7fd fd30 bl 8000218 <__aeabi_uldivmod>
80027b8: 4602 mov r2, r0
80027ba: 460b mov r3, r1
80027bc: 4613 mov r3, r2
80027be: 613b str r3, [r7, #16]
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
80027c0: 693b ldr r3, [r7, #16]
80027c2: f5b3 7f40 cmp.w r3, #768 ; 0x300
80027c6: d308 bcc.n 80027da <UART_SetConfig+0x3de>
80027c8: 693b ldr r3, [r7, #16]
80027ca: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
80027ce: d204 bcs.n 80027da <UART_SetConfig+0x3de>
{
huart->Instance->BRR = usartdiv;
80027d0: 687b ldr r3, [r7, #4]
80027d2: 681b ldr r3, [r3, #0]
80027d4: 693a ldr r2, [r7, #16]
80027d6: 60da str r2, [r3, #12]
80027d8: e0c2 b.n 8002960 <UART_SetConfig+0x564>
}
else
{
ret = HAL_ERROR;
80027da: 2301 movs r3, #1
80027dc: 76bb strb r3, [r7, #26]
80027de: e0bf b.n 8002960 <UART_SetConfig+0x564>
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
} /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
80027e0: 687b ldr r3, [r7, #4]
80027e2: 69db ldr r3, [r3, #28]
80027e4: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
80027e8: d165 bne.n 80028b6 <UART_SetConfig+0x4ba>
{
switch (clocksource)
80027ea: 7efb ldrb r3, [r7, #27]
80027ec: 2b08 cmp r3, #8
80027ee: d828 bhi.n 8002842 <UART_SetConfig+0x446>
80027f0: a201 add r2, pc, #4 ; (adr r2, 80027f8 <UART_SetConfig+0x3fc>)
80027f2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80027f6: bf00 nop
80027f8: 0800281d .word 0x0800281d
80027fc: 08002825 .word 0x08002825
8002800: 0800282d .word 0x0800282d
8002804: 08002843 .word 0x08002843
8002808: 08002833 .word 0x08002833
800280c: 08002843 .word 0x08002843
8002810: 08002843 .word 0x08002843
8002814: 08002843 .word 0x08002843
8002818: 0800283b .word 0x0800283b
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
800281c: f7ff fae0 bl 8001de0 <HAL_RCC_GetPCLK1Freq>
8002820: 6178 str r0, [r7, #20]
break;
8002822: e013 b.n 800284c <UART_SetConfig+0x450>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8002824: f7ff faf2 bl 8001e0c <HAL_RCC_GetPCLK2Freq>
8002828: 6178 str r0, [r7, #20]
break;
800282a: e00f b.n 800284c <UART_SetConfig+0x450>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
800282c: 4b57 ldr r3, [pc, #348] ; (800298c <UART_SetConfig+0x590>)
800282e: 617b str r3, [r7, #20]
break;
8002830: e00c b.n 800284c <UART_SetConfig+0x450>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8002832: f7ff fa67 bl 8001d04 <HAL_RCC_GetSysClockFreq>
8002836: 6178 str r0, [r7, #20]
break;
8002838: e008 b.n 800284c <UART_SetConfig+0x450>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
800283a: f44f 4300 mov.w r3, #32768 ; 0x8000
800283e: 617b str r3, [r7, #20]
break;
8002840: e004 b.n 800284c <UART_SetConfig+0x450>
default:
pclk = 0U;
8002842: 2300 movs r3, #0
8002844: 617b str r3, [r7, #20]
ret = HAL_ERROR;
8002846: 2301 movs r3, #1
8002848: 76bb strb r3, [r7, #26]
break;
800284a: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
800284c: 697b ldr r3, [r7, #20]
800284e: 2b00 cmp r3, #0
8002850: f000 8086 beq.w 8002960 <UART_SetConfig+0x564>
{
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8002854: 687b ldr r3, [r7, #4]
8002856: 6a5b ldr r3, [r3, #36] ; 0x24
8002858: 4a4b ldr r2, [pc, #300] ; (8002988 <UART_SetConfig+0x58c>)
800285a: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
800285e: 461a mov r2, r3
8002860: 697b ldr r3, [r7, #20]
8002862: fbb3 f3f2 udiv r3, r3, r2
8002866: 005a lsls r2, r3, #1
8002868: 687b ldr r3, [r7, #4]
800286a: 685b ldr r3, [r3, #4]
800286c: 085b lsrs r3, r3, #1
800286e: 441a add r2, r3
8002870: 687b ldr r3, [r7, #4]
8002872: 685b ldr r3, [r3, #4]
8002874: fbb2 f3f3 udiv r3, r2, r3
8002878: b29b uxth r3, r3
800287a: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
800287c: 693b ldr r3, [r7, #16]
800287e: 2b0f cmp r3, #15
8002880: d916 bls.n 80028b0 <UART_SetConfig+0x4b4>
8002882: 693b ldr r3, [r7, #16]
8002884: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8002888: d212 bcs.n 80028b0 <UART_SetConfig+0x4b4>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
800288a: 693b ldr r3, [r7, #16]
800288c: b29b uxth r3, r3
800288e: f023 030f bic.w r3, r3, #15
8002892: 81fb strh r3, [r7, #14]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8002894: 693b ldr r3, [r7, #16]
8002896: 085b lsrs r3, r3, #1
8002898: b29b uxth r3, r3
800289a: f003 0307 and.w r3, r3, #7
800289e: b29a uxth r2, r3
80028a0: 89fb ldrh r3, [r7, #14]
80028a2: 4313 orrs r3, r2
80028a4: 81fb strh r3, [r7, #14]
huart->Instance->BRR = brrtemp;
80028a6: 687b ldr r3, [r7, #4]
80028a8: 681b ldr r3, [r3, #0]
80028aa: 89fa ldrh r2, [r7, #14]
80028ac: 60da str r2, [r3, #12]
80028ae: e057 b.n 8002960 <UART_SetConfig+0x564>
}
else
{
ret = HAL_ERROR;
80028b0: 2301 movs r3, #1
80028b2: 76bb strb r3, [r7, #26]
80028b4: e054 b.n 8002960 <UART_SetConfig+0x564>
}
}
}
else
{
switch (clocksource)
80028b6: 7efb ldrb r3, [r7, #27]
80028b8: 2b08 cmp r3, #8
80028ba: d828 bhi.n 800290e <UART_SetConfig+0x512>
80028bc: a201 add r2, pc, #4 ; (adr r2, 80028c4 <UART_SetConfig+0x4c8>)
80028be: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80028c2: bf00 nop
80028c4: 080028e9 .word 0x080028e9
80028c8: 080028f1 .word 0x080028f1
80028cc: 080028f9 .word 0x080028f9
80028d0: 0800290f .word 0x0800290f
80028d4: 080028ff .word 0x080028ff
80028d8: 0800290f .word 0x0800290f
80028dc: 0800290f .word 0x0800290f
80028e0: 0800290f .word 0x0800290f
80028e4: 08002907 .word 0x08002907
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
80028e8: f7ff fa7a bl 8001de0 <HAL_RCC_GetPCLK1Freq>
80028ec: 6178 str r0, [r7, #20]
break;
80028ee: e013 b.n 8002918 <UART_SetConfig+0x51c>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
80028f0: f7ff fa8c bl 8001e0c <HAL_RCC_GetPCLK2Freq>
80028f4: 6178 str r0, [r7, #20]
break;
80028f6: e00f b.n 8002918 <UART_SetConfig+0x51c>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
80028f8: 4b24 ldr r3, [pc, #144] ; (800298c <UART_SetConfig+0x590>)
80028fa: 617b str r3, [r7, #20]
break;
80028fc: e00c b.n 8002918 <UART_SetConfig+0x51c>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80028fe: f7ff fa01 bl 8001d04 <HAL_RCC_GetSysClockFreq>
8002902: 6178 str r0, [r7, #20]
break;
8002904: e008 b.n 8002918 <UART_SetConfig+0x51c>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8002906: f44f 4300 mov.w r3, #32768 ; 0x8000
800290a: 617b str r3, [r7, #20]
break;
800290c: e004 b.n 8002918 <UART_SetConfig+0x51c>
default:
pclk = 0U;
800290e: 2300 movs r3, #0
8002910: 617b str r3, [r7, #20]
ret = HAL_ERROR;
8002912: 2301 movs r3, #1
8002914: 76bb strb r3, [r7, #26]
break;
8002916: bf00 nop
}
if (pclk != 0U)
8002918: 697b ldr r3, [r7, #20]
800291a: 2b00 cmp r3, #0
800291c: d020 beq.n 8002960 <UART_SetConfig+0x564>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
800291e: 687b ldr r3, [r7, #4]
8002920: 6a5b ldr r3, [r3, #36] ; 0x24
8002922: 4a19 ldr r2, [pc, #100] ; (8002988 <UART_SetConfig+0x58c>)
8002924: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
8002928: 461a mov r2, r3
800292a: 697b ldr r3, [r7, #20]
800292c: fbb3 f2f2 udiv r2, r3, r2
8002930: 687b ldr r3, [r7, #4]
8002932: 685b ldr r3, [r3, #4]
8002934: 085b lsrs r3, r3, #1
8002936: 441a add r2, r3
8002938: 687b ldr r3, [r7, #4]
800293a: 685b ldr r3, [r3, #4]
800293c: fbb2 f3f3 udiv r3, r2, r3
8002940: b29b uxth r3, r3
8002942: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8002944: 693b ldr r3, [r7, #16]
8002946: 2b0f cmp r3, #15
8002948: d908 bls.n 800295c <UART_SetConfig+0x560>
800294a: 693b ldr r3, [r7, #16]
800294c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8002950: d204 bcs.n 800295c <UART_SetConfig+0x560>
{
huart->Instance->BRR = usartdiv;
8002952: 687b ldr r3, [r7, #4]
8002954: 681b ldr r3, [r3, #0]
8002956: 693a ldr r2, [r7, #16]
8002958: 60da str r2, [r3, #12]
800295a: e001 b.n 8002960 <UART_SetConfig+0x564>
}
else
{
ret = HAL_ERROR;
800295c: 2301 movs r3, #1
800295e: 76bb strb r3, [r7, #26]
}
}
}
/* Initialize the number of data to process during RX/TX ISR execution */
huart->NbTxDataToProcess = 1;
8002960: 687b ldr r3, [r7, #4]
8002962: 2201 movs r2, #1
8002964: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
huart->NbRxDataToProcess = 1;
8002968: 687b ldr r3, [r7, #4]
800296a: 2201 movs r2, #1
800296c: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
/* Clear ISR function pointers */
huart->RxISR = NULL;
8002970: 687b ldr r3, [r7, #4]
8002972: 2200 movs r2, #0
8002974: 671a str r2, [r3, #112] ; 0x70
huart->TxISR = NULL;
8002976: 687b ldr r3, [r7, #4]
8002978: 2200 movs r2, #0
800297a: 675a str r2, [r3, #116] ; 0x74
return ret;
800297c: 7ebb ldrb r3, [r7, #26]
}
800297e: 4618 mov r0, r3
8002980: 3720 adds r7, #32
8002982: 46bd mov sp, r7
8002984: bdb0 pop {r4, r5, r7, pc}
8002986: bf00 nop
8002988: 08002ef8 .word 0x08002ef8
800298c: 00f42400 .word 0x00f42400
08002990 <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
8002990: b480 push {r7}
8002992: b083 sub sp, #12
8002994: af00 add r7, sp, #0
8002996: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
8002998: 687b ldr r3, [r7, #4]
800299a: 6a9b ldr r3, [r3, #40] ; 0x28
800299c: f003 0301 and.w r3, r3, #1
80029a0: 2b00 cmp r3, #0
80029a2: d00a beq.n 80029ba <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
80029a4: 687b ldr r3, [r7, #4]
80029a6: 681b ldr r3, [r3, #0]
80029a8: 685b ldr r3, [r3, #4]
80029aa: f423 3100 bic.w r1, r3, #131072 ; 0x20000
80029ae: 687b ldr r3, [r7, #4]
80029b0: 6ada ldr r2, [r3, #44] ; 0x2c
80029b2: 687b ldr r3, [r7, #4]
80029b4: 681b ldr r3, [r3, #0]
80029b6: 430a orrs r2, r1
80029b8: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
80029ba: 687b ldr r3, [r7, #4]
80029bc: 6a9b ldr r3, [r3, #40] ; 0x28
80029be: f003 0302 and.w r3, r3, #2
80029c2: 2b00 cmp r3, #0
80029c4: d00a beq.n 80029dc <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
80029c6: 687b ldr r3, [r7, #4]
80029c8: 681b ldr r3, [r3, #0]
80029ca: 685b ldr r3, [r3, #4]
80029cc: f423 3180 bic.w r1, r3, #65536 ; 0x10000
80029d0: 687b ldr r3, [r7, #4]
80029d2: 6b1a ldr r2, [r3, #48] ; 0x30
80029d4: 687b ldr r3, [r7, #4]
80029d6: 681b ldr r3, [r3, #0]
80029d8: 430a orrs r2, r1
80029da: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
80029dc: 687b ldr r3, [r7, #4]
80029de: 6a9b ldr r3, [r3, #40] ; 0x28
80029e0: f003 0304 and.w r3, r3, #4
80029e4: 2b00 cmp r3, #0
80029e6: d00a beq.n 80029fe <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
80029e8: 687b ldr r3, [r7, #4]
80029ea: 681b ldr r3, [r3, #0]
80029ec: 685b ldr r3, [r3, #4]
80029ee: f423 2180 bic.w r1, r3, #262144 ; 0x40000
80029f2: 687b ldr r3, [r7, #4]
80029f4: 6b5a ldr r2, [r3, #52] ; 0x34
80029f6: 687b ldr r3, [r7, #4]
80029f8: 681b ldr r3, [r3, #0]
80029fa: 430a orrs r2, r1
80029fc: 605a str r2, [r3, #4]
}
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
80029fe: 687b ldr r3, [r7, #4]
8002a00: 6a9b ldr r3, [r3, #40] ; 0x28
8002a02: f003 0308 and.w r3, r3, #8
8002a06: 2b00 cmp r3, #0
8002a08: d00a beq.n 8002a20 <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
8002a0a: 687b ldr r3, [r7, #4]
8002a0c: 681b ldr r3, [r3, #0]
8002a0e: 685b ldr r3, [r3, #4]
8002a10: f423 4100 bic.w r1, r3, #32768 ; 0x8000
8002a14: 687b ldr r3, [r7, #4]
8002a16: 6b9a ldr r2, [r3, #56] ; 0x38
8002a18: 687b ldr r3, [r7, #4]
8002a1a: 681b ldr r3, [r3, #0]
8002a1c: 430a orrs r2, r1
8002a1e: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
8002a20: 687b ldr r3, [r7, #4]
8002a22: 6a9b ldr r3, [r3, #40] ; 0x28
8002a24: f003 0310 and.w r3, r3, #16
8002a28: 2b00 cmp r3, #0
8002a2a: d00a beq.n 8002a42 <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
8002a2c: 687b ldr r3, [r7, #4]
8002a2e: 681b ldr r3, [r3, #0]
8002a30: 689b ldr r3, [r3, #8]
8002a32: f423 5180 bic.w r1, r3, #4096 ; 0x1000
8002a36: 687b ldr r3, [r7, #4]
8002a38: 6bda ldr r2, [r3, #60] ; 0x3c
8002a3a: 687b ldr r3, [r7, #4]
8002a3c: 681b ldr r3, [r3, #0]
8002a3e: 430a orrs r2, r1
8002a40: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
8002a42: 687b ldr r3, [r7, #4]
8002a44: 6a9b ldr r3, [r3, #40] ; 0x28
8002a46: f003 0320 and.w r3, r3, #32
8002a4a: 2b00 cmp r3, #0
8002a4c: d00a beq.n 8002a64 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
8002a4e: 687b ldr r3, [r7, #4]
8002a50: 681b ldr r3, [r3, #0]
8002a52: 689b ldr r3, [r3, #8]
8002a54: f423 5100 bic.w r1, r3, #8192 ; 0x2000
8002a58: 687b ldr r3, [r7, #4]
8002a5a: 6c1a ldr r2, [r3, #64] ; 0x40
8002a5c: 687b ldr r3, [r7, #4]
8002a5e: 681b ldr r3, [r3, #0]
8002a60: 430a orrs r2, r1
8002a62: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
8002a64: 687b ldr r3, [r7, #4]
8002a66: 6a9b ldr r3, [r3, #40] ; 0x28
8002a68: f003 0340 and.w r3, r3, #64 ; 0x40
8002a6c: 2b00 cmp r3, #0
8002a6e: d01a beq.n 8002aa6 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
8002a70: 687b ldr r3, [r7, #4]
8002a72: 681b ldr r3, [r3, #0]
8002a74: 685b ldr r3, [r3, #4]
8002a76: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
8002a7a: 687b ldr r3, [r7, #4]
8002a7c: 6c5a ldr r2, [r3, #68] ; 0x44
8002a7e: 687b ldr r3, [r7, #4]
8002a80: 681b ldr r3, [r3, #0]
8002a82: 430a orrs r2, r1
8002a84: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
8002a86: 687b ldr r3, [r7, #4]
8002a88: 6c5b ldr r3, [r3, #68] ; 0x44
8002a8a: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
8002a8e: d10a bne.n 8002aa6 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
8002a90: 687b ldr r3, [r7, #4]
8002a92: 681b ldr r3, [r3, #0]
8002a94: 685b ldr r3, [r3, #4]
8002a96: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
8002a9a: 687b ldr r3, [r7, #4]
8002a9c: 6c9a ldr r2, [r3, #72] ; 0x48
8002a9e: 687b ldr r3, [r7, #4]
8002aa0: 681b ldr r3, [r3, #0]
8002aa2: 430a orrs r2, r1
8002aa4: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
8002aa6: 687b ldr r3, [r7, #4]
8002aa8: 6a9b ldr r3, [r3, #40] ; 0x28
8002aaa: f003 0380 and.w r3, r3, #128 ; 0x80
8002aae: 2b00 cmp r3, #0
8002ab0: d00a beq.n 8002ac8 <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
8002ab2: 687b ldr r3, [r7, #4]
8002ab4: 681b ldr r3, [r3, #0]
8002ab6: 685b ldr r3, [r3, #4]
8002ab8: f423 2100 bic.w r1, r3, #524288 ; 0x80000
8002abc: 687b ldr r3, [r7, #4]
8002abe: 6cda ldr r2, [r3, #76] ; 0x4c
8002ac0: 687b ldr r3, [r7, #4]
8002ac2: 681b ldr r3, [r3, #0]
8002ac4: 430a orrs r2, r1
8002ac6: 605a str r2, [r3, #4]
}
}
8002ac8: bf00 nop
8002aca: 370c adds r7, #12
8002acc: 46bd mov sp, r7
8002ace: f85d 7b04 ldr.w r7, [sp], #4
8002ad2: 4770 bx lr
08002ad4 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
8002ad4: b580 push {r7, lr}
8002ad6: b086 sub sp, #24
8002ad8: af02 add r7, sp, #8
8002ada: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8002adc: 687b ldr r3, [r7, #4]
8002ade: 2200 movs r2, #0
8002ae0: f8c3 208c str.w r2, [r3, #140] ; 0x8c
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8002ae4: f7fe f806 bl 8000af4 <HAL_GetTick>
8002ae8: 60f8 str r0, [r7, #12]
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
8002aea: 687b ldr r3, [r7, #4]
8002aec: 681b ldr r3, [r3, #0]
8002aee: 681b ldr r3, [r3, #0]
8002af0: f003 0308 and.w r3, r3, #8
8002af4: 2b08 cmp r3, #8
8002af6: d10e bne.n 8002b16 <UART_CheckIdleState+0x42>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8002af8: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
8002afc: 9300 str r3, [sp, #0]
8002afe: 68fb ldr r3, [r7, #12]
8002b00: 2200 movs r2, #0
8002b02: f44f 1100 mov.w r1, #2097152 ; 0x200000
8002b06: 6878 ldr r0, [r7, #4]
8002b08: f000 f82f bl 8002b6a <UART_WaitOnFlagUntilTimeout>
8002b0c: 4603 mov r3, r0
8002b0e: 2b00 cmp r3, #0
8002b10: d001 beq.n 8002b16 <UART_CheckIdleState+0x42>
{
/* Timeout occurred */
return HAL_TIMEOUT;
8002b12: 2303 movs r3, #3
8002b14: e025 b.n 8002b62 <UART_CheckIdleState+0x8e>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
8002b16: 687b ldr r3, [r7, #4]
8002b18: 681b ldr r3, [r3, #0]
8002b1a: 681b ldr r3, [r3, #0]
8002b1c: f003 0304 and.w r3, r3, #4
8002b20: 2b04 cmp r3, #4
8002b22: d10e bne.n 8002b42 <UART_CheckIdleState+0x6e>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8002b24: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
8002b28: 9300 str r3, [sp, #0]
8002b2a: 68fb ldr r3, [r7, #12]
8002b2c: 2200 movs r2, #0
8002b2e: f44f 0180 mov.w r1, #4194304 ; 0x400000
8002b32: 6878 ldr r0, [r7, #4]
8002b34: f000 f819 bl 8002b6a <UART_WaitOnFlagUntilTimeout>
8002b38: 4603 mov r3, r0
8002b3a: 2b00 cmp r3, #0
8002b3c: d001 beq.n 8002b42 <UART_CheckIdleState+0x6e>
{
/* Timeout occurred */
return HAL_TIMEOUT;
8002b3e: 2303 movs r3, #3
8002b40: e00f b.n 8002b62 <UART_CheckIdleState+0x8e>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
8002b42: 687b ldr r3, [r7, #4]
8002b44: 2220 movs r2, #32
8002b46: f8c3 2084 str.w r2, [r3, #132] ; 0x84
huart->RxState = HAL_UART_STATE_READY;
8002b4a: 687b ldr r3, [r7, #4]
8002b4c: 2220 movs r2, #32
8002b4e: f8c3 2088 str.w r2, [r3, #136] ; 0x88
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8002b52: 687b ldr r3, [r7, #4]
8002b54: 2200 movs r2, #0
8002b56: 66da str r2, [r3, #108] ; 0x6c
__HAL_UNLOCK(huart);
8002b58: 687b ldr r3, [r7, #4]
8002b5a: 2200 movs r2, #0
8002b5c: f883 2080 strb.w r2, [r3, #128] ; 0x80
return HAL_OK;
8002b60: 2300 movs r3, #0
}
8002b62: 4618 mov r0, r3
8002b64: 3710 adds r7, #16
8002b66: 46bd mov sp, r7
8002b68: bd80 pop {r7, pc}
08002b6a <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8002b6a: b580 push {r7, lr}
8002b6c: b084 sub sp, #16
8002b6e: af00 add r7, sp, #0
8002b70: 60f8 str r0, [r7, #12]
8002b72: 60b9 str r1, [r7, #8]
8002b74: 603b str r3, [r7, #0]
8002b76: 4613 mov r3, r2
8002b78: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8002b7a: e062 b.n 8002c42 <UART_WaitOnFlagUntilTimeout+0xd8>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8002b7c: 69bb ldr r3, [r7, #24]
8002b7e: f1b3 3fff cmp.w r3, #4294967295
8002b82: d05e beq.n 8002c42 <UART_WaitOnFlagUntilTimeout+0xd8>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8002b84: f7fd ffb6 bl 8000af4 <HAL_GetTick>
8002b88: 4602 mov r2, r0
8002b8a: 683b ldr r3, [r7, #0]
8002b8c: 1ad3 subs r3, r2, r3
8002b8e: 69ba ldr r2, [r7, #24]
8002b90: 429a cmp r2, r3
8002b92: d302 bcc.n 8002b9a <UART_WaitOnFlagUntilTimeout+0x30>
8002b94: 69bb ldr r3, [r7, #24]
8002b96: 2b00 cmp r3, #0
8002b98: d11d bne.n 8002bd6 <UART_WaitOnFlagUntilTimeout+0x6c>
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
8002b9a: 68fb ldr r3, [r7, #12]
8002b9c: 681b ldr r3, [r3, #0]
8002b9e: 681a ldr r2, [r3, #0]
8002ba0: 68fb ldr r3, [r7, #12]
8002ba2: 681b ldr r3, [r3, #0]
8002ba4: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
8002ba8: 601a str r2, [r3, #0]
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8002baa: 68fb ldr r3, [r7, #12]
8002bac: 681b ldr r3, [r3, #0]
8002bae: 689a ldr r2, [r3, #8]
8002bb0: 68fb ldr r3, [r7, #12]
8002bb2: 681b ldr r3, [r3, #0]
8002bb4: f022 0201 bic.w r2, r2, #1
8002bb8: 609a str r2, [r3, #8]
huart->gState = HAL_UART_STATE_READY;
8002bba: 68fb ldr r3, [r7, #12]
8002bbc: 2220 movs r2, #32
8002bbe: f8c3 2084 str.w r2, [r3, #132] ; 0x84
huart->RxState = HAL_UART_STATE_READY;
8002bc2: 68fb ldr r3, [r7, #12]
8002bc4: 2220 movs r2, #32
8002bc6: f8c3 2088 str.w r2, [r3, #136] ; 0x88
__HAL_UNLOCK(huart);
8002bca: 68fb ldr r3, [r7, #12]
8002bcc: 2200 movs r2, #0
8002bce: f883 2080 strb.w r2, [r3, #128] ; 0x80
return HAL_TIMEOUT;
8002bd2: 2303 movs r3, #3
8002bd4: e045 b.n 8002c62 <UART_WaitOnFlagUntilTimeout+0xf8>
}
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
8002bd6: 68fb ldr r3, [r7, #12]
8002bd8: 681b ldr r3, [r3, #0]
8002bda: 681b ldr r3, [r3, #0]
8002bdc: f003 0304 and.w r3, r3, #4
8002be0: 2b00 cmp r3, #0
8002be2: d02e beq.n 8002c42 <UART_WaitOnFlagUntilTimeout+0xd8>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
8002be4: 68fb ldr r3, [r7, #12]
8002be6: 681b ldr r3, [r3, #0]
8002be8: 69db ldr r3, [r3, #28]
8002bea: f403 6300 and.w r3, r3, #2048 ; 0x800
8002bee: f5b3 6f00 cmp.w r3, #2048 ; 0x800
8002bf2: d126 bne.n 8002c42 <UART_WaitOnFlagUntilTimeout+0xd8>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8002bf4: 68fb ldr r3, [r7, #12]
8002bf6: 681b ldr r3, [r3, #0]
8002bf8: f44f 6200 mov.w r2, #2048 ; 0x800
8002bfc: 621a str r2, [r3, #32]
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
8002bfe: 68fb ldr r3, [r7, #12]
8002c00: 681b ldr r3, [r3, #0]
8002c02: 681a ldr r2, [r3, #0]
8002c04: 68fb ldr r3, [r7, #12]
8002c06: 681b ldr r3, [r3, #0]
8002c08: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
8002c0c: 601a str r2, [r3, #0]
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8002c0e: 68fb ldr r3, [r7, #12]
8002c10: 681b ldr r3, [r3, #0]
8002c12: 689a ldr r2, [r3, #8]
8002c14: 68fb ldr r3, [r7, #12]
8002c16: 681b ldr r3, [r3, #0]
8002c18: f022 0201 bic.w r2, r2, #1
8002c1c: 609a str r2, [r3, #8]
huart->gState = HAL_UART_STATE_READY;
8002c1e: 68fb ldr r3, [r7, #12]
8002c20: 2220 movs r2, #32
8002c22: f8c3 2084 str.w r2, [r3, #132] ; 0x84
huart->RxState = HAL_UART_STATE_READY;
8002c26: 68fb ldr r3, [r7, #12]
8002c28: 2220 movs r2, #32
8002c2a: f8c3 2088 str.w r2, [r3, #136] ; 0x88
huart->ErrorCode = HAL_UART_ERROR_RTO;
8002c2e: 68fb ldr r3, [r7, #12]
8002c30: 2220 movs r2, #32
8002c32: f8c3 208c str.w r2, [r3, #140] ; 0x8c
/* Process Unlocked */
__HAL_UNLOCK(huart);
8002c36: 68fb ldr r3, [r7, #12]
8002c38: 2200 movs r2, #0
8002c3a: f883 2080 strb.w r2, [r3, #128] ; 0x80
return HAL_TIMEOUT;
8002c3e: 2303 movs r3, #3
8002c40: e00f b.n 8002c62 <UART_WaitOnFlagUntilTimeout+0xf8>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8002c42: 68fb ldr r3, [r7, #12]
8002c44: 681b ldr r3, [r3, #0]
8002c46: 69da ldr r2, [r3, #28]
8002c48: 68bb ldr r3, [r7, #8]
8002c4a: 4013 ands r3, r2
8002c4c: 68ba ldr r2, [r7, #8]
8002c4e: 429a cmp r2, r3
8002c50: bf0c ite eq
8002c52: 2301 moveq r3, #1
8002c54: 2300 movne r3, #0
8002c56: b2db uxtb r3, r3
8002c58: 461a mov r2, r3
8002c5a: 79fb ldrb r3, [r7, #7]
8002c5c: 429a cmp r2, r3
8002c5e: d08d beq.n 8002b7c <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8002c60: 2300 movs r3, #0
}
8002c62: 4618 mov r0, r3
8002c64: 3710 adds r7, #16
8002c66: 46bd mov sp, r7
8002c68: bd80 pop {r7, pc}
08002c6a <HAL_UARTEx_DisableFifoMode>:
* @brief Disable the FIFO mode.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
{
8002c6a: b480 push {r7}
8002c6c: b085 sub sp, #20
8002c6e: af00 add r7, sp, #0
8002c70: 6078 str r0, [r7, #4]
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
/* Process Locked */
__HAL_LOCK(huart);
8002c72: 687b ldr r3, [r7, #4]
8002c74: f893 3080 ldrb.w r3, [r3, #128] ; 0x80
8002c78: 2b01 cmp r3, #1
8002c7a: d101 bne.n 8002c80 <HAL_UARTEx_DisableFifoMode+0x16>
8002c7c: 2302 movs r3, #2
8002c7e: e027 b.n 8002cd0 <HAL_UARTEx_DisableFifoMode+0x66>
8002c80: 687b ldr r3, [r7, #4]
8002c82: 2201 movs r2, #1
8002c84: f883 2080 strb.w r2, [r3, #128] ; 0x80
huart->gState = HAL_UART_STATE_BUSY;
8002c88: 687b ldr r3, [r7, #4]
8002c8a: 2224 movs r2, #36 ; 0x24
8002c8c: f8c3 2084 str.w r2, [r3, #132] ; 0x84
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
8002c90: 687b ldr r3, [r7, #4]
8002c92: 681b ldr r3, [r3, #0]
8002c94: 681b ldr r3, [r3, #0]
8002c96: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
8002c98: 687b ldr r3, [r7, #4]
8002c9a: 681b ldr r3, [r3, #0]
8002c9c: 681a ldr r2, [r3, #0]
8002c9e: 687b ldr r3, [r7, #4]
8002ca0: 681b ldr r3, [r3, #0]
8002ca2: f022 0201 bic.w r2, r2, #1
8002ca6: 601a str r2, [r3, #0]
/* Enable FIFO mode */
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
8002ca8: 68fb ldr r3, [r7, #12]
8002caa: f023 5300 bic.w r3, r3, #536870912 ; 0x20000000
8002cae: 60fb str r3, [r7, #12]
huart->FifoMode = UART_FIFOMODE_DISABLE;
8002cb0: 687b ldr r3, [r7, #4]
8002cb2: 2200 movs r2, #0
8002cb4: 665a str r2, [r3, #100] ; 0x64
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
8002cb6: 687b ldr r3, [r7, #4]
8002cb8: 681b ldr r3, [r3, #0]
8002cba: 68fa ldr r2, [r7, #12]
8002cbc: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
8002cbe: 687b ldr r3, [r7, #4]
8002cc0: 2220 movs r2, #32
8002cc2: f8c3 2084 str.w r2, [r3, #132] ; 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
8002cc6: 687b ldr r3, [r7, #4]
8002cc8: 2200 movs r2, #0
8002cca: f883 2080 strb.w r2, [r3, #128] ; 0x80
return HAL_OK;
8002cce: 2300 movs r3, #0
}
8002cd0: 4618 mov r0, r3
8002cd2: 3714 adds r7, #20
8002cd4: 46bd mov sp, r7
8002cd6: f85d 7b04 ldr.w r7, [sp], #4
8002cda: 4770 bx lr
08002cdc <HAL_UARTEx_SetTxFifoThreshold>:
* @arg @ref UART_TXFIFO_THRESHOLD_7_8
* @arg @ref UART_TXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
8002cdc: b580 push {r7, lr}
8002cde: b084 sub sp, #16
8002ce0: af00 add r7, sp, #0
8002ce2: 6078 str r0, [r7, #4]
8002ce4: 6039 str r1, [r7, #0]
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(huart);
8002ce6: 687b ldr r3, [r7, #4]
8002ce8: f893 3080 ldrb.w r3, [r3, #128] ; 0x80
8002cec: 2b01 cmp r3, #1
8002cee: d101 bne.n 8002cf4 <HAL_UARTEx_SetTxFifoThreshold+0x18>
8002cf0: 2302 movs r3, #2
8002cf2: e02d b.n 8002d50 <HAL_UARTEx_SetTxFifoThreshold+0x74>
8002cf4: 687b ldr r3, [r7, #4]
8002cf6: 2201 movs r2, #1
8002cf8: f883 2080 strb.w r2, [r3, #128] ; 0x80
huart->gState = HAL_UART_STATE_BUSY;
8002cfc: 687b ldr r3, [r7, #4]
8002cfe: 2224 movs r2, #36 ; 0x24
8002d00: f8c3 2084 str.w r2, [r3, #132] ; 0x84
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
8002d04: 687b ldr r3, [r7, #4]
8002d06: 681b ldr r3, [r3, #0]
8002d08: 681b ldr r3, [r3, #0]
8002d0a: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
8002d0c: 687b ldr r3, [r7, #4]
8002d0e: 681b ldr r3, [r3, #0]
8002d10: 681a ldr r2, [r3, #0]
8002d12: 687b ldr r3, [r7, #4]
8002d14: 681b ldr r3, [r3, #0]
8002d16: f022 0201 bic.w r2, r2, #1
8002d1a: 601a str r2, [r3, #0]
/* Update TX threshold configuration */
MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
8002d1c: 687b ldr r3, [r7, #4]
8002d1e: 681b ldr r3, [r3, #0]
8002d20: 689b ldr r3, [r3, #8]
8002d22: f023 4160 bic.w r1, r3, #3758096384 ; 0xe0000000
8002d26: 687b ldr r3, [r7, #4]
8002d28: 681b ldr r3, [r3, #0]
8002d2a: 683a ldr r2, [r7, #0]
8002d2c: 430a orrs r2, r1
8002d2e: 609a str r2, [r3, #8]
/* Determine the number of data to process during RX/TX ISR execution */
UARTEx_SetNbDataToProcess(huart);
8002d30: 6878 ldr r0, [r7, #4]
8002d32: f000 f84f bl 8002dd4 <UARTEx_SetNbDataToProcess>
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
8002d36: 687b ldr r3, [r7, #4]
8002d38: 681b ldr r3, [r3, #0]
8002d3a: 68fa ldr r2, [r7, #12]
8002d3c: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
8002d3e: 687b ldr r3, [r7, #4]
8002d40: 2220 movs r2, #32
8002d42: f8c3 2084 str.w r2, [r3, #132] ; 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
8002d46: 687b ldr r3, [r7, #4]
8002d48: 2200 movs r2, #0
8002d4a: f883 2080 strb.w r2, [r3, #128] ; 0x80
return HAL_OK;
8002d4e: 2300 movs r3, #0
}
8002d50: 4618 mov r0, r3
8002d52: 3710 adds r7, #16
8002d54: 46bd mov sp, r7
8002d56: bd80 pop {r7, pc}
08002d58 <HAL_UARTEx_SetRxFifoThreshold>:
* @arg @ref UART_RXFIFO_THRESHOLD_7_8
* @arg @ref UART_RXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
8002d58: b580 push {r7, lr}
8002d5a: b084 sub sp, #16
8002d5c: af00 add r7, sp, #0
8002d5e: 6078 str r0, [r7, #4]
8002d60: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(huart);
8002d62: 687b ldr r3, [r7, #4]
8002d64: f893 3080 ldrb.w r3, [r3, #128] ; 0x80
8002d68: 2b01 cmp r3, #1
8002d6a: d101 bne.n 8002d70 <HAL_UARTEx_SetRxFifoThreshold+0x18>
8002d6c: 2302 movs r3, #2
8002d6e: e02d b.n 8002dcc <HAL_UARTEx_SetRxFifoThreshold+0x74>
8002d70: 687b ldr r3, [r7, #4]
8002d72: 2201 movs r2, #1
8002d74: f883 2080 strb.w r2, [r3, #128] ; 0x80
huart->gState = HAL_UART_STATE_BUSY;
8002d78: 687b ldr r3, [r7, #4]
8002d7a: 2224 movs r2, #36 ; 0x24
8002d7c: f8c3 2084 str.w r2, [r3, #132] ; 0x84
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
8002d80: 687b ldr r3, [r7, #4]
8002d82: 681b ldr r3, [r3, #0]
8002d84: 681b ldr r3, [r3, #0]
8002d86: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
8002d88: 687b ldr r3, [r7, #4]
8002d8a: 681b ldr r3, [r3, #0]
8002d8c: 681a ldr r2, [r3, #0]
8002d8e: 687b ldr r3, [r7, #4]
8002d90: 681b ldr r3, [r3, #0]
8002d92: f022 0201 bic.w r2, r2, #1
8002d96: 601a str r2, [r3, #0]
/* Update RX threshold configuration */
MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
8002d98: 687b ldr r3, [r7, #4]
8002d9a: 681b ldr r3, [r3, #0]
8002d9c: 689b ldr r3, [r3, #8]
8002d9e: f023 6160 bic.w r1, r3, #234881024 ; 0xe000000
8002da2: 687b ldr r3, [r7, #4]
8002da4: 681b ldr r3, [r3, #0]
8002da6: 683a ldr r2, [r7, #0]
8002da8: 430a orrs r2, r1
8002daa: 609a str r2, [r3, #8]
/* Determine the number of data to process during RX/TX ISR execution */
UARTEx_SetNbDataToProcess(huart);
8002dac: 6878 ldr r0, [r7, #4]
8002dae: f000 f811 bl 8002dd4 <UARTEx_SetNbDataToProcess>
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
8002db2: 687b ldr r3, [r7, #4]
8002db4: 681b ldr r3, [r3, #0]
8002db6: 68fa ldr r2, [r7, #12]
8002db8: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
8002dba: 687b ldr r3, [r7, #4]
8002dbc: 2220 movs r2, #32
8002dbe: f8c3 2084 str.w r2, [r3, #132] ; 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
8002dc2: 687b ldr r3, [r7, #4]
8002dc4: 2200 movs r2, #0
8002dc6: f883 2080 strb.w r2, [r3, #128] ; 0x80
return HAL_OK;
8002dca: 2300 movs r3, #0
}
8002dcc: 4618 mov r0, r3
8002dce: 3710 adds r7, #16
8002dd0: 46bd mov sp, r7
8002dd2: bd80 pop {r7, pc}
08002dd4 <UARTEx_SetNbDataToProcess>:
* the UART configuration registers.
* @param huart UART handle.
* @retval None
*/
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
{
8002dd4: b480 push {r7}
8002dd6: b085 sub sp, #20
8002dd8: af00 add r7, sp, #0
8002dda: 6078 str r0, [r7, #4]
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
8002ddc: 687b ldr r3, [r7, #4]
8002dde: 6e5b ldr r3, [r3, #100] ; 0x64
8002de0: 2b00 cmp r3, #0
8002de2: d108 bne.n 8002df6 <UARTEx_SetNbDataToProcess+0x22>
{
huart->NbTxDataToProcess = 1U;
8002de4: 687b ldr r3, [r7, #4]
8002de6: 2201 movs r2, #1
8002de8: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
huart->NbRxDataToProcess = 1U;
8002dec: 687b ldr r3, [r7, #4]
8002dee: 2201 movs r2, #1
8002df0: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
(uint16_t)denominator[tx_fifo_threshold];
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
(uint16_t)denominator[rx_fifo_threshold];
}
}
8002df4: e031 b.n 8002e5a <UARTEx_SetNbDataToProcess+0x86>
rx_fifo_depth = RX_FIFO_DEPTH;
8002df6: 2308 movs r3, #8
8002df8: 73fb strb r3, [r7, #15]
tx_fifo_depth = TX_FIFO_DEPTH;
8002dfa: 2308 movs r3, #8
8002dfc: 73bb strb r3, [r7, #14]
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
8002dfe: 687b ldr r3, [r7, #4]
8002e00: 681b ldr r3, [r3, #0]
8002e02: 689b ldr r3, [r3, #8]
8002e04: 0e5b lsrs r3, r3, #25
8002e06: b2db uxtb r3, r3
8002e08: f003 0307 and.w r3, r3, #7
8002e0c: 737b strb r3, [r7, #13]
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
8002e0e: 687b ldr r3, [r7, #4]
8002e10: 681b ldr r3, [r3, #0]
8002e12: 689b ldr r3, [r3, #8]
8002e14: 0f5b lsrs r3, r3, #29
8002e16: b2db uxtb r3, r3
8002e18: f003 0307 and.w r3, r3, #7
8002e1c: 733b strb r3, [r7, #12]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8002e1e: 7bbb ldrb r3, [r7, #14]
8002e20: 7b3a ldrb r2, [r7, #12]
8002e22: 4911 ldr r1, [pc, #68] ; (8002e68 <UARTEx_SetNbDataToProcess+0x94>)
8002e24: 5c8a ldrb r2, [r1, r2]
8002e26: fb02 f303 mul.w r3, r2, r3
(uint16_t)denominator[tx_fifo_threshold];
8002e2a: 7b3a ldrb r2, [r7, #12]
8002e2c: 490f ldr r1, [pc, #60] ; (8002e6c <UARTEx_SetNbDataToProcess+0x98>)
8002e2e: 5c8a ldrb r2, [r1, r2]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8002e30: fb93 f3f2 sdiv r3, r3, r2
8002e34: b29a uxth r2, r3
8002e36: 687b ldr r3, [r7, #4]
8002e38: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
8002e3c: 7bfb ldrb r3, [r7, #15]
8002e3e: 7b7a ldrb r2, [r7, #13]
8002e40: 4909 ldr r1, [pc, #36] ; (8002e68 <UARTEx_SetNbDataToProcess+0x94>)
8002e42: 5c8a ldrb r2, [r1, r2]
8002e44: fb02 f303 mul.w r3, r2, r3
(uint16_t)denominator[rx_fifo_threshold];
8002e48: 7b7a ldrb r2, [r7, #13]
8002e4a: 4908 ldr r1, [pc, #32] ; (8002e6c <UARTEx_SetNbDataToProcess+0x98>)
8002e4c: 5c8a ldrb r2, [r1, r2]
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
8002e4e: fb93 f3f2 sdiv r3, r3, r2
8002e52: b29a uxth r2, r3
8002e54: 687b ldr r3, [r7, #4]
8002e56: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
}
8002e5a: bf00 nop
8002e5c: 3714 adds r7, #20
8002e5e: 46bd mov sp, r7
8002e60: f85d 7b04 ldr.w r7, [sp], #4
8002e64: 4770 bx lr
8002e66: bf00 nop
8002e68: 08002f10 .word 0x08002f10
8002e6c: 08002f18 .word 0x08002f18
08002e70 <__libc_init_array>:
8002e70: b570 push {r4, r5, r6, lr}
8002e72: 4d0d ldr r5, [pc, #52] ; (8002ea8 <__libc_init_array+0x38>)
8002e74: 4c0d ldr r4, [pc, #52] ; (8002eac <__libc_init_array+0x3c>)
8002e76: 1b64 subs r4, r4, r5
8002e78: 10a4 asrs r4, r4, #2
8002e7a: 2600 movs r6, #0
8002e7c: 42a6 cmp r6, r4
8002e7e: d109 bne.n 8002e94 <__libc_init_array+0x24>
8002e80: 4d0b ldr r5, [pc, #44] ; (8002eb0 <__libc_init_array+0x40>)
8002e82: 4c0c ldr r4, [pc, #48] ; (8002eb4 <__libc_init_array+0x44>)
8002e84: f000 f820 bl 8002ec8 <_init>
8002e88: 1b64 subs r4, r4, r5
8002e8a: 10a4 asrs r4, r4, #2
8002e8c: 2600 movs r6, #0
8002e8e: 42a6 cmp r6, r4
8002e90: d105 bne.n 8002e9e <__libc_init_array+0x2e>
8002e92: bd70 pop {r4, r5, r6, pc}
8002e94: f855 3b04 ldr.w r3, [r5], #4
8002e98: 4798 blx r3
8002e9a: 3601 adds r6, #1
8002e9c: e7ee b.n 8002e7c <__libc_init_array+0xc>
8002e9e: f855 3b04 ldr.w r3, [r5], #4
8002ea2: 4798 blx r3
8002ea4: 3601 adds r6, #1
8002ea6: e7f2 b.n 8002e8e <__libc_init_array+0x1e>
8002ea8: 08002f28 .word 0x08002f28
8002eac: 08002f28 .word 0x08002f28
8002eb0: 08002f28 .word 0x08002f28
8002eb4: 08002f2c .word 0x08002f2c
08002eb8 <memset>:
8002eb8: 4402 add r2, r0
8002eba: 4603 mov r3, r0
8002ebc: 4293 cmp r3, r2
8002ebe: d100 bne.n 8002ec2 <memset+0xa>
8002ec0: 4770 bx lr
8002ec2: f803 1b01 strb.w r1, [r3], #1
8002ec6: e7f9 b.n 8002ebc <memset+0x4>
08002ec8 <_init>:
8002ec8: b5f8 push {r3, r4, r5, r6, r7, lr}
8002eca: bf00 nop
8002ecc: bcf8 pop {r3, r4, r5, r6, r7}
8002ece: bc08 pop {r3}
8002ed0: 469e mov lr, r3
8002ed2: 4770 bx lr
08002ed4 <_fini>:
8002ed4: b5f8 push {r3, r4, r5, r6, r7, lr}
8002ed6: bf00 nop
8002ed8: bcf8 pop {r3, r4, r5, r6, r7}
8002eda: bc08 pop {r3}
8002edc: 469e mov lr, r3
8002ede: 4770 bx lr
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