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ARM GAS /tmp/ccjISuh0.s page 1
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1 .cpu cortex-m0
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2 .eabi_attribute 20, 1
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3 .eabi_attribute 21, 1
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4 .eabi_attribute 23, 3
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5 .eabi_attribute 24, 1
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6 .eabi_attribute 25, 1
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7 .eabi_attribute 26, 1
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8 .eabi_attribute 30, 1
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9 .eabi_attribute 34, 0
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10 .eabi_attribute 18, 4
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11 .file "system_stm32f0xx.c"
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12 .text
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13 .Ltext0:
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14 .cfi_sections .debug_frame
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15 .section .text.SystemInit,"ax",%progbits
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16 .align 1
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17 .global SystemInit
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18 .syntax unified
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19 .code 16
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20 .thumb_func
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21 .fpu softvfp
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23 SystemInit:
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24 .LFB40:
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25 .file 1 "Src/system_stm32f0xx.c"
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1:Src/system_stm32f0xx.c **** /**
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2:Src/system_stm32f0xx.c **** ******************************************************************************
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3:Src/system_stm32f0xx.c **** * @file system_stm32f0xx.c
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4:Src/system_stm32f0xx.c **** * @author MCD Application Team
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5:Src/system_stm32f0xx.c **** * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
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6:Src/system_stm32f0xx.c **** *
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7:Src/system_stm32f0xx.c **** * 1. This file provides two functions and one global variable to be called from
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8:Src/system_stm32f0xx.c **** * user application:
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9:Src/system_stm32f0xx.c **** * - SystemInit(): This function is called at startup just after reset and
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10:Src/system_stm32f0xx.c **** * before branch to main program. This call is made inside
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11:Src/system_stm32f0xx.c **** * the "startup_stm32f0xx.s" file.
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12:Src/system_stm32f0xx.c **** *
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13:Src/system_stm32f0xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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14:Src/system_stm32f0xx.c **** * by the user application to setup the SysTick
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15:Src/system_stm32f0xx.c **** * timer or configure other parameters.
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16:Src/system_stm32f0xx.c **** *
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17:Src/system_stm32f0xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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18:Src/system_stm32f0xx.c **** * be called whenever the core clock is changed
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19:Src/system_stm32f0xx.c **** * during program execution.
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20:Src/system_stm32f0xx.c **** *
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21:Src/system_stm32f0xx.c **** *
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22:Src/system_stm32f0xx.c **** ******************************************************************************
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23:Src/system_stm32f0xx.c **** * @attention
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24:Src/system_stm32f0xx.c **** *
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25:Src/system_stm32f0xx.c **** * <h2><center>© Copyright (c) 2016 STMicroelectronics.
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26:Src/system_stm32f0xx.c **** * All rights reserved.</center></h2>
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27:Src/system_stm32f0xx.c **** *
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28:Src/system_stm32f0xx.c **** * This software component is licensed by ST under BSD 3-Clause license,
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29:Src/system_stm32f0xx.c **** * the "License"; You may not use this file except in compliance with the
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30:Src/system_stm32f0xx.c **** * License. You may obtain a copy of the License at:
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31:Src/system_stm32f0xx.c **** * opensource.org/licenses/BSD-3-Clause
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32:Src/system_stm32f0xx.c **** *
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33:Src/system_stm32f0xx.c **** ******************************************************************************
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ARM GAS /tmp/ccjISuh0.s page 2
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34:Src/system_stm32f0xx.c **** */
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35:Src/system_stm32f0xx.c ****
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36:Src/system_stm32f0xx.c **** /** @addtogroup CMSIS
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37:Src/system_stm32f0xx.c **** * @{
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38:Src/system_stm32f0xx.c **** */
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39:Src/system_stm32f0xx.c ****
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40:Src/system_stm32f0xx.c **** /** @addtogroup stm32f0xx_system
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41:Src/system_stm32f0xx.c **** * @{
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42:Src/system_stm32f0xx.c **** */
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43:Src/system_stm32f0xx.c ****
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44:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_Includes
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45:Src/system_stm32f0xx.c **** * @{
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46:Src/system_stm32f0xx.c **** */
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47:Src/system_stm32f0xx.c ****
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48:Src/system_stm32f0xx.c **** #include "stm32f0xx.h"
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49:Src/system_stm32f0xx.c ****
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50:Src/system_stm32f0xx.c **** /**
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51:Src/system_stm32f0xx.c **** * @}
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52:Src/system_stm32f0xx.c **** */
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53:Src/system_stm32f0xx.c ****
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54:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
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55:Src/system_stm32f0xx.c **** * @{
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56:Src/system_stm32f0xx.c **** */
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57:Src/system_stm32f0xx.c ****
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58:Src/system_stm32f0xx.c **** /**
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59:Src/system_stm32f0xx.c **** * @}
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60:Src/system_stm32f0xx.c **** */
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61:Src/system_stm32f0xx.c ****
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62:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_Defines
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63:Src/system_stm32f0xx.c **** * @{
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64:Src/system_stm32f0xx.c **** */
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65:Src/system_stm32f0xx.c **** #if !defined (HSE_VALUE)
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66:Src/system_stm32f0xx.c **** #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
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67:Src/system_stm32f0xx.c **** This value can be provided and adapted by the user
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68:Src/system_stm32f0xx.c **** #endif /* HSE_VALUE */
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69:Src/system_stm32f0xx.c ****
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70:Src/system_stm32f0xx.c **** #if !defined (HSI_VALUE)
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71:Src/system_stm32f0xx.c **** #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
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72:Src/system_stm32f0xx.c **** This value can be provided and adapted by the user
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73:Src/system_stm32f0xx.c **** #endif /* HSI_VALUE */
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74:Src/system_stm32f0xx.c ****
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75:Src/system_stm32f0xx.c **** #if !defined (HSI48_VALUE)
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76:Src/system_stm32f0xx.c **** #define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in
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77:Src/system_stm32f0xx.c **** This value can be provided and adapted by the user
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78:Src/system_stm32f0xx.c **** #endif /* HSI48_VALUE */
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79:Src/system_stm32f0xx.c **** /**
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80:Src/system_stm32f0xx.c **** * @}
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81:Src/system_stm32f0xx.c **** */
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82:Src/system_stm32f0xx.c ****
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83:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_Macros
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84:Src/system_stm32f0xx.c **** * @{
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85:Src/system_stm32f0xx.c **** */
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86:Src/system_stm32f0xx.c ****
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87:Src/system_stm32f0xx.c **** /**
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88:Src/system_stm32f0xx.c **** * @}
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89:Src/system_stm32f0xx.c **** */
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90:Src/system_stm32f0xx.c ****
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ARM GAS /tmp/ccjISuh0.s page 3
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91:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_Variables
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92:Src/system_stm32f0xx.c **** * @{
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93:Src/system_stm32f0xx.c **** */
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94:Src/system_stm32f0xx.c **** /* This variable is updated in three ways:
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95:Src/system_stm32f0xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate()
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96:Src/system_stm32f0xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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97:Src/system_stm32f0xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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98:Src/system_stm32f0xx.c **** Note: If you use this function to configure the system clock; then there
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99:Src/system_stm32f0xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock
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100:Src/system_stm32f0xx.c **** variable is updated automatically.
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101:Src/system_stm32f0xx.c **** */
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102:Src/system_stm32f0xx.c **** uint32_t SystemCoreClock = 8000000;
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103:Src/system_stm32f0xx.c ****
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104:Src/system_stm32f0xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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105:Src/system_stm32f0xx.c **** const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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106:Src/system_stm32f0xx.c ****
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107:Src/system_stm32f0xx.c **** /**
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108:Src/system_stm32f0xx.c **** * @}
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109:Src/system_stm32f0xx.c **** */
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110:Src/system_stm32f0xx.c ****
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111:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
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112:Src/system_stm32f0xx.c **** * @{
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113:Src/system_stm32f0xx.c **** */
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114:Src/system_stm32f0xx.c ****
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115:Src/system_stm32f0xx.c **** /**
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116:Src/system_stm32f0xx.c **** * @}
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117:Src/system_stm32f0xx.c **** */
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118:Src/system_stm32f0xx.c ****
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119:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_Functions
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120:Src/system_stm32f0xx.c **** * @{
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121:Src/system_stm32f0xx.c **** */
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122:Src/system_stm32f0xx.c ****
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123:Src/system_stm32f0xx.c **** /**
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124:Src/system_stm32f0xx.c **** * @brief Setup the microcontroller system
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125:Src/system_stm32f0xx.c **** * @param None
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126:Src/system_stm32f0xx.c **** * @retval None
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127:Src/system_stm32f0xx.c **** */
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128:Src/system_stm32f0xx.c **** void SystemInit(void)
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129:Src/system_stm32f0xx.c **** {
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26 .loc 1 129 0
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27 .cfi_startproc
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28 @ args = 0, pretend = 0, frame = 0
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29 @ frame_needed = 0, uses_anonymous_args = 0
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30 @ link register save eliminated.
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130:Src/system_stm32f0xx.c **** /* NOTE :SystemInit(): This function is called at startup just after reset and
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131:Src/system_stm32f0xx.c **** before branch to main program. This call is made inside
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132:Src/system_stm32f0xx.c **** the "startup_stm32f0xx.s" file.
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133:Src/system_stm32f0xx.c **** User can setups the default system clock (System clock source, PLL Multipl
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134:Src/system_stm32f0xx.c **** and Divider factors, AHB/APBx prescalers and Flash settings).
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135:Src/system_stm32f0xx.c **** */
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136:Src/system_stm32f0xx.c **** }
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31 .loc 1 136 0
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32 @ sp needed
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33 0000 7047 bx lr
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34 .cfi_endproc
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35 .LFE40:
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37 .global __aeabi_uidiv
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ARM GAS /tmp/ccjISuh0.s page 4
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38 .section .text.SystemCoreClockUpdate,"ax",%progbits
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39 .align 1
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40 .global SystemCoreClockUpdate
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41 .syntax unified
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42 .code 16
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43 .thumb_func
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44 .fpu softvfp
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46 SystemCoreClockUpdate:
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47 .LFB41:
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137:Src/system_stm32f0xx.c ****
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138:Src/system_stm32f0xx.c **** /**
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139:Src/system_stm32f0xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values.
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140:Src/system_stm32f0xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can
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141:Src/system_stm32f0xx.c **** * be used by the user application to setup the SysTick timer or configure
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142:Src/system_stm32f0xx.c **** * other parameters.
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143:Src/system_stm32f0xx.c **** *
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144:Src/system_stm32f0xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called
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145:Src/system_stm32f0xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration
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146:Src/system_stm32f0xx.c **** * based on this variable will be incorrect.
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147:Src/system_stm32f0xx.c **** *
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148:Src/system_stm32f0xx.c **** * @note - The system frequency computed by this function is not the real
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149:Src/system_stm32f0xx.c **** * frequency in the chip. It is calculated based on the predefined
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150:Src/system_stm32f0xx.c **** * constant and the selected clock source:
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151:Src/system_stm32f0xx.c **** *
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152:Src/system_stm32f0xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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153:Src/system_stm32f0xx.c **** *
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154:Src/system_stm32f0xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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155:Src/system_stm32f0xx.c **** *
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156:Src/system_stm32f0xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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157:Src/system_stm32f0xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors.
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158:Src/system_stm32f0xx.c **** *
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159:Src/system_stm32f0xx.c **** * (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
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160:Src/system_stm32f0xx.c **** * 8 MHz) but the real value may vary depending on the variations
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161:Src/system_stm32f0xx.c **** * in voltage and temperature.
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162:Src/system_stm32f0xx.c **** *
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163:Src/system_stm32f0xx.c **** * (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (its value
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164:Src/system_stm32f0xx.c **** * depends on the application requirements), user has to ensure that HSE_VALUE
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165:Src/system_stm32f0xx.c **** * is same as the real frequency of the crystal used. Otherwise, this function
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166:Src/system_stm32f0xx.c **** * may have wrong result.
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167:Src/system_stm32f0xx.c **** *
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168:Src/system_stm32f0xx.c **** * - The result of this function could be not correct when using fractional
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169:Src/system_stm32f0xx.c **** * value for HSE crystal.
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170:Src/system_stm32f0xx.c **** *
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171:Src/system_stm32f0xx.c **** * @param None
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172:Src/system_stm32f0xx.c **** * @retval None
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173:Src/system_stm32f0xx.c **** */
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174:Src/system_stm32f0xx.c **** void SystemCoreClockUpdate (void)
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175:Src/system_stm32f0xx.c **** {
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48 .loc 1 175 0
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49 .cfi_startproc
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50 @ args = 0, pretend = 0, frame = 0
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51 @ frame_needed = 0, uses_anonymous_args = 0
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52 0000 10B5 push {r4, lr}
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53 .LCFI0:
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54 .cfi_def_cfa_offset 8
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55 .cfi_offset 4, -8
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56 .cfi_offset 14, -4
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ARM GAS /tmp/ccjISuh0.s page 5
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57 .LVL0:
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176:Src/system_stm32f0xx.c **** uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
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177:Src/system_stm32f0xx.c ****
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178:Src/system_stm32f0xx.c **** /* Get SYSCLK source -------------------------------------------------------*/
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179:Src/system_stm32f0xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS;
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58 .loc 1 179 0
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59 0002 254B ldr r3, .L14
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60 0004 5A68 ldr r2, [r3, #4]
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61 0006 0C23 movs r3, #12
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62 0008 1340 ands r3, r2
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63 .LVL1:
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180:Src/system_stm32f0xx.c ****
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181:Src/system_stm32f0xx.c **** switch (tmp)
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64 .loc 1 181 0
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65 000a 042B cmp r3, #4
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66 000c 16D0 beq .L4
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67 000e 082B cmp r3, #8
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68 0010 18D0 beq .L5
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69 0012 002B cmp r3, #0
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70 0014 03D0 beq .L11
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182:Src/system_stm32f0xx.c **** {
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183:Src/system_stm32f0xx.c **** case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
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184:Src/system_stm32f0xx.c **** SystemCoreClock = HSI_VALUE;
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185:Src/system_stm32f0xx.c **** break;
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186:Src/system_stm32f0xx.c **** case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
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187:Src/system_stm32f0xx.c **** SystemCoreClock = HSE_VALUE;
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188:Src/system_stm32f0xx.c **** break;
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189:Src/system_stm32f0xx.c **** case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
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190:Src/system_stm32f0xx.c **** /* Get PLL clock source and multiplication factor ----------------------*/
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191:Src/system_stm32f0xx.c **** pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
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192:Src/system_stm32f0xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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193:Src/system_stm32f0xx.c **** pllmull = ( pllmull >> 18) + 2;
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194:Src/system_stm32f0xx.c **** predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
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195:Src/system_stm32f0xx.c ****
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196:Src/system_stm32f0xx.c **** if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
|
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197:Src/system_stm32f0xx.c **** {
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198:Src/system_stm32f0xx.c **** /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
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199:Src/system_stm32f0xx.c **** SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
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200:Src/system_stm32f0xx.c **** }
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201:Src/system_stm32f0xx.c **** #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) ||
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202:Src/system_stm32f0xx.c **** else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
|
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203:Src/system_stm32f0xx.c **** {
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204:Src/system_stm32f0xx.c **** /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
|
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205:Src/system_stm32f0xx.c **** SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
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206:Src/system_stm32f0xx.c **** }
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207:Src/system_stm32f0xx.c **** #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
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208:Src/system_stm32f0xx.c **** else
|
|
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209:Src/system_stm32f0xx.c **** {
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210:Src/system_stm32f0xx.c **** #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
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211:Src/system_stm32f0xx.c **** || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
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212:Src/system_stm32f0xx.c **** || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
|
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213:Src/system_stm32f0xx.c **** /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
|
|
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214:Src/system_stm32f0xx.c **** SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
|
|
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215:Src/system_stm32f0xx.c **** #else
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216:Src/system_stm32f0xx.c **** /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
|
|
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217:Src/system_stm32f0xx.c **** SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
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|
218:Src/system_stm32f0xx.c **** #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
|
|
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ARM GAS /tmp/ccjISuh0.s page 6
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219:Src/system_stm32f0xx.c **** STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
|
|
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220:Src/system_stm32f0xx.c **** STM32F091xC || STM32F098xx || STM32F030xC */
|
|
|
221:Src/system_stm32f0xx.c **** }
|
|
|
222:Src/system_stm32f0xx.c **** break;
|
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223:Src/system_stm32f0xx.c **** default: /* HSI used as system clock */
|
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|
224:Src/system_stm32f0xx.c **** SystemCoreClock = HSI_VALUE;
|
|
|
71 .loc 1 224 0
|
|
|
72 0016 214B ldr r3, .L14+4
|
|
|
73 .LVL2:
|
|
|
74 0018 214A ldr r2, .L14+8
|
|
|
75 .LVL3:
|
|
|
76 001a 1A60 str r2, [r3]
|
|
|
225:Src/system_stm32f0xx.c **** break;
|
|
|
77 .loc 1 225 0
|
|
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78 001c 02E0 b .L7
|
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|
79 .LVL4:
|
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|
80 .L11:
|
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|
184:Src/system_stm32f0xx.c **** break;
|
|
|
81 .loc 1 184 0
|
|
|
82 001e 1F4B ldr r3, .L14+4
|
|
|
83 .LVL5:
|
|
|
84 0020 1F4A ldr r2, .L14+8
|
|
|
85 .LVL6:
|
|
|
86 0022 1A60 str r2, [r3]
|
|
|
87 .LVL7:
|
|
|
88 .L7:
|
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|
226:Src/system_stm32f0xx.c **** }
|
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|
227:Src/system_stm32f0xx.c **** /* Compute HCLK clock frequency ----------------*/
|
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|
228:Src/system_stm32f0xx.c **** /* Get HCLK prescaler */
|
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|
229:Src/system_stm32f0xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
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|
89 .loc 1 229 0
|
|
|
90 0024 1C4B ldr r3, .L14
|
|
|
91 0026 5A68 ldr r2, [r3, #4]
|
|
|
92 0028 1209 lsrs r2, r2, #4
|
|
|
93 002a 0F23 movs r3, #15
|
|
|
94 002c 1340 ands r3, r2
|
|
|
95 002e 1D4A ldr r2, .L14+12
|
|
|
96 0030 D35C ldrb r3, [r2, r3]
|
|
|
97 .LVL8:
|
|
|
230:Src/system_stm32f0xx.c **** /* HCLK clock frequency */
|
|
|
231:Src/system_stm32f0xx.c **** SystemCoreClock >>= tmp;
|
|
|
98 .loc 1 231 0
|
|
|
99 0032 1A4A ldr r2, .L14+4
|
|
|
100 0034 1168 ldr r1, [r2]
|
|
|
101 0036 D940 lsrs r1, r1, r3
|
|
|
102 0038 1160 str r1, [r2]
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|
232:Src/system_stm32f0xx.c **** }
|
|
|
103 .loc 1 232 0
|
|
|
104 @ sp needed
|
|
|
105 003a 10BD pop {r4, pc}
|
|
|
106 .LVL9:
|
|
|
107 .L4:
|
|
|
187:Src/system_stm32f0xx.c **** break;
|
|
|
108 .loc 1 187 0
|
|
|
109 003c 174B ldr r3, .L14+4
|
|
|
110 .LVL10:
|
|
|
111 003e 184A ldr r2, .L14+8
|
|
|
ARM GAS /tmp/ccjISuh0.s page 7
|
|
|
|
|
|
|
|
|
112 .LVL11:
|
|
|
113 0040 1A60 str r2, [r3]
|
|
|
188:Src/system_stm32f0xx.c **** case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
|
|
|
114 .loc 1 188 0
|
|
|
115 0042 EFE7 b .L7
|
|
|
116 .LVL12:
|
|
|
117 .L5:
|
|
|
191:Src/system_stm32f0xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
|
|
118 .loc 1 191 0
|
|
|
119 0044 144A ldr r2, .L14
|
|
|
120 0046 5068 ldr r0, [r2, #4]
|
|
|
121 .LVL13:
|
|
|
192:Src/system_stm32f0xx.c **** pllmull = ( pllmull >> 18) + 2;
|
|
|
122 .loc 1 192 0
|
|
|
123 0048 5368 ldr r3, [r2, #4]
|
|
|
124 .LVL14:
|
|
|
125 004a C021 movs r1, #192
|
|
|
126 004c 4902 lsls r1, r1, #9
|
|
|
127 004e 0B40 ands r3, r1
|
|
|
128 .LVL15:
|
|
|
193:Src/system_stm32f0xx.c **** predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
|
|
|
129 .loc 1 193 0
|
|
|
130 0050 800C lsrs r0, r0, #18
|
|
|
131 .LVL16:
|
|
|
132 0052 0F21 movs r1, #15
|
|
|
133 0054 0840 ands r0, r1
|
|
|
134 0056 841C adds r4, r0, #2
|
|
|
135 .LVL17:
|
|
|
194:Src/system_stm32f0xx.c ****
|
|
|
136 .loc 1 194 0
|
|
|
137 0058 D26A ldr r2, [r2, #44]
|
|
|
138 005a 1140 ands r1, r2
|
|
|
139 005c 0131 adds r1, r1, #1
|
|
|
140 .LVL18:
|
|
|
196:Src/system_stm32f0xx.c **** {
|
|
|
141 .loc 1 196 0
|
|
|
142 005e 8022 movs r2, #128
|
|
|
143 0060 5202 lsls r2, r2, #9
|
|
|
144 0062 9342 cmp r3, r2
|
|
|
145 0064 0AD0 beq .L12
|
|
|
202:Src/system_stm32f0xx.c **** {
|
|
|
146 .loc 1 202 0
|
|
|
147 0066 C022 movs r2, #192
|
|
|
148 0068 5202 lsls r2, r2, #9
|
|
|
149 006a 9342 cmp r3, r2
|
|
|
150 006c 0DD0 beq .L13
|
|
|
214:Src/system_stm32f0xx.c **** #else
|
|
|
151 .loc 1 214 0
|
|
|
152 006e 0C48 ldr r0, .L14+8
|
|
|
153 0070 FFF7FEFF bl __aeabi_uidiv
|
|
|
154 .LVL19:
|
|
|
155 0074 6043 muls r0, r4
|
|
|
156 0076 094B ldr r3, .L14+4
|
|
|
157 0078 1860 str r0, [r3]
|
|
|
158 007a D3E7 b .L7
|
|
|
159 .LVL20:
|
|
|
160 .L12:
|
|
|
ARM GAS /tmp/ccjISuh0.s page 8
|
|
|
|
|
|
|
|
|
199:Src/system_stm32f0xx.c **** }
|
|
|
161 .loc 1 199 0
|
|
|
162 007c 0848 ldr r0, .L14+8
|
|
|
163 007e FFF7FEFF bl __aeabi_uidiv
|
|
|
164 .LVL21:
|
|
|
165 0082 6043 muls r0, r4
|
|
|
166 0084 054B ldr r3, .L14+4
|
|
|
167 0086 1860 str r0, [r3]
|
|
|
168 0088 CCE7 b .L7
|
|
|
169 .LVL22:
|
|
|
170 .L13:
|
|
|
205:Src/system_stm32f0xx.c **** }
|
|
|
171 .loc 1 205 0
|
|
|
172 008a 0748 ldr r0, .L14+16
|
|
|
173 008c FFF7FEFF bl __aeabi_uidiv
|
|
|
174 .LVL23:
|
|
|
175 0090 6043 muls r0, r4
|
|
|
176 0092 024B ldr r3, .L14+4
|
|
|
177 0094 1860 str r0, [r3]
|
|
|
178 0096 C5E7 b .L7
|
|
|
179 .L15:
|
|
|
180 .align 2
|
|
|
181 .L14:
|
|
|
182 0098 00100240 .word 1073876992
|
|
|
183 009c 00000000 .word .LANCHOR0
|
|
|
184 00a0 00127A00 .word 8000000
|
|
|
185 00a4 00000000 .word .LANCHOR1
|
|
|
186 00a8 006CDC02 .word 48000000
|
|
|
187 .cfi_endproc
|
|
|
188 .LFE41:
|
|
|
190 .global APBPrescTable
|
|
|
191 .global AHBPrescTable
|
|
|
192 .global SystemCoreClock
|
|
|
193 .section .data.SystemCoreClock,"aw",%progbits
|
|
|
194 .align 2
|
|
|
195 .set .LANCHOR0,. + 0
|
|
|
198 SystemCoreClock:
|
|
|
199 0000 00127A00 .word 8000000
|
|
|
200 .section .rodata.AHBPrescTable,"a",%progbits
|
|
|
201 .align 2
|
|
|
202 .set .LANCHOR1,. + 0
|
|
|
205 AHBPrescTable:
|
|
|
206 0000 00 .byte 0
|
|
|
207 0001 00 .byte 0
|
|
|
208 0002 00 .byte 0
|
|
|
209 0003 00 .byte 0
|
|
|
210 0004 00 .byte 0
|
|
|
211 0005 00 .byte 0
|
|
|
212 0006 00 .byte 0
|
|
|
213 0007 00 .byte 0
|
|
|
214 0008 01 .byte 1
|
|
|
215 0009 02 .byte 2
|
|
|
216 000a 03 .byte 3
|
|
|
217 000b 04 .byte 4
|
|
|
218 000c 06 .byte 6
|
|
|
219 000d 07 .byte 7
|
|
|
220 000e 08 .byte 8
|
|
|
ARM GAS /tmp/ccjISuh0.s page 9
|
|
|
|
|
|
|
|
|
221 000f 09 .byte 9
|
|
|
222 .section .rodata.APBPrescTable,"a",%progbits
|
|
|
223 .align 2
|
|
|
226 APBPrescTable:
|
|
|
227 0000 00 .byte 0
|
|
|
228 0001 00 .byte 0
|
|
|
229 0002 00 .byte 0
|
|
|
230 0003 00 .byte 0
|
|
|
231 0004 01 .byte 1
|
|
|
232 0005 02 .byte 2
|
|
|
233 0006 03 .byte 3
|
|
|
234 0007 04 .byte 4
|
|
|
235 .text
|
|
|
236 .Letext0:
|
|
|
237 .file 2 "/usr/include/newlib/machine/_default_types.h"
|
|
|
238 .file 3 "/usr/include/newlib/sys/_stdint.h"
|
|
|
239 .file 4 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h"
|
|
|
240 .file 5 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h"
|
|
|
ARM GAS /tmp/ccjISuh0.s page 10
|
|
|
|
|
|
|
|
|
DEFINED SYMBOLS
|
|
|
*ABS*:0000000000000000 system_stm32f0xx.c
|
|
|
/tmp/ccjISuh0.s:16 .text.SystemInit:0000000000000000 $t
|
|
|
/tmp/ccjISuh0.s:23 .text.SystemInit:0000000000000000 SystemInit
|
|
|
/tmp/ccjISuh0.s:39 .text.SystemCoreClockUpdate:0000000000000000 $t
|
|
|
/tmp/ccjISuh0.s:46 .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate
|
|
|
/tmp/ccjISuh0.s:182 .text.SystemCoreClockUpdate:0000000000000098 $d
|
|
|
/tmp/ccjISuh0.s:226 .rodata.APBPrescTable:0000000000000000 APBPrescTable
|
|
|
/tmp/ccjISuh0.s:205 .rodata.AHBPrescTable:0000000000000000 AHBPrescTable
|
|
|
/tmp/ccjISuh0.s:198 .data.SystemCoreClock:0000000000000000 SystemCoreClock
|
|
|
/tmp/ccjISuh0.s:194 .data.SystemCoreClock:0000000000000000 $d
|
|
|
/tmp/ccjISuh0.s:201 .rodata.AHBPrescTable:0000000000000000 $d
|
|
|
/tmp/ccjISuh0.s:223 .rodata.APBPrescTable:0000000000000000 $d
|
|
|
|
|
|
UNDEFINED SYMBOLS
|
|
|
__aeabi_uidiv
|
