ARM GAS  C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s 			page 1


   1              		.cpu cortex-m0
   2              		.eabi_attribute 20, 1
   3              		.eabi_attribute 21, 1
   4              		.eabi_attribute 23, 3
   5              		.eabi_attribute 24, 1
   6              		.eabi_attribute 25, 1
   7              		.eabi_attribute 26, 1
   8              		.eabi_attribute 30, 1
   9              		.eabi_attribute 34, 0
  10              		.eabi_attribute 18, 4
  11              		.file	"system_stm32f0xx.c"
  12              		.text
  13              	.Ltext0:
  14              		.cfi_sections	.debug_frame
  15              		.section	.text.SystemInit,"ax",%progbits
  16              		.align	1
  17              		.global	SystemInit
  18              		.arch armv6s-m
  19              		.syntax unified
  20              		.code	16
  21              		.thumb_func
  22              		.fpu softvfp
  24              	SystemInit:
  25              	.LFB40:
  26              		.file 1 "Src/system_stm32f0xx.c"
   1:Src/system_stm32f0xx.c **** /**
   2:Src/system_stm32f0xx.c ****   ******************************************************************************
   3:Src/system_stm32f0xx.c ****   * @file    system_stm32f0xx.c
   4:Src/system_stm32f0xx.c ****   * @author  MCD Application Team
   5:Src/system_stm32f0xx.c ****   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
   6:Src/system_stm32f0xx.c ****   *
   7:Src/system_stm32f0xx.c ****   * 1. This file provides two functions and one global variable to be called from
   8:Src/system_stm32f0xx.c ****   *    user application:
   9:Src/system_stm32f0xx.c ****   *      - SystemInit(): This function is called at startup just after reset and 
  10:Src/system_stm32f0xx.c ****   *                      before branch to main program. This call is made inside
  11:Src/system_stm32f0xx.c ****   *                      the "startup_stm32f0xx.s" file.
  12:Src/system_stm32f0xx.c ****   *
  13:Src/system_stm32f0xx.c ****   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  14:Src/system_stm32f0xx.c ****   *                                  by the user application to setup the SysTick
  15:Src/system_stm32f0xx.c ****   *                                  timer or configure other parameters.
  16:Src/system_stm32f0xx.c ****   *
  17:Src/system_stm32f0xx.c ****   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  18:Src/system_stm32f0xx.c ****   *                                 be called whenever the core clock is changed
  19:Src/system_stm32f0xx.c ****   *                                 during program execution.
  20:Src/system_stm32f0xx.c ****   *
  21:Src/system_stm32f0xx.c ****   *
  22:Src/system_stm32f0xx.c ****   ******************************************************************************
  23:Src/system_stm32f0xx.c ****   * @attention
  24:Src/system_stm32f0xx.c ****   *
  25:Src/system_stm32f0xx.c ****   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  26:Src/system_stm32f0xx.c ****   * All rights reserved.</center></h2>
  27:Src/system_stm32f0xx.c ****   *
  28:Src/system_stm32f0xx.c ****   * This software component is licensed by ST under BSD 3-Clause license,
  29:Src/system_stm32f0xx.c ****   * the "License"; You may not use this file except in compliance with the
  30:Src/system_stm32f0xx.c ****   * License. You may obtain a copy of the License at:
  31:Src/system_stm32f0xx.c ****   *                        opensource.org/licenses/BSD-3-Clause
  32:Src/system_stm32f0xx.c ****   *
ARM GAS  C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s 			page 2


  33:Src/system_stm32f0xx.c ****   ******************************************************************************
  34:Src/system_stm32f0xx.c ****   */
  35:Src/system_stm32f0xx.c **** 
  36:Src/system_stm32f0xx.c **** /** @addtogroup CMSIS
  37:Src/system_stm32f0xx.c ****   * @{
  38:Src/system_stm32f0xx.c ****   */
  39:Src/system_stm32f0xx.c **** 
  40:Src/system_stm32f0xx.c **** /** @addtogroup stm32f0xx_system
  41:Src/system_stm32f0xx.c ****   * @{
  42:Src/system_stm32f0xx.c ****   */
  43:Src/system_stm32f0xx.c **** 
  44:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_Includes
  45:Src/system_stm32f0xx.c ****   * @{
  46:Src/system_stm32f0xx.c ****   */
  47:Src/system_stm32f0xx.c **** 
  48:Src/system_stm32f0xx.c **** #include "stm32f0xx.h"
  49:Src/system_stm32f0xx.c **** 
  50:Src/system_stm32f0xx.c **** /**
  51:Src/system_stm32f0xx.c ****   * @}
  52:Src/system_stm32f0xx.c ****   */
  53:Src/system_stm32f0xx.c **** 
  54:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
  55:Src/system_stm32f0xx.c ****   * @{
  56:Src/system_stm32f0xx.c ****   */
  57:Src/system_stm32f0xx.c **** 
  58:Src/system_stm32f0xx.c **** /**
  59:Src/system_stm32f0xx.c ****   * @}
  60:Src/system_stm32f0xx.c ****   */
  61:Src/system_stm32f0xx.c **** 
  62:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_Defines
  63:Src/system_stm32f0xx.c ****   * @{
  64:Src/system_stm32f0xx.c ****   */
  65:Src/system_stm32f0xx.c **** #if !defined  (HSE_VALUE) 
  66:Src/system_stm32f0xx.c ****   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
  67:Src/system_stm32f0xx.c ****                                                 This value can be provided and adapted by the user 
  68:Src/system_stm32f0xx.c **** #endif /* HSE_VALUE */
  69:Src/system_stm32f0xx.c **** 
  70:Src/system_stm32f0xx.c **** #if !defined  (HSI_VALUE)
  71:Src/system_stm32f0xx.c ****   #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
  72:Src/system_stm32f0xx.c ****                                                 This value can be provided and adapted by the user 
  73:Src/system_stm32f0xx.c **** #endif /* HSI_VALUE */
  74:Src/system_stm32f0xx.c **** 
  75:Src/system_stm32f0xx.c **** #if !defined (HSI48_VALUE)
  76:Src/system_stm32f0xx.c **** #define HSI48_VALUE    ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in 
  77:Src/system_stm32f0xx.c ****                                                  This value can be provided and adapted by the user
  78:Src/system_stm32f0xx.c **** #endif /* HSI48_VALUE */
  79:Src/system_stm32f0xx.c **** /**
  80:Src/system_stm32f0xx.c ****   * @}
  81:Src/system_stm32f0xx.c ****   */
  82:Src/system_stm32f0xx.c **** 
  83:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_Macros
  84:Src/system_stm32f0xx.c ****   * @{
  85:Src/system_stm32f0xx.c ****   */
  86:Src/system_stm32f0xx.c **** 
  87:Src/system_stm32f0xx.c **** /**
  88:Src/system_stm32f0xx.c ****   * @}
  89:Src/system_stm32f0xx.c ****   */
ARM GAS  C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s 			page 3


  90:Src/system_stm32f0xx.c **** 
  91:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_Variables
  92:Src/system_stm32f0xx.c ****   * @{
  93:Src/system_stm32f0xx.c ****   */
  94:Src/system_stm32f0xx.c ****   /* This variable is updated in three ways:
  95:Src/system_stm32f0xx.c ****       1) by calling CMSIS function SystemCoreClockUpdate()
  96:Src/system_stm32f0xx.c ****       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
  97:Src/system_stm32f0xx.c ****       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
  98:Src/system_stm32f0xx.c ****          Note: If you use this function to configure the system clock; then there
  99:Src/system_stm32f0xx.c ****                is no need to call the 2 first functions listed above, since SystemCoreClock
 100:Src/system_stm32f0xx.c ****                variable is updated automatically.
 101:Src/system_stm32f0xx.c ****   */
 102:Src/system_stm32f0xx.c **** uint32_t SystemCoreClock = 8000000;
 103:Src/system_stm32f0xx.c **** 
 104:Src/system_stm32f0xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 105:Src/system_stm32f0xx.c **** const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
 106:Src/system_stm32f0xx.c **** 
 107:Src/system_stm32f0xx.c **** /**
 108:Src/system_stm32f0xx.c ****   * @}
 109:Src/system_stm32f0xx.c ****   */
 110:Src/system_stm32f0xx.c **** 
 111:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
 112:Src/system_stm32f0xx.c ****   * @{
 113:Src/system_stm32f0xx.c ****   */
 114:Src/system_stm32f0xx.c **** 
 115:Src/system_stm32f0xx.c **** /**
 116:Src/system_stm32f0xx.c ****   * @}
 117:Src/system_stm32f0xx.c ****   */
 118:Src/system_stm32f0xx.c **** 
 119:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_Functions
 120:Src/system_stm32f0xx.c ****   * @{
 121:Src/system_stm32f0xx.c ****   */
 122:Src/system_stm32f0xx.c **** 
 123:Src/system_stm32f0xx.c **** /**
 124:Src/system_stm32f0xx.c ****   * @brief  Setup the microcontroller system
 125:Src/system_stm32f0xx.c ****   * @param  None
 126:Src/system_stm32f0xx.c ****   * @retval None
 127:Src/system_stm32f0xx.c ****   */
 128:Src/system_stm32f0xx.c **** void SystemInit(void)
 129:Src/system_stm32f0xx.c **** {
  27              		.loc 1 129 1 view -0
  28              		.cfi_startproc
  29              		@ args = 0, pretend = 0, frame = 0
  30              		@ frame_needed = 0, uses_anonymous_args = 0
  31              		@ link register save eliminated.
 130:Src/system_stm32f0xx.c ****   /* NOTE :SystemInit(): This function is called at startup just after reset and 
 131:Src/system_stm32f0xx.c ****                          before branch to main program. This call is made inside
 132:Src/system_stm32f0xx.c ****                          the "startup_stm32f0xx.s" file.
 133:Src/system_stm32f0xx.c ****                          User can setups the default system clock (System clock source, PLL Multipl
 134:Src/system_stm32f0xx.c ****                          and Divider factors, AHB/APBx prescalers and Flash settings).
 135:Src/system_stm32f0xx.c ****    */
 136:Src/system_stm32f0xx.c **** }
  32              		.loc 1 136 1 view .LVU1
  33              		@ sp needed
  34 0000 7047     		bx	lr
  35              		.cfi_endproc
  36              	.LFE40:
ARM GAS  C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s 			page 4


  38              		.global	__aeabi_uidiv
  39              		.section	.text.SystemCoreClockUpdate,"ax",%progbits
  40              		.align	1
  41              		.global	SystemCoreClockUpdate
  42              		.syntax unified
  43              		.code	16
  44              		.thumb_func
  45              		.fpu softvfp
  47              	SystemCoreClockUpdate:
  48              	.LFB41:
 137:Src/system_stm32f0xx.c **** 
 138:Src/system_stm32f0xx.c **** /**
 139:Src/system_stm32f0xx.c ****    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 140:Src/system_stm32f0xx.c ****   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 141:Src/system_stm32f0xx.c ****   *         be used by the user application to setup the SysTick timer or configure
 142:Src/system_stm32f0xx.c ****   *         other parameters.
 143:Src/system_stm32f0xx.c ****   *
 144:Src/system_stm32f0xx.c ****   * @note   Each time the core clock (HCLK) changes, this function must be called
 145:Src/system_stm32f0xx.c ****   *         to update SystemCoreClock variable value. Otherwise, any configuration
 146:Src/system_stm32f0xx.c ****   *         based on this variable will be incorrect.
 147:Src/system_stm32f0xx.c ****   *
 148:Src/system_stm32f0xx.c ****   * @note   - The system frequency computed by this function is not the real
 149:Src/system_stm32f0xx.c ****   *           frequency in the chip. It is calculated based on the predefined
 150:Src/system_stm32f0xx.c ****   *           constant and the selected clock source:
 151:Src/system_stm32f0xx.c ****   *
 152:Src/system_stm32f0xx.c ****   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 153:Src/system_stm32f0xx.c ****   *
 154:Src/system_stm32f0xx.c ****   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 155:Src/system_stm32f0xx.c ****   *
 156:Src/system_stm32f0xx.c ****   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 157:Src/system_stm32f0xx.c ****   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 158:Src/system_stm32f0xx.c ****   *
 159:Src/system_stm32f0xx.c ****   *         (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
 160:Src/system_stm32f0xx.c ****   *             8 MHz) but the real value may vary depending on the variations
 161:Src/system_stm32f0xx.c ****   *             in voltage and temperature.
 162:Src/system_stm32f0xx.c ****   *
 163:Src/system_stm32f0xx.c ****   *         (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (its value
 164:Src/system_stm32f0xx.c ****   *              depends on the application requirements), user has to ensure that HSE_VALUE
 165:Src/system_stm32f0xx.c ****   *              is same as the real frequency of the crystal used. Otherwise, this function
 166:Src/system_stm32f0xx.c ****   *              may have wrong result.
 167:Src/system_stm32f0xx.c ****   *
 168:Src/system_stm32f0xx.c ****   *         - The result of this function could be not correct when using fractional
 169:Src/system_stm32f0xx.c ****   *           value for HSE crystal.
 170:Src/system_stm32f0xx.c ****   *
 171:Src/system_stm32f0xx.c ****   * @param  None
 172:Src/system_stm32f0xx.c ****   * @retval None
 173:Src/system_stm32f0xx.c ****   */
 174:Src/system_stm32f0xx.c **** void SystemCoreClockUpdate (void)
 175:Src/system_stm32f0xx.c **** {
  49              		.loc 1 175 1 view -0
  50              		.cfi_startproc
  51              		@ args = 0, pretend = 0, frame = 0
  52              		@ frame_needed = 0, uses_anonymous_args = 0
  53 0000 10B5     		push	{r4, lr}
  54              	.LCFI0:
  55              		.cfi_def_cfa_offset 8
  56              		.cfi_offset 4, -8
ARM GAS  C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s 			page 5


  57              		.cfi_offset 14, -4
 176:Src/system_stm32f0xx.c ****   uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
  58              		.loc 1 176 3 view .LVU3
  59              	.LVL0:
 177:Src/system_stm32f0xx.c **** 
 178:Src/system_stm32f0xx.c ****   /* Get SYSCLK source -------------------------------------------------------*/
 179:Src/system_stm32f0xx.c ****   tmp = RCC->CFGR & RCC_CFGR_SWS;
  60              		.loc 1 179 3 view .LVU4
  61              		.loc 1 179 12 is_stmt 0 view .LVU5
  62 0002 254B     		ldr	r3, .L12
  63 0004 5A68     		ldr	r2, [r3, #4]
  64              		.loc 1 179 7 view .LVU6
  65 0006 0C23     		movs	r3, #12
  66 0008 1340     		ands	r3, r2
  67              	.LVL1:
 180:Src/system_stm32f0xx.c **** 
 181:Src/system_stm32f0xx.c ****   switch (tmp)
  68              		.loc 1 181 3 is_stmt 1 view .LVU7
  69 000a 042B     		cmp	r3, #4
  70 000c 16D0     		beq	.L3
  71 000e 082B     		cmp	r3, #8
  72 0010 18D0     		beq	.L4
  73 0012 002B     		cmp	r3, #0
  74 0014 03D0     		beq	.L9
 182:Src/system_stm32f0xx.c ****   {
 183:Src/system_stm32f0xx.c ****     case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
 184:Src/system_stm32f0xx.c ****       SystemCoreClock = HSI_VALUE;
 185:Src/system_stm32f0xx.c ****       break;
 186:Src/system_stm32f0xx.c ****     case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
 187:Src/system_stm32f0xx.c ****       SystemCoreClock = HSE_VALUE;
 188:Src/system_stm32f0xx.c ****       break;
 189:Src/system_stm32f0xx.c ****     case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
 190:Src/system_stm32f0xx.c ****       /* Get PLL clock source and multiplication factor ----------------------*/
 191:Src/system_stm32f0xx.c ****       pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
 192:Src/system_stm32f0xx.c ****       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 193:Src/system_stm32f0xx.c ****       pllmull = ( pllmull >> 18) + 2;
 194:Src/system_stm32f0xx.c ****       predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
 195:Src/system_stm32f0xx.c **** 
 196:Src/system_stm32f0xx.c ****       if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
 197:Src/system_stm32f0xx.c ****       {
 198:Src/system_stm32f0xx.c ****         /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
 199:Src/system_stm32f0xx.c ****         SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
 200:Src/system_stm32f0xx.c ****       }
 201:Src/system_stm32f0xx.c **** #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) ||
 202:Src/system_stm32f0xx.c ****       else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
 203:Src/system_stm32f0xx.c ****       {
 204:Src/system_stm32f0xx.c ****         /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
 205:Src/system_stm32f0xx.c ****         SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
 206:Src/system_stm32f0xx.c ****       }
 207:Src/system_stm32f0xx.c **** #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
 208:Src/system_stm32f0xx.c ****       else
 209:Src/system_stm32f0xx.c ****       {
 210:Src/system_stm32f0xx.c **** #if defined(STM32F042x6) || defined(STM32F048xx)  || defined(STM32F070x6) \
 211:Src/system_stm32f0xx.c ****  || defined(STM32F078xx) || defined(STM32F071xB)  || defined(STM32F072xB) \
 212:Src/system_stm32f0xx.c ****  || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx)  || defined(STM32F030xC)
 213:Src/system_stm32f0xx.c ****         /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
 214:Src/system_stm32f0xx.c ****         SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
ARM GAS  C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s 			page 6


 215:Src/system_stm32f0xx.c **** #else
 216:Src/system_stm32f0xx.c ****         /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
 217:Src/system_stm32f0xx.c ****         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
 218:Src/system_stm32f0xx.c **** #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || 
 219:Src/system_stm32f0xx.c ****           STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
 220:Src/system_stm32f0xx.c ****           STM32F091xC || STM32F098xx || STM32F030xC */
 221:Src/system_stm32f0xx.c ****       }
 222:Src/system_stm32f0xx.c ****       break;
 223:Src/system_stm32f0xx.c ****     default: /* HSI used as system clock */
 224:Src/system_stm32f0xx.c ****       SystemCoreClock = HSI_VALUE;
  75              		.loc 1 224 7 view .LVU8
  76              		.loc 1 224 23 is_stmt 0 view .LVU9
  77 0016 214B     		ldr	r3, .L12+4
  78              	.LVL2:
  79              		.loc 1 224 23 view .LVU10
  80 0018 214A     		ldr	r2, .L12+8
  81              	.LVL3:
  82              		.loc 1 224 23 view .LVU11
  83 001a 1A60     		str	r2, [r3]
 225:Src/system_stm32f0xx.c ****       break;
  84              		.loc 1 225 7 is_stmt 1 view .LVU12
  85 001c 02E0     		b	.L6
  86              	.LVL4:
  87              	.L9:
 184:Src/system_stm32f0xx.c ****       break;
  88              		.loc 1 184 7 view .LVU13
 184:Src/system_stm32f0xx.c ****       break;
  89              		.loc 1 184 23 is_stmt 0 view .LVU14
  90 001e 1F4B     		ldr	r3, .L12+4
  91              	.LVL5:
 184:Src/system_stm32f0xx.c ****       break;
  92              		.loc 1 184 23 view .LVU15
  93 0020 1F4A     		ldr	r2, .L12+8
  94              	.LVL6:
 184:Src/system_stm32f0xx.c ****       break;
  95              		.loc 1 184 23 view .LVU16
  96 0022 1A60     		str	r2, [r3]
 185:Src/system_stm32f0xx.c ****     case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
  97              		.loc 1 185 7 is_stmt 1 view .LVU17
  98              	.LVL7:
  99              	.L6:
 226:Src/system_stm32f0xx.c ****   }
 227:Src/system_stm32f0xx.c ****   /* Compute HCLK clock frequency ----------------*/
 228:Src/system_stm32f0xx.c ****   /* Get HCLK prescaler */
 229:Src/system_stm32f0xx.c ****   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 100              		.loc 1 229 3 view .LVU18
 101              		.loc 1 229 28 is_stmt 0 view .LVU19
 102 0024 1C4B     		ldr	r3, .L12
 103 0026 5A68     		ldr	r2, [r3, #4]
 104              		.loc 1 229 52 view .LVU20
 105 0028 1209     		lsrs	r2, r2, #4
 106 002a 0F23     		movs	r3, #15
 107 002c 1340     		ands	r3, r2
 108              		.loc 1 229 22 view .LVU21
 109 002e 1D4A     		ldr	r2, .L12+12
 110 0030 D35C     		ldrb	r3, [r2, r3]
 111              	.LVL8:
ARM GAS  C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s 			page 7


 230:Src/system_stm32f0xx.c ****   /* HCLK clock frequency */
 231:Src/system_stm32f0xx.c ****   SystemCoreClock >>= tmp;
 112              		.loc 1 231 3 is_stmt 1 view .LVU22
 113              		.loc 1 231 19 is_stmt 0 view .LVU23
 114 0032 1A4A     		ldr	r2, .L12+4
 115 0034 1168     		ldr	r1, [r2]
 116 0036 D940     		lsrs	r1, r1, r3
 117 0038 1160     		str	r1, [r2]
 232:Src/system_stm32f0xx.c **** }
 118              		.loc 1 232 1 view .LVU24
 119              		@ sp needed
 120 003a 10BD     		pop	{r4, pc}
 121              	.LVL9:
 122              	.L3:
 187:Src/system_stm32f0xx.c ****       break;
 123              		.loc 1 187 7 is_stmt 1 view .LVU25
 187:Src/system_stm32f0xx.c ****       break;
 124              		.loc 1 187 23 is_stmt 0 view .LVU26
 125 003c 174B     		ldr	r3, .L12+4
 126              	.LVL10:
 187:Src/system_stm32f0xx.c ****       break;
 127              		.loc 1 187 23 view .LVU27
 128 003e 184A     		ldr	r2, .L12+8
 129              	.LVL11:
 187:Src/system_stm32f0xx.c ****       break;
 130              		.loc 1 187 23 view .LVU28
 131 0040 1A60     		str	r2, [r3]
 188:Src/system_stm32f0xx.c ****     case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
 132              		.loc 1 188 7 is_stmt 1 view .LVU29
 133 0042 EFE7     		b	.L6
 134              	.LVL12:
 135              	.L4:
 191:Src/system_stm32f0xx.c ****       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 136              		.loc 1 191 7 view .LVU30
 191:Src/system_stm32f0xx.c ****       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 137              		.loc 1 191 20 is_stmt 0 view .LVU31
 138 0044 1448     		ldr	r0, .L12
 139 0046 4368     		ldr	r3, [r0, #4]
 140              	.LVL13:
 192:Src/system_stm32f0xx.c ****       pllmull = ( pllmull >> 18) + 2;
 141              		.loc 1 192 7 is_stmt 1 view .LVU32
 192:Src/system_stm32f0xx.c ****       pllmull = ( pllmull >> 18) + 2;
 142              		.loc 1 192 22 is_stmt 0 view .LVU33
 143 0048 4268     		ldr	r2, [r0, #4]
 144              	.LVL14:
 192:Src/system_stm32f0xx.c ****       pllmull = ( pllmull >> 18) + 2;
 145              		.loc 1 192 17 view .LVU34
 146 004a C021     		movs	r1, #192
 147 004c 4902     		lsls	r1, r1, #9
 148 004e 0A40     		ands	r2, r1
 149              	.LVL15:
 193:Src/system_stm32f0xx.c ****       predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
 150              		.loc 1 193 7 is_stmt 1 view .LVU35
 193:Src/system_stm32f0xx.c ****       predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
 151              		.loc 1 193 27 is_stmt 0 view .LVU36
 152 0050 9B0C     		lsrs	r3, r3, #18
 153              	.LVL16:
ARM GAS  C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s 			page 8


 193:Src/system_stm32f0xx.c ****       predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
 154              		.loc 1 193 27 view .LVU37
 155 0052 0F21     		movs	r1, #15
 156 0054 0B40     		ands	r3, r1
 193:Src/system_stm32f0xx.c ****       predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
 157              		.loc 1 193 15 view .LVU38
 158 0056 9C1C     		adds	r4, r3, #2
 159              	.LVL17:
 194:Src/system_stm32f0xx.c **** 
 160              		.loc 1 194 7 is_stmt 1 view .LVU39
 194:Src/system_stm32f0xx.c **** 
 161              		.loc 1 194 26 is_stmt 0 view .LVU40
 162 0058 C36A     		ldr	r3, [r0, #44]
 194:Src/system_stm32f0xx.c **** 
 163              		.loc 1 194 34 view .LVU41
 164 005a 1940     		ands	r1, r3
 194:Src/system_stm32f0xx.c **** 
 165              		.loc 1 194 20 view .LVU42
 166 005c 0131     		adds	r1, r1, #1
 167              	.LVL18:
 196:Src/system_stm32f0xx.c ****       {
 168              		.loc 1 196 7 is_stmt 1 view .LVU43
 196:Src/system_stm32f0xx.c ****       {
 169              		.loc 1 196 10 is_stmt 0 view .LVU44
 170 005e 8023     		movs	r3, #128
 171 0060 5B02     		lsls	r3, r3, #9
 172 0062 9A42     		cmp	r2, r3
 173 0064 0AD0     		beq	.L10
 202:Src/system_stm32f0xx.c ****       {
 174              		.loc 1 202 12 is_stmt 1 view .LVU45
 202:Src/system_stm32f0xx.c ****       {
 175              		.loc 1 202 15 is_stmt 0 view .LVU46
 176 0066 C023     		movs	r3, #192
 177 0068 5B02     		lsls	r3, r3, #9
 178 006a 9A42     		cmp	r2, r3
 179 006c 0DD0     		beq	.L11
 214:Src/system_stm32f0xx.c **** #else
 180              		.loc 1 214 9 is_stmt 1 view .LVU47
 214:Src/system_stm32f0xx.c **** #else
 181              		.loc 1 214 37 is_stmt 0 view .LVU48
 182 006e 0C48     		ldr	r0, .L12+8
 183 0070 FFF7FEFF 		bl	__aeabi_uidiv
 184              	.LVL19:
 214:Src/system_stm32f0xx.c **** #else
 185              		.loc 1 214 52 view .LVU49
 186 0074 6043     		muls	r0, r4
 214:Src/system_stm32f0xx.c **** #else
 187              		.loc 1 214 25 view .LVU50
 188 0076 094A     		ldr	r2, .L12+4
 189 0078 1060     		str	r0, [r2]
 190 007a D3E7     		b	.L6
 191              	.LVL20:
 192              	.L10:
 199:Src/system_stm32f0xx.c ****       }
 193              		.loc 1 199 9 is_stmt 1 view .LVU51
 199:Src/system_stm32f0xx.c ****       }
 194              		.loc 1 199 37 is_stmt 0 view .LVU52
ARM GAS  C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s 			page 9


 195 007c 0848     		ldr	r0, .L12+8
 196 007e FFF7FEFF 		bl	__aeabi_uidiv
 197              	.LVL21:
 199:Src/system_stm32f0xx.c ****       }
 198              		.loc 1 199 52 view .LVU53
 199 0082 6043     		muls	r0, r4
 199:Src/system_stm32f0xx.c ****       }
 200              		.loc 1 199 25 view .LVU54
 201 0084 054A     		ldr	r2, .L12+4
 202 0086 1060     		str	r0, [r2]
 203 0088 CCE7     		b	.L6
 204              	.LVL22:
 205              	.L11:
 205:Src/system_stm32f0xx.c ****       }
 206              		.loc 1 205 9 is_stmt 1 view .LVU55
 205:Src/system_stm32f0xx.c ****       }
 207              		.loc 1 205 39 is_stmt 0 view .LVU56
 208 008a 0748     		ldr	r0, .L12+16
 209 008c FFF7FEFF 		bl	__aeabi_uidiv
 210              	.LVL23:
 205:Src/system_stm32f0xx.c ****       }
 211              		.loc 1 205 54 view .LVU57
 212 0090 6043     		muls	r0, r4
 205:Src/system_stm32f0xx.c ****       }
 213              		.loc 1 205 25 view .LVU58
 214 0092 024A     		ldr	r2, .L12+4
 215 0094 1060     		str	r0, [r2]
 216 0096 C5E7     		b	.L6
 217              	.L13:
 218              		.align	2
 219              	.L12:
 220 0098 00100240 		.word	1073876992
 221 009c 00000000 		.word	.LANCHOR0
 222 00a0 00127A00 		.word	8000000
 223 00a4 00000000 		.word	.LANCHOR1
 224 00a8 006CDC02 		.word	48000000
 225              		.cfi_endproc
 226              	.LFE41:
 228              		.global	APBPrescTable
 229              		.global	AHBPrescTable
 230              		.global	SystemCoreClock
 231              		.section	.data.SystemCoreClock,"aw"
 232              		.align	2
 233              		.set	.LANCHOR0,. + 0
 236              	SystemCoreClock:
 237 0000 00127A00 		.word	8000000
 238              		.section	.rodata.AHBPrescTable,"a"
 239              		.align	2
 240              		.set	.LANCHOR1,. + 0
 243              	AHBPrescTable:
 244 0000 00000000 		.ascii	"\000\000\000\000\000\000\000\000\001\002\003\004\006"
 244      00000000 
 244      01020304 
 244      06
 245 000d 070809   		.ascii	"\007\010\011"
 246              		.section	.rodata.APBPrescTable,"a"
 247              		.align	2
ARM GAS  C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s 			page 10


 250              	APBPrescTable:
 251 0000 00000000 		.ascii	"\000\000\000\000\001\002\003\004"
 251      01020304 
 252              		.text
 253              	.Letext0:
 254              		.file 2 "c:\\programdata\\chocolatey\\lib\\gcc-arm-embedded\\tools\\gcc-arm-none-eabi-10-2020-q4-m
 255              		.file 3 "c:\\programdata\\chocolatey\\lib\\gcc-arm-embedded\\tools\\gcc-arm-none-eabi-10-2020-q4-m
 256              		.file 4 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h"
 257              		.file 5 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h"
ARM GAS  C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s 			page 11


DEFINED SYMBOLS
                            *ABS*:00000000 system_stm32f0xx.c
C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s:16     .text.SystemInit:00000000 $t
C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s:24     .text.SystemInit:00000000 SystemInit
C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s:40     .text.SystemCoreClockUpdate:00000000 $t
C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s:47     .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate
C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s:220    .text.SystemCoreClockUpdate:00000098 $d
C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s:250    .rodata.APBPrescTable:00000000 APBPrescTable
C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s:243    .rodata.AHBPrescTable:00000000 AHBPrescTable
C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s:236    .data.SystemCoreClock:00000000 SystemCoreClock
C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s:232    .data.SystemCoreClock:00000000 $d
C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s:239    .rodata.AHBPrescTable:00000000 $d
C:\Users\144311\AppData\Local\Temp\cc5flEeJ.s:247    .rodata.APBPrescTable:00000000 $d

UNDEFINED SYMBOLS
__aeabi_uidiv