/**
**************************************************************************************************
* @file		hwd_interrupt.h		
* @author	Kerem Yollu & Edwin Koch
* @date		26.02.2023
* @version	1.0
************************************************************************************************** 
* @brief
* 
* **Detailed Description :**
*	
**************************************************************************************************
*/

#ifndef _HWD_INTERRUPT_H_
#define _HWD_INTERRUPT_H_

#ifdef __cplusplus
extern "C" {
#endif

#include "hardwareDescription.h"

/*! interrupt types. These act as indexes for the */
typedef enum {
	TIM1_BREAK,
	TIM1_UPDATE,
	TIM1_TRIGGER,
	TIM1_COMMUNICATION,
	TIM1_COUNTERCOMPARE_1,
	TIM1_COUNTERCOMPARE_2,
	TIM1_COUNTERCOMPARE_3,
	TIM1_COUNTERCOMPARE_4,
	TIM2_UPDATE,
	TIM2_COUNTERCOMPARE_1,
	TIM2_COUNTERCOMPARE_2,
	TIM2_COUNTERCOMPARE_3,
	TIM2_COUNTERCOMPARE_4,
	TIM2_TRIGGER,
	TIM2_CAPTURECOMPARE_1,
	TIM2_CAPTURECOMPARE_2,
	TIM2_CAPTURECOMPARE_3,
  	TIM2_CAPTURECOMAPRE_4,
	TIM3_UPDATE,
	TIM3_COUNTERCOMPARE_1,
	TIM3_COUNTERCOMPARE_2,
	TIM3_COUNTERCOMPARE_3,
	TIM3_COUNTERCOMPARE_4,
	TIM3_TRIGGER,
	TIM3_CAPTURECOMPARE_1,
	TIM3_CAPTURECOMPARE_2,
	TIM3_CAPTURECOMPARE_3,
  	TIM3_CAPTURECOMAPRE_4,
	TIM14_CAPTURECOMPARE_1_OVERCAPTURE,
	TIM14_CAPTURECOMPARE_1,
	TIM14_UPDATE,
	TIM16_CAPTURECOMPARE_1_OVERCAPTURE,
	TIM16_BREAK,
	TIM16_COMMUNICATION,
	TIM16_CAPTURECOMPARE_1,
	TIM16_UPDATE,
	TIM17_CAPTURECOMPARE_1_OVERCAPTURE,
	TIM17_BREAK,
	TIM17_COMMUNICATION,
	TIM17_CAPTURECOMPARE_1,
	TIM17_UPDATE,
	intTypeEND
}intrType_t;

static uint32_t intHandlerList[intTypeEND]={0};

static const uint8_t interruptTypeIndexList[intTypeEND] =
{
	TIM1_BRK_UP_TRG_COM_IRQn,
	TIM1_BRK_UP_TRG_COM_IRQn,
	TIM1_BRK_UP_TRG_COM_IRQn,
	TIM1_BRK_UP_TRG_COM_IRQn,
	TIM1_CC_IRQn,
	TIM1_CC_IRQn,
	TIM1_CC_IRQn,
	TIM1_CC_IRQn,
	TIM2_IRQn,
	TIM2_IRQn,
	TIM2_IRQn,
	TIM2_IRQn,
	TIM2_IRQn,
	TIM2_IRQn,
	TIM2_IRQn,
	TIM2_IRQn,
	TIM2_IRQn,
	TIM2_IRQn,
	TIM3_IRQn,
	TIM3_IRQn,
	TIM3_IRQn,
	TIM3_IRQn,
	TIM3_IRQn,
	TIM3_IRQn,
	TIM3_IRQn,
	TIM3_IRQn,
	TIM3_IRQn,
	TIM3_IRQn,
	TIM14_IRQn,
	TIM14_IRQn,
	TIM14_IRQn,
	TIM16_IRQn,
	TIM16_IRQn,
	TIM16_IRQn,
	TIM16_IRQn,
	TIM16_IRQn,
	TIM17_IRQn,
	TIM17_IRQn,
	TIM17_IRQn,
	TIM17_IRQn,
	TIM17_IRQn
};

#ifdef __cplusplus
}
#endif

#endif // _HWD_INTERRUPT_H_