From dc125b0d7882634bc49a17e7902d274e55478a0d Mon Sep 17 00:00:00 2001 From: key Date: Thu, 23 Sep 2021 18:00:30 +0200 Subject: [PATCH] somewhat working CMAKE --- bsl/cmakeLowLayer/CMakeLists.txt | 86 + bsl/cmakeLowLayer/Makefile | 4 +- bsl/cmakeLowLayer/cmakeBuild/CMakeCache.txt | 394 + .../CMakeFiles/3.13.4/CMakeASMCompiler.cmake | 17 + .../CMakeFiles/3.13.4/CMakeCCompiler.cmake | 73 + .../CMakeFiles/3.13.4/CMakeCXXCompiler.cmake | 76 + .../3.13.4/CMakeDetermineCompilerABI_C.bin | Bin 0 -> 16544 bytes .../3.13.4/CMakeDetermineCompilerABI_CXX.bin | Bin 0 -> 16560 bytes .../CMakeFiles/3.13.4/CMakeSystem.cmake | 15 + .../3.13.4/CompilerIdC/CMakeCCompilerId.c | 623 + .../CompilerIdCXX/CMakeCXXCompilerId.cpp | 602 + .../CMakeDirectoryInformation.cmake | 16 + .../cmakeBuild/CMakeFiles/CMakeOutput.log | 704 + .../cmakeBuild/CMakeFiles/Makefile.cmake | 50 + .../cmakeBuild/CMakeFiles/Makefile2 | 113 + .../CMakeFiles/TargetDirectories.txt | 3 + .../cmakeBuild/CMakeFiles/cmake.check_cache | 1 + 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bsl/makeLowLayer/cmakeLowLayer.ioc create mode 100644 bsl/makeLowLayer/startup_stm32f042x6.s diff --git a/bsl/cmakeLowLayer/CMakeLists.txt b/bsl/cmakeLowLayer/CMakeLists.txt new file mode 100644 index 0000000..2989c44 --- /dev/null +++ b/bsl/cmakeLowLayer/CMakeLists.txt @@ -0,0 +1,86 @@ +cmake_minimum_required(VERSION 3.5) + +project(refOvenTest) + +enable_language(C ASM) +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR arm) +set(CMAKE_CROSSCOMPILING TRUE) + + +set(CMAKE_C_COMPILER "/usr/bin/arm-none-eabi-gcc") +set(CMAKE_ASM_COMPILER "/usr/bin/arm-none-eabi-gcc") +set(CMAKE_OBJCOPY "usr/bin/arm-none-eabi-objcopy") + +set(EXECUTABLE ${PROJECT_NAME}.out) + +set(C_SOURCES + Src/main.c + Src/stm32f0xx_it.c + Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c + Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c + Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c + Src/system_stm32f0xx.c + Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c + Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c + Inc/main.h + Inc/stm32_assert.h + Inc/stm32f0xx_it.h + startup_stm32f042x6.s) + + + + +add_executable(${EXECUTABLE} ${C_SOURCES}) + +target_compile_options(${EXECUTABLE} PRIVATE + $<$:-x assembler-with-cpp ${ASM_FLAGS}> +) + +target_compile_options(${EXECUTABLE} PRIVATE + -mcpu=cortex-m0 + -mthumb + -Wall + -fdata-sections + -ffunction-sections + $<$:-O -g -gdwarf-2>) + +target_compile_definitions(${EXECUTABLE} PRIVATE + -DUSE_FULL_LL_DRIVER + -DSTM32F042x6 + -DHSE_VALUE=8000000 + -DHSE_STARTUP_TIMEOUT=100 + -DLSE_STARTUP_TIMEOUT=5000 + -DLSE_VALUE=32768 + -DHSI_VALUE=8000000 + -DLSI_VALUE=40000 + -DVDD_VALUE=3300 + -DPREFETCH_ENABLE=1 + -DINSTRUCTION_CACHE_ENABLE=0 + -DDATA_CACHE_ENABLE=0) + +target_include_directories(${EXECUTABLE} PRIVATE + Inc + Drivers/STM32F0xx_HAL_Driver/Inc + Drivers/CMSIS/Device/ST/STM32F0xx/Include + Drivers/CMSIS/Include) + +target_link_options(${EXECUTABLE} PRIVATE + -mcpu=cortex-m0 + -mthumb + -specs=nano.specs + -T${CMAKE_SOURCE_DIR}/STM32F042K6Tx_FLASH.ld + -lc + -lm + -lnosys + -Wl,-Map=${PROJECT_NAME}.map,--cref + -Wl,--gc-sections) + +add_custom_command(TARGET ${EXECUTABLE} + POST_BUILD + COMMAND arm-none-eabi-size ${EXECUTABLE}) + +add_custom_command(TARGET ${EXECUTABLE} + POST_BUILD + COMMAND arm-none-eabi-objcopy -O ihex ${EXECUTABLE} ${PROJECT_NAME}.hex + COMMAND arm-none-eabi-objcopy -O binary ${EXECUTABLE} ${PROJECT_NAME}.bin) diff --git a/bsl/cmakeLowLayer/Makefile b/bsl/cmakeLowLayer/Makefile index 7cde49b..37864a8 100644 --- a/bsl/cmakeLowLayer/Makefile +++ b/bsl/cmakeLowLayer/Makefile @@ -35,7 +35,7 @@ BUILD_DIR = build # source ###################################### # C sources -C_SOURCES = \ +C_SOURChS = \ Src/main.c \ Src/stm32f0xx_it.c \ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c \ @@ -83,7 +83,7 @@ CPU = -mcpu=cortex-m0 # mcu -MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) +MCU = $(CPU) -m-mthumbthumb $(FPU) $(FLOAT-ABI) # macros for gcc # AS defines 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DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__SUNPRO_C) +# define COMPILER_ID "SunPro" +# if __SUNPRO_C >= 0x5100 + /* __SUNPRO_C = 0xVRRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_C>>12) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_C>>4 & 0xFF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_C & 0xF) +# else + /* __SUNPRO_CC = 0xVRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_C>>8) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_C>>4 & 0xF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_C & 0xF) +# endif + +#elif defined(__HP_cc) +# define COMPILER_ID "HP" + /* __HP_cc = VVRRPP */ +# define COMPILER_VERSION_MAJOR DEC(__HP_cc/10000) +# define COMPILER_VERSION_MINOR DEC(__HP_cc/100 % 100) +# define COMPILER_VERSION_PATCH DEC(__HP_cc % 100) + +#elif defined(__DECC) +# define COMPILER_ID "Compaq" + /* __DECC_VER = VVRRTPPPP */ +# define COMPILER_VERSION_MAJOR DEC(__DECC_VER/10000000) +# define COMPILER_VERSION_MINOR DEC(__DECC_VER/100000 % 100) +# define COMPILER_VERSION_PATCH DEC(__DECC_VER % 10000) + +#elif defined(__IBMC__) && defined(__COMPILER_VER__) +# define COMPILER_ID "zOS" +# if defined(__ibmxl__) +# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__) +# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__) +# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__) +# else + /* __IBMC__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10) +# endif + + +#elif defined(__ibmxl__) || (defined(__IBMC__) && !defined(__COMPILER_VER__) && __IBMC__ >= 800) +# define COMPILER_ID "XL" +# if defined(__ibmxl__) +# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__) +# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__) +# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__) +# else + /* __IBMC__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10) +# endif + + +#elif defined(__IBMC__) && !defined(__COMPILER_VER__) && __IBMC__ < 800 +# define COMPILER_ID "VisualAge" +# if defined(__ibmxl__) +# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__) +# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__) +# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__) +# else + /* __IBMC__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10) +# endif + + +#elif defined(__PGI) +# define COMPILER_ID "PGI" +# define COMPILER_VERSION_MAJOR DEC(__PGIC__) +# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__) +# if defined(__PGIC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__) +# endif + +#elif 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COMPILER_VERSION_PATCH HEX(__VISUALDSPVERSION__>>8 & 0xFF) +#endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# define COMPILER_ID "IAR" +# if defined(__VER__) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000) +# define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000) +# define COMPILER_VERSION_PATCH DEC((__VER__) % 1000) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# endif + +#elif defined(__ARMCC_VERSION) +# define COMPILER_ID "ARMCC" +#if __ARMCC_VERSION >= 1000000 + /* __ARMCC_VERSION = VRRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#else + /* __ARMCC_VERSION = VRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#endif + + +#elif defined(__SDCC_VERSION_MAJOR) || defined(SDCC) +# define COMPILER_ID "SDCC" +# if defined(__SDCC_VERSION_MAJOR) +# define COMPILER_VERSION_MAJOR DEC(__SDCC_VERSION_MAJOR) +# define COMPILER_VERSION_MINOR DEC(__SDCC_VERSION_MINOR) +# define COMPILER_VERSION_PATCH DEC(__SDCC_VERSION_PATCH) +# else + /* SDCC = VRP */ +# define COMPILER_VERSION_MAJOR DEC(SDCC/100) +# define COMPILER_VERSION_MINOR DEC(SDCC/10 % 10) +# define COMPILER_VERSION_PATCH DEC(SDCC % 10) +# endif + +#elif defined(_SGI_COMPILER_VERSION) || defined(_COMPILER_VERSION) +# define COMPILER_ID "MIPSpro" +# if defined(_SGI_COMPILER_VERSION) + /* _SGI_COMPILER_VERSION = VRP */ +# define COMPILER_VERSION_MAJOR DEC(_SGI_COMPILER_VERSION/100) +# define COMPILER_VERSION_MINOR DEC(_SGI_COMPILER_VERSION/10 % 10) +# define COMPILER_VERSION_PATCH DEC(_SGI_COMPILER_VERSION % 10) +# else + /* _COMPILER_VERSION = VRP */ +# define COMPILER_VERSION_MAJOR DEC(_COMPILER_VERSION/100) +# define COMPILER_VERSION_MINOR DEC(_COMPILER_VERSION/10 % 10) +# define COMPILER_VERSION_PATCH DEC(_COMPILER_VERSION % 10) +# endif + + +/* These compilers are either not known or too old to define an + identification macro. Try to identify the platform and guess that + it is the native compiler. */ +#elif defined(__sgi) +# define COMPILER_ID "MIPSpro" + +#elif defined(__hpux) || defined(__hpua) +# define COMPILER_ID "HP" + +#else /* unknown compiler */ +# define COMPILER_ID "" +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]"; +#ifdef SIMULATE_ID +char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]"; +#endif + +#ifdef __QNXNTO__ +char const* qnxnto = "INFO" ":" "qnxnto[]"; +#endif + +#if defined(__CRAYXE) || defined(__CRAYXC) +char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]"; +#endif + +#define STRINGIFY_HELPER(X) #X +#define STRINGIFY(X) STRINGIFY_HELPER(X) + +/* Identify known platforms by name. */ +#if defined(__linux) || defined(__linux__) || defined(linux) +# define PLATFORM_ID "Linux" + +#elif defined(__CYGWIN__) +# define PLATFORM_ID "Cygwin" + +#elif defined(__MINGW32__) +# define PLATFORM_ID "MinGW" + +#elif defined(__APPLE__) +# define PLATFORM_ID "Darwin" + +#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32) +# define PLATFORM_ID "Windows" + +#elif defined(__FreeBSD__) || defined(__FreeBSD) +# define PLATFORM_ID "FreeBSD" + +#elif defined(__NetBSD__) || defined(__NetBSD) +# define PLATFORM_ID "NetBSD" + +#elif defined(__OpenBSD__) || defined(__OPENBSD) +# define PLATFORM_ID "OpenBSD" + +#elif defined(__sun) || defined(sun) +# define PLATFORM_ID "SunOS" + +#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__) +# define PLATFORM_ID "AIX" + +#elif defined(__sgi) || defined(__sgi__) || defined(_SGI) +# define PLATFORM_ID "IRIX" + +#elif defined(__hpux) || defined(__hpux__) +# define PLATFORM_ID "HP-UX" + +#elif defined(__HAIKU__) +# define PLATFORM_ID "Haiku" + +#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS) +# define PLATFORM_ID "BeOS" + +#elif defined(__QNX__) || defined(__QNXNTO__) +# define PLATFORM_ID "QNX" + +#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__) +# define PLATFORM_ID "Tru64" + +#elif defined(__riscos) || defined(__riscos__) +# define PLATFORM_ID "RISCos" + +#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__) +# define PLATFORM_ID "SINIX" + +#elif defined(__UNIX_SV__) +# define PLATFORM_ID "UNIX_SV" + +#elif defined(__bsdos__) +# define PLATFORM_ID "BSDOS" + +#elif defined(_MPRAS) || defined(MPRAS) +# define PLATFORM_ID "MP-RAS" + +#elif defined(__osf) || defined(__osf__) +# define PLATFORM_ID "OSF1" + +#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv) +# define PLATFORM_ID "SCO_SV" + +#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX) +# define PLATFORM_ID "ULTRIX" + +#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX) +# define PLATFORM_ID "Xenix" + +#elif defined(__WATCOMC__) +# if defined(__LINUX__) +# define PLATFORM_ID "Linux" + +# elif defined(__DOS__) +# define PLATFORM_ID "DOS" + +# elif defined(__OS2__) +# define PLATFORM_ID "OS2" + +# elif defined(__WINDOWS__) +# define PLATFORM_ID "Windows3x" + +# else /* unknown platform */ +# define PLATFORM_ID +# endif + +#else /* unknown platform */ +# define PLATFORM_ID + +#endif + +/* For windows compilers MSVC and Intel we can determine + the architecture of the compiler being used. This is because + the compilers do not have flags that can change the architecture, + but rather depend on which compiler is being used +*/ +#if defined(_WIN32) && defined(_MSC_VER) +# if defined(_M_IA64) +# define ARCHITECTURE_ID "IA64" + +# elif defined(_M_X64) || defined(_M_AMD64) +# define ARCHITECTURE_ID "x64" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# elif defined(_M_ARM64) +# define ARCHITECTURE_ID "ARM64" + +# elif defined(_M_ARM) +# if _M_ARM == 4 +# define ARCHITECTURE_ID "ARMV4I" +# elif _M_ARM == 5 +# define ARCHITECTURE_ID "ARMV5I" +# else +# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM) +# endif + +# elif defined(_M_MIPS) +# define ARCHITECTURE_ID "MIPS" + +# elif defined(_M_SH) +# define ARCHITECTURE_ID "SHx" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__WATCOMC__) +# if defined(_M_I86) +# define ARCHITECTURE_ID "I86" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# if defined(__ICCARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__ICCAVR__) +# define ARCHITECTURE_ID "AVR" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif +#else +# define ARCHITECTURE_ID +#endif + +/* Convert integer to decimal digit literals. */ +#define DEC(n) \ + ('0' + (((n) / 10000000)%10)), \ + ('0' + (((n) / 1000000)%10)), \ + ('0' + (((n) / 100000)%10)), \ + ('0' + (((n) / 10000)%10)), \ + ('0' + (((n) / 1000)%10)), \ + ('0' + (((n) / 100)%10)), \ + ('0' + (((n) / 10)%10)), \ + ('0' + ((n) % 10)) + +/* Convert integer to hex digit literals. */ +#define HEX(n) \ + ('0' + ((n)>>28 & 0xF)), \ + ('0' + ((n)>>24 & 0xF)), \ + ('0' + ((n)>>20 & 0xF)), \ + ('0' + ((n)>>16 & 0xF)), \ + ('0' + ((n)>>12 & 0xF)), \ + ('0' + ((n)>>8 & 0xF)), \ + ('0' + ((n)>>4 & 0xF)), \ + ('0' + ((n) & 0xF)) + +/* Construct a string literal encoding the version number components. */ +#ifdef COMPILER_VERSION_MAJOR +char const info_version[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[', + COMPILER_VERSION_MAJOR, +# ifdef COMPILER_VERSION_MINOR + '.', COMPILER_VERSION_MINOR, +# ifdef COMPILER_VERSION_PATCH + '.', COMPILER_VERSION_PATCH, +# ifdef COMPILER_VERSION_TWEAK + '.', COMPILER_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct a string literal encoding the internal version number. */ +#ifdef COMPILER_VERSION_INTERNAL +char const info_version_internal[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_', + 'i','n','t','e','r','n','a','l','[', + COMPILER_VERSION_INTERNAL,']','\0'}; +#endif + +/* Construct a string literal encoding the version number components. */ +#ifdef SIMULATE_VERSION_MAJOR +char const info_simulate_version[] = { + 'I', 'N', 'F', 'O', ':', + 's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[', + SIMULATE_VERSION_MAJOR, +# ifdef SIMULATE_VERSION_MINOR + '.', SIMULATE_VERSION_MINOR, +# ifdef SIMULATE_VERSION_PATCH + '.', SIMULATE_VERSION_PATCH, +# ifdef SIMULATE_VERSION_TWEAK + '.', SIMULATE_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_platform = "INFO" ":" "platform[" PLATFORM_ID "]"; +char const* info_arch = "INFO" ":" "arch[" ARCHITECTURE_ID "]"; + + + + +#if !defined(__STDC__) +# if (defined(_MSC_VER) && !defined(__clang__)) \ + || (defined(__ibmxl__) || defined(__IBMC__)) +# define C_DIALECT "90" +# else +# define C_DIALECT +# endif +#elif __STDC_VERSION__ >= 201000L +# define C_DIALECT "11" +#elif __STDC_VERSION__ >= 199901L +# define C_DIALECT "99" +#else +# define C_DIALECT "90" +#endif +const char* info_language_dialect_default = + "INFO" ":" "dialect_default[" C_DIALECT "]"; + +/*--------------------------------------------------------------------------*/ + +#ifdef ID_VOID_MAIN +void main() {} +#else +# if defined(__CLASSIC_C__) +int main(argc, argv) int argc; char *argv[]; +# else +int main(int argc, char* argv[]) +# endif +{ + int require = 0; + require += info_compiler[argc]; + require += info_platform[argc]; + require += info_arch[argc]; +#ifdef COMPILER_VERSION_MAJOR + require += info_version[argc]; +#endif +#ifdef COMPILER_VERSION_INTERNAL + require += info_version_internal[argc]; +#endif +#ifdef SIMULATE_ID + require += info_simulate[argc]; +#endif +#ifdef SIMULATE_VERSION_MAJOR + require += info_simulate_version[argc]; +#endif +#if defined(__CRAYXE) || defined(__CRAYXC) + require += info_cray[argc]; +#endif + require += info_language_dialect_default[argc]; + (void)argv; + return require; +} +#endif diff --git a/bsl/cmakeLowLayer/cmakeBuild/CMakeFiles/3.13.4/CompilerIdCXX/CMakeCXXCompilerId.cpp b/bsl/cmakeLowLayer/cmakeBuild/CMakeFiles/3.13.4/CompilerIdCXX/CMakeCXXCompilerId.cpp new file mode 100644 index 0000000..b728b63 --- /dev/null +++ b/bsl/cmakeLowLayer/cmakeBuild/CMakeFiles/3.13.4/CompilerIdCXX/CMakeCXXCompilerId.cpp @@ -0,0 +1,602 @@ +/* This source file must have a .cpp extension so that all C++ compilers + recognize the extension without flags. Borland does not know .cxx for + example. */ +#ifndef __cplusplus +# error "A C compiler has been selected for C++." +#endif + + +/* Version number components: V=Version, R=Revision, P=Patch + Version date components: YYYY=Year, MM=Month, DD=Day */ + +#if defined(__COMO__) +# define COMPILER_ID "Comeau" + /* __COMO_VERSION__ = VRR */ +# define COMPILER_VERSION_MAJOR DEC(__COMO_VERSION__ / 100) +# define COMPILER_VERSION_MINOR DEC(__COMO_VERSION__ % 100) + +#elif defined(__INTEL_COMPILER) || defined(__ICC) +# define COMPILER_ID "Intel" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif + /* __INTEL_COMPILER = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER/100) +# define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER/10 % 10) +# if defined(__INTEL_COMPILER_UPDATE) +# define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER_UPDATE) +# else +# define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER % 10) +# endif +# if defined(__INTEL_COMPILER_BUILD_DATE) + /* __INTEL_COMPILER_BUILD_DATE = YYYYMMDD */ +# define COMPILER_VERSION_TWEAK DEC(__INTEL_COMPILER_BUILD_DATE) +# endif +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif + +#elif defined(__PATHCC__) +# define COMPILER_ID "PathScale" +# define COMPILER_VERSION_MAJOR DEC(__PATHCC__) +# define COMPILER_VERSION_MINOR DEC(__PATHCC_MINOR__) +# if defined(__PATHCC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PATHCC_PATCHLEVEL__) +# endif + +#elif defined(__BORLANDC__) && defined(__CODEGEARC_VERSION__) +# define COMPILER_ID "Embarcadero" +# define COMPILER_VERSION_MAJOR HEX(__CODEGEARC_VERSION__>>24 & 0x00FF) +# define COMPILER_VERSION_MINOR HEX(__CODEGEARC_VERSION__>>16 & 0x00FF) +# define COMPILER_VERSION_PATCH DEC(__CODEGEARC_VERSION__ & 0xFFFF) + +#elif defined(__BORLANDC__) +# define COMPILER_ID "Borland" + /* __BORLANDC__ = 0xVRR */ +# define COMPILER_VERSION_MAJOR HEX(__BORLANDC__>>8) +# define COMPILER_VERSION_MINOR HEX(__BORLANDC__ & 0xFF) + +#elif defined(__WATCOMC__) && __WATCOMC__ < 1200 +# define COMPILER_ID "Watcom" + /* __WATCOMC__ = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(__WATCOMC__ / 100) +# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10) +# if (__WATCOMC__ % 10) > 0 +# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__WATCOMC__) +# define COMPILER_ID "OpenWatcom" + /* __WATCOMC__ = VVRP + 1100 */ +# define COMPILER_VERSION_MAJOR DEC((__WATCOMC__ - 1100) / 100) +# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10) +# if (__WATCOMC__ % 10) > 0 +# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__SUNPRO_CC) +# define COMPILER_ID "SunPro" +# if __SUNPRO_CC >= 0x5100 + /* __SUNPRO_CC = 0xVRRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_CC>>12) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_CC>>4 & 0xFF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_CC & 0xF) +# else + /* __SUNPRO_CC = 0xVRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_CC>>8) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_CC>>4 & 0xF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_CC & 0xF) +# endif + +#elif defined(__HP_aCC) +# define COMPILER_ID "HP" + /* __HP_aCC = VVRRPP */ +# define COMPILER_VERSION_MAJOR DEC(__HP_aCC/10000) +# define COMPILER_VERSION_MINOR DEC(__HP_aCC/100 % 100) +# define COMPILER_VERSION_PATCH DEC(__HP_aCC % 100) + +#elif defined(__DECCXX) +# define COMPILER_ID "Compaq" + /* __DECCXX_VER = VVRRTPPPP */ +# define COMPILER_VERSION_MAJOR DEC(__DECCXX_VER/10000000) +# define COMPILER_VERSION_MINOR DEC(__DECCXX_VER/100000 % 100) +# define COMPILER_VERSION_PATCH DEC(__DECCXX_VER % 10000) + +#elif defined(__IBMCPP__) && defined(__COMPILER_VER__) +# define COMPILER_ID "zOS" +# if defined(__ibmxl__) +# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__) +# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__) +# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__) +# else + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) +# endif + + +#elif defined(__ibmxl__) || (defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ >= 800) +# define COMPILER_ID "XL" +# if defined(__ibmxl__) +# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__) +# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__) +# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__) +# else + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) +# endif + + +#elif defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ < 800 +# define COMPILER_ID "VisualAge" +# if defined(__ibmxl__) +# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__) +# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__) +# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__) +# else + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) +# endif + + +#elif defined(__PGI) +# define COMPILER_ID "PGI" +# define COMPILER_VERSION_MAJOR DEC(__PGIC__) +# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__) +# if defined(__PGIC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__) +# endif + +#elif defined(_CRAYC) +# define COMPILER_ID "Cray" +# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR) +# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR) + +#elif defined(__TI_COMPILER_VERSION__) +# define COMPILER_ID "TI" + /* __TI_COMPILER_VERSION__ = VVVRRRPPP */ +# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000) +# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000 % 1000) +# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__ % 1000) + +#elif defined(__FUJITSU) || defined(__FCC_VERSION) || defined(__fcc_version) +# define COMPILER_ID "Fujitsu" + +#elif defined(__SCO_VERSION__) +# define COMPILER_ID "SCO" + +#elif defined(__clang__) && defined(__apple_build_version__) +# define COMPILER_ID "AppleClang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif +# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__) + +#elif defined(__clang__) +# define COMPILER_ID "Clang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif + +#elif defined(__GNUC__) || defined(__GNUG__) +# define COMPILER_ID "GNU" +# if defined(__GNUC__) +# define COMPILER_VERSION_MAJOR DEC(__GNUC__) +# else +# define COMPILER_VERSION_MAJOR DEC(__GNUG__) +# endif +# if defined(__GNUC_MINOR__) +# define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__) +# endif +# if defined(__GNUC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif + +#elif defined(_MSC_VER) +# define COMPILER_ID "MSVC" + /* _MSC_VER = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100) +# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100) +# if defined(_MSC_FULL_VER) +# if _MSC_VER >= 1400 + /* _MSC_FULL_VER = VVRRPPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000) +# else + /* _MSC_FULL_VER = VVRRPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000) +# endif +# endif +# if defined(_MSC_BUILD) +# define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD) +# endif + +#elif defined(__VISUALDSPVERSION__) || defined(__ADSPBLACKFIN__) || defined(__ADSPTS__) || defined(__ADSP21000__) +# define COMPILER_ID "ADSP" +#if defined(__VISUALDSPVERSION__) + /* __VISUALDSPVERSION__ = 0xVVRRPP00 */ +# define COMPILER_VERSION_MAJOR HEX(__VISUALDSPVERSION__>>24) +# define COMPILER_VERSION_MINOR HEX(__VISUALDSPVERSION__>>16 & 0xFF) +# define COMPILER_VERSION_PATCH HEX(__VISUALDSPVERSION__>>8 & 0xFF) +#endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# define COMPILER_ID "IAR" +# if defined(__VER__) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000) +# define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000) +# define COMPILER_VERSION_PATCH DEC((__VER__) % 1000) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# endif + +#elif defined(__ARMCC_VERSION) +# define COMPILER_ID "ARMCC" +#if __ARMCC_VERSION >= 1000000 + /* __ARMCC_VERSION = VRRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#else + /* __ARMCC_VERSION = VRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#endif + + +#elif defined(_SGI_COMPILER_VERSION) || defined(_COMPILER_VERSION) +# define COMPILER_ID "MIPSpro" +# if defined(_SGI_COMPILER_VERSION) + /* _SGI_COMPILER_VERSION = VRP */ +# define COMPILER_VERSION_MAJOR DEC(_SGI_COMPILER_VERSION/100) +# define COMPILER_VERSION_MINOR DEC(_SGI_COMPILER_VERSION/10 % 10) +# define COMPILER_VERSION_PATCH DEC(_SGI_COMPILER_VERSION % 10) +# else + /* _COMPILER_VERSION = VRP */ +# define COMPILER_VERSION_MAJOR DEC(_COMPILER_VERSION/100) +# define COMPILER_VERSION_MINOR DEC(_COMPILER_VERSION/10 % 10) +# define COMPILER_VERSION_PATCH DEC(_COMPILER_VERSION % 10) +# endif + + +/* These compilers are either not known or too old to define an + identification macro. Try to identify the platform and guess that + it is the native compiler. */ +#elif defined(__sgi) +# define COMPILER_ID "MIPSpro" + +#elif defined(__hpux) || defined(__hpua) +# define COMPILER_ID "HP" + +#else /* unknown compiler */ +# define COMPILER_ID "" +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]"; +#ifdef SIMULATE_ID +char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]"; +#endif + +#ifdef __QNXNTO__ +char const* qnxnto = "INFO" ":" "qnxnto[]"; +#endif + +#if defined(__CRAYXE) || defined(__CRAYXC) +char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]"; +#endif + +#define STRINGIFY_HELPER(X) #X +#define STRINGIFY(X) STRINGIFY_HELPER(X) + +/* Identify known platforms by name. */ +#if defined(__linux) || defined(__linux__) || defined(linux) +# define PLATFORM_ID "Linux" + +#elif defined(__CYGWIN__) +# define PLATFORM_ID "Cygwin" + +#elif defined(__MINGW32__) +# define PLATFORM_ID "MinGW" + +#elif defined(__APPLE__) +# define PLATFORM_ID "Darwin" + +#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32) +# define PLATFORM_ID "Windows" + +#elif defined(__FreeBSD__) || defined(__FreeBSD) +# define PLATFORM_ID "FreeBSD" + +#elif defined(__NetBSD__) || defined(__NetBSD) +# define PLATFORM_ID "NetBSD" + +#elif defined(__OpenBSD__) || defined(__OPENBSD) +# define PLATFORM_ID "OpenBSD" + +#elif defined(__sun) || defined(sun) +# define PLATFORM_ID "SunOS" + +#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__) +# define PLATFORM_ID "AIX" + +#elif defined(__sgi) || defined(__sgi__) || defined(_SGI) +# define PLATFORM_ID "IRIX" + +#elif defined(__hpux) || defined(__hpux__) +# define PLATFORM_ID "HP-UX" + +#elif defined(__HAIKU__) +# define PLATFORM_ID "Haiku" + +#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS) +# define PLATFORM_ID "BeOS" + +#elif defined(__QNX__) || defined(__QNXNTO__) +# define PLATFORM_ID "QNX" + +#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__) +# define PLATFORM_ID "Tru64" + +#elif defined(__riscos) || defined(__riscos__) +# define PLATFORM_ID "RISCos" + +#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__) +# define PLATFORM_ID "SINIX" + +#elif defined(__UNIX_SV__) +# define PLATFORM_ID "UNIX_SV" + +#elif defined(__bsdos__) +# define PLATFORM_ID "BSDOS" + +#elif defined(_MPRAS) || defined(MPRAS) +# define PLATFORM_ID "MP-RAS" + +#elif defined(__osf) || defined(__osf__) +# define PLATFORM_ID "OSF1" + +#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv) +# define PLATFORM_ID "SCO_SV" + +#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX) +# define PLATFORM_ID "ULTRIX" + +#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX) +# define PLATFORM_ID "Xenix" + +#elif defined(__WATCOMC__) +# if defined(__LINUX__) +# define PLATFORM_ID "Linux" + +# elif defined(__DOS__) +# define PLATFORM_ID "DOS" + +# elif defined(__OS2__) +# define PLATFORM_ID "OS2" + +# elif defined(__WINDOWS__) +# define PLATFORM_ID "Windows3x" + +# else /* unknown platform */ +# define PLATFORM_ID +# endif + +#else /* unknown platform */ +# define PLATFORM_ID + +#endif + +/* For windows compilers MSVC and Intel we can determine + the architecture of the compiler being used. This is because + the compilers do not have flags that can change the architecture, + but rather depend on which compiler is being used +*/ +#if defined(_WIN32) && defined(_MSC_VER) +# if defined(_M_IA64) +# define ARCHITECTURE_ID "IA64" + +# elif defined(_M_X64) || defined(_M_AMD64) +# define ARCHITECTURE_ID "x64" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# elif defined(_M_ARM64) +# define ARCHITECTURE_ID "ARM64" + +# elif defined(_M_ARM) +# if _M_ARM == 4 +# define ARCHITECTURE_ID "ARMV4I" +# elif _M_ARM == 5 +# define ARCHITECTURE_ID "ARMV5I" +# else +# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM) +# endif + +# elif defined(_M_MIPS) +# define ARCHITECTURE_ID "MIPS" + +# elif defined(_M_SH) +# define ARCHITECTURE_ID "SHx" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__WATCOMC__) +# if defined(_M_I86) +# define ARCHITECTURE_ID "I86" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# if defined(__ICCARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__ICCAVR__) +# define ARCHITECTURE_ID "AVR" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif +#else +# define ARCHITECTURE_ID +#endif + +/* Convert integer to decimal digit literals. */ +#define DEC(n) \ + ('0' + (((n) / 10000000)%10)), \ + ('0' + (((n) / 1000000)%10)), \ + ('0' + (((n) / 100000)%10)), \ + ('0' + (((n) / 10000)%10)), \ + ('0' + (((n) / 1000)%10)), \ + ('0' + (((n) / 100)%10)), \ + ('0' + (((n) / 10)%10)), \ + ('0' + ((n) % 10)) + +/* Convert integer to hex digit literals. */ +#define HEX(n) \ + ('0' + ((n)>>28 & 0xF)), \ + ('0' + ((n)>>24 & 0xF)), \ + ('0' + ((n)>>20 & 0xF)), \ + ('0' + ((n)>>16 & 0xF)), \ + ('0' + ((n)>>12 & 0xF)), \ + ('0' + ((n)>>8 & 0xF)), \ + ('0' + ((n)>>4 & 0xF)), \ + ('0' + ((n) & 0xF)) + +/* Construct a string literal encoding the version number components. */ +#ifdef COMPILER_VERSION_MAJOR +char const info_version[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[', + COMPILER_VERSION_MAJOR, +# ifdef COMPILER_VERSION_MINOR + '.', COMPILER_VERSION_MINOR, +# ifdef COMPILER_VERSION_PATCH + '.', COMPILER_VERSION_PATCH, +# ifdef COMPILER_VERSION_TWEAK + '.', COMPILER_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct a string literal encoding the internal version number. */ +#ifdef COMPILER_VERSION_INTERNAL +char const info_version_internal[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_', + 'i','n','t','e','r','n','a','l','[', + COMPILER_VERSION_INTERNAL,']','\0'}; +#endif + +/* Construct a string literal encoding the version number components. */ +#ifdef SIMULATE_VERSION_MAJOR +char const info_simulate_version[] = { + 'I', 'N', 'F', 'O', ':', + 's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[', + SIMULATE_VERSION_MAJOR, +# ifdef SIMULATE_VERSION_MINOR + '.', SIMULATE_VERSION_MINOR, +# ifdef SIMULATE_VERSION_PATCH + '.', SIMULATE_VERSION_PATCH, +# ifdef SIMULATE_VERSION_TWEAK + '.', SIMULATE_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. 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"install_manifest_${CMAKE_INSTALL_COMPONENT}.txt") +else() + set(CMAKE_INSTALL_MANIFEST "install_manifest.txt") +endif() + +string(REPLACE ";" "\n" CMAKE_INSTALL_MANIFEST_CONTENT + "${CMAKE_INSTALL_MANIFEST_FILES}") +file(WRITE "/home/key/Git/KED/bsl/cmakeLowLayer/cmakeBuild/${CMAKE_INSTALL_MANIFEST}" + "${CMAKE_INSTALL_MANIFEST_CONTENT}") diff --git a/bsl/cmakeLowLayer/cmakeBuild/copare.txt b/bsl/cmakeLowLayer/cmakeBuild/copare.txt new file mode 100644 index 0000000..81edb62 --- /dev/null +++ b/bsl/cmakeLowLayer/cmakeBuild/copare.txt @@ -0,0 +1,2 @@ +arm-none-eabi-gcc -c -mcpu=cortex-m0 -mthumb -DUSE_FULL_LL_DRIVER -DSTM32F042x6 -DHSE_VALUE=8000000 -DHSE_STARTUP_TIMEOUT=100 -DLSE_STARTUP_TIMEOUT=5000 -DLSE_VALUE=32768 -DHSI_VALUE=8000000 -DLSI_VALUE=40000 -DVDD_VALUE=3300 -DPREFETCH_ENABLE=1 -DINSTRUCTION_CACHE_ENABLE=0 -DDATA_CACHE_ENABLE=0 -IInc -IDrivers/STM32F0xx_HAL_Driver/Inc -IDrivers/CMSIS/Device/ST/STM32F0xx/Include -IDrivers/CMSIS/Include -Og -Wall -fdata-sections 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+CDefines=USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;HSI_VALUE:8000000;LSI_VALUE:40000;VDD_VALUE:3300;PREFETCH_ENABLE:1;INSTRUCTION_CACHE_ENABLE:0;DATA_CACHE_ENABLE:0;STM32F042x6;USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;HSI_VALUE:8000000;LSI_VALUE:40000;VDD_VALUE:3300;PREFETCH_ENABLE:1;INSTRUCTION_CACHE_ENABLE:0;DATA_CACHE_ENABLE:0; + +[PreviousGenFiles] +HeaderPath=C:/keyterm/stm/stm32f042/cmakeLowLayer/Inc +HeaderFiles=stm32f0xx_it.h;stm32_assert.h;main.h; +SourcePath=C:/keyterm/stm/stm32f042/cmakeLowLayer/Src +SourceFiles=stm32f0xx_it.c;main.c; + diff --git a/bsl/makeLowLayer/CMakeLists.txt b/bsl/makeLowLayer/CMakeLists.txt new file mode 100644 index 0000000..d9cecc0 --- /dev/null +++ b/bsl/makeLowLayer/CMakeLists.txt @@ -0,0 +1,7 @@ +cmake_minimum_required(VERSION 3.5) + +project(refOvenTest) + +add_subdirectory(Src) + + diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h b/bsl/makeLowLayer/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h new file mode 100644 index 0000000..23e125c --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h @@ -0,0 +1,10677 @@ +/** + ****************************************************************************** + * @file stm32f042x6.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F0xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f042x6 + * @{ + */ + +#ifndef __STM32F042x6_H +#define __STM32F042x6_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M0 Processor and Core Peripherals + */ +#define __CM0_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ +#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F0xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** STM32F0 specific Interrupt Numbers ******************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupt through EXTI Lines 16 and 31 */ + RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */ + TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */ + ADC1_IRQn = 12, /*!< ADC1 Interrupt */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ + USART2_IRQn = 28, /*!< USART2 global Interrupt */ + CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */ + USB_IRQn = 31 /*!< USB global Interrupt & EXTI Line18 Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_stm32f0xx.h" /* STM32F0xx System Header */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +}CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +}CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +}CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[14]; /*!< CAN Filter Register, Address offset: 0x240-0x2AC */ +}CAN_TypeDef; + +/** + * @brief HDMI-CEC + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +}CRS_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx + * @{ + */ + +#ifndef __STM32F0xx_H +#define __STM32F0xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F0) +#define STM32F0 +#endif /* STM32F0 */ + +/** Uncomment the line below according to the target STM32 device used in your application. + * stm32f0xxxx.h file contains: + * - All the peripheral register's definitions, bits definitions and memory mapping for STM32F0xxxx devices + * - IRQ channel definition + * - Peripheral memory mapping and physical registers address definition + * - Peripheral pointer declaration and driver header file inclusion + * - Product miscellaneous configuration: assert macros… + * Note: These CMSIS drivers (stm32f0xxxx.h) are always supporting features of the sub-family’s superset. + */ + +#if !defined (STM32F030x6) && !defined (STM32F030x8) && \ + !defined (STM32F031x6) && !defined (STM32F038xx) && \ + !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \ + !defined (STM32F051x8) && !defined (STM32F058xx) && \ + !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \ + !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC) + /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */ + /* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */ + /* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F048xx */ /*!< STM32F048xx Devices (STM32F048xx microcontrollers where the Flash memory is 32 Kbytes) */ + /* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */ + /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */ + /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */ + /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */ + /* #define STM32F091xC */ /*!< STM32F091xB, STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory ranges between 128 and 256 Kbytes) */ + /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */ +#endif +/* Legacy aliases */ +#if defined (STM32F048x6) + #define STM32F048xx +#endif /* STM32F048x6 */ + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.3.6 + */ +#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x06) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ + |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ + |(__STM32F0_DEVICE_VERSION_SUB2 << 8 )\ + |(__STM32F0_DEVICE_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F030x6) + #include "stm32f030x6.h" +#elif defined(STM32F030x8) + #include "stm32f030x8.h" +#elif defined(STM32F031x6) + #include "stm32f031x6.h" +#elif defined(STM32F038xx) + #include "stm32f038xx.h" +#elif defined(STM32F042x6) + #include "stm32f042x6.h" +#elif defined(STM32F048xx) + #include "stm32f048xx.h" +#elif defined(STM32F051x8) + #include "stm32f051x8.h" +#elif defined(STM32F058xx) + #include "stm32f058xx.h" +#elif defined(STM32F070x6) + #include "stm32f070x6.h" +#elif defined(STM32F070xB) + #include "stm32f070xb.h" +#elif defined(STM32F071xB) + #include "stm32f071xb.h" +#elif defined(STM32F072xB) + #include "stm32f072xb.h" +#elif defined(STM32F078xx) + #include "stm32f078xx.h" +#elif defined(STM32F091xC) + #include "stm32f091xc.h" +#elif defined(STM32F098xx) + #include "stm32f098xx.h" +#elif defined(STM32F030xC) + #include "stm32f030xc.h" +#else + #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0U, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0U, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0U, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/* Use of interrupt control for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + SET_BIT((REG), (BIT)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + CLEAR_BIT((REG), (BIT)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \ + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \ + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f0xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F0xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h b/bsl/makeLowLayer/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h new file mode 100644 index 0000000..3b71cfe --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h @@ -0,0 +1,105 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F0XX_H +#define __SYSTEM_STM32F0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F0xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 3) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) by calling HAL API function HAL_RCC_ClockConfig() + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F0XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_armcc.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000..4d9d064 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,865 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_armclang.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000..162a400 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1869 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_compiler.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000..94212eb --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_gcc.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..2d9db15 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_iccarm.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000..11c4af0 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 19. June 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_version.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000..660f612 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/core_armv8mbl.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000..251e4ed --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1918 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/core_armv8mml.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000..3a3148e --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2927 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm0.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..f929bba --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,949 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm0plus.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..424011a --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1083 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm1.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000..0ed678e --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,976 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 23. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm23.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000..acbc5df --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,1993 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm3.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..74bff64 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1941 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm33.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000..6cd2db7 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,3002 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm4.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..7d56873 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm7.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..a14dc62 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2671 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/core_sc000.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..9b67c92 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1022 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/core_sc300.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..3e8a471 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1915 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/mpu_armv7.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000..0142203 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/mpu_armv8.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000..62571da --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsl/makeLowLayer/Drivers/CMSIS/Include/tz_context.h b/bsl/makeLowLayer/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h new file mode 100644 index 0000000..0468a19 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h @@ -0,0 +1,845 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_BUS_H +#define __STM32F0xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN +#if defined(DMA2) +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN +#endif /*DMA2*/ +#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN +#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN +#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN +#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN +#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN +#if defined(GPIOD) +#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN +#endif /*GPIOD*/ +#if defined(GPIOE) +#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN +#endif /*GPIOE*/ +#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN +#if defined(TSC) +#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN +#endif /*TSC*/ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#if defined(TIM2) +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN +#endif /*TIM2*/ +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN +#if defined(TIM6) +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN +#endif /*TIM6*/ +#if defined(TIM7) +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN +#endif /*TIM7*/ +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN +#if defined(SPI2) +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN +#endif /*SPI2*/ +#if defined(USART2) +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN +#endif /* USART2 */ +#if defined(USART3) +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN +#endif /* USART3 */ +#if defined(USART4) +#define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN +#endif /* USART4 */ +#if defined(USART5) +#define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN +#endif /* USART5 */ +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN +#if defined(I2C2) +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN +#endif /*I2C2*/ +#if defined(USB) +#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN +#endif /* USB */ +#if defined(CAN) +#define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN +#endif /*CAN*/ +#if defined(CRS) +#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN +#endif /*CRS*/ +#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN +#if defined(DAC) +#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN +#endif /*DAC*/ +#if defined(CEC) +#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN +#endif /*CEC*/ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + * @{ + */ +#define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN +#define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN +#if defined(USART8) +#define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN +#endif /*USART8*/ +#if defined(USART7) +#define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN +#endif /*USART7*/ +#if defined(USART6) +#define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN +#endif /*USART6*/ +#define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN +#if defined(TIM15) +#define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN +#endif /*TIM15*/ +#define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n + * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + * AHBENR TSCEN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHBENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n + * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + * AHBENR TSCEN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock (available in register 1). + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n + * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + * APB1ENR CECEN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not (available in register 1). + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB1 peripherals clock (available in register 1). + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n + * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + * APB1ENR CECEN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset (available in register 1). + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset (available in register 1). + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock (available in register 2). + * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_EnableClock\n + * APB2ENR ADC1EN LL_APB1_GRP2_EnableClock\n + * APB2ENR USART8EN LL_APB1_GRP2_EnableClock\n + * APB2ENR USART7EN LL_APB1_GRP2_EnableClock\n + * APB2ENR USART6EN LL_APB1_GRP2_EnableClock\n + * APB2ENR TIM1EN LL_APB1_GRP2_EnableClock\n + * APB2ENR SPI1EN LL_APB1_GRP2_EnableClock\n + * APB2ENR USART1EN LL_APB1_GRP2_EnableClock\n + * APB2ENR TIM15EN LL_APB1_GRP2_EnableClock\n + * APB2ENR TIM16EN LL_APB1_GRP2_EnableClock\n + * APB2ENR TIM17EN LL_APB1_GRP2_EnableClock\n + * APB2ENR DBGMCUEN LL_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not (available in register 2). + * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR ADC1EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR USART8EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR USART7EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR USART6EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR TIM1EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR USART1EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR TIM15EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR TIM16EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR TIM17EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR DBGMCUEN LL_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB1 peripherals clock (available in register 2). + * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_DisableClock\n + * APB2ENR ADC1EN LL_APB1_GRP2_DisableClock\n + * APB2ENR USART8EN LL_APB1_GRP2_DisableClock\n + * APB2ENR USART7EN LL_APB1_GRP2_DisableClock\n + * APB2ENR USART6EN LL_APB1_GRP2_DisableClock\n + * APB2ENR TIM1EN LL_APB1_GRP2_DisableClock\n + * APB2ENR SPI1EN LL_APB1_GRP2_DisableClock\n + * APB2ENR USART1EN LL_APB1_GRP2_DisableClock\n + * APB2ENR TIM15EN LL_APB1_GRP2_DisableClock\n + * APB2ENR TIM16EN LL_APB1_GRP2_DisableClock\n + * APB2ENR TIM17EN LL_APB1_GRP2_DisableClock\n + * APB2ENR DBGMCUEN LL_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset (available in register 2). + * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ForceReset\n + * APB2RSTR ADC1RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR USART8RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR USART7RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR USART6RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR TIM1RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR SPI1RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR USART1RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR TIM15RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR TIM16RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR TIM17RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR DBGMCURST LL_APB1_GRP2_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset (available in register 2). + * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR ADC1RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR USART8RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR USART7RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR USART6RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR TIM1RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR USART1RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR TIM15RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR TIM16RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR TIM17RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR DBGMCURST LL_APB1_GRP2_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_BUS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h new file mode 100644 index 0000000..3e16460 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h @@ -0,0 +1,320 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) API to access to MCU info (CPUID register) + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_CORTEX_H +#define __STM32F0xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Architecture number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture + * @retval Value should be equal to 0xC for Cortex-M0 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC20 for Cortex-M0 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_CORTEX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h new file mode 100644 index 0000000..b44e4be --- /dev/null +++ b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h @@ -0,0 +1,783 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_crs.h + * @author MCD Application Team + * @brief Header file of CRS LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_CRS_H +#define __STM32F0xx_LL_CRS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined(CRS) + +/** @defgroup CRS_LL CRS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants + * @{ + */ + +/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_CRS_ReadReg function + * @{ + */ +#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF +#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF +#define LL_CRS_ISR_ERRF CRS_ISR_ERRF +#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF +#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR +#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS +#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF +/** + * @} + */ + +/** @defgroup CRS_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions + * @{ + */ +#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE +#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE +#define LL_CRS_CR_ERRIE CRS_CR_ERRIE +#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider + * @{ + */ +#define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */ +#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source + * @{ + */ +#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */ +#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity + * @{ + */ +#define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */ +#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction + * @{ + */ +#define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */ +#define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values + * @{ + */ +/** + * @brief Reset value of the RELOAD field + * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz + * and a synchronization signal frequency of 1 kHz (SOF signal from USB) + */ +#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU) + +/** + * @brief Reset value of Frequency error limit. + */ +#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U) + +/** + * @brief Reset value of the HSI48 Calibration field + * @note The default value is 32, which corresponds to the middle of the trimming interval. + * The trimming step is around 67 kHz between two consecutive TRIM steps. + * A higher TRIM value corresponds to a higher output frequency + */ +#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros + * @{ + */ + +/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload + * @{ + */ + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between + * the target frequency and the frequency of the synchronization source after + * prescaling. It is then decreased by one in order to reach the expected + * synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval Reload value (in Hz) + */ +#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions + * @{ + */ + +/** @defgroup CRS_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable Frequency error counter + * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified + * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) +{ + SET_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Disable Frequency error counter + * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Check if Frequency error counter is enabled or not + * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)); +} + +/** + * @brief Enable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) +{ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Disable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Check if Automatic trimming is enabled or not + * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)); +} + +/** + * @brief Set HSI48 oscillator smooth trimming + * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only + * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming + * @param Value a number between Min_Data = 0 and Max_Data = 63 + * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); +} + +/** + * @brief Get HSI48 oscillator smooth trimming + * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming + * @retval a number between Min_Data = 0 and Max_Data = 63 + */ +__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) +{ + return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); +} + +/** + * @brief Set counter reload value + * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter + * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF + * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT + * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); +} + +/** + * @brief Get counter reload value + * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter + * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); +} + +/** + * @brief Set frequency error limit + * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit + * @param Value a number between Min_Data = 0 and Max_Data = 255 + * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Get frequency error limit + * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit + * @retval A number between Min_Data = 0 and Max_Data = 255 + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Set division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); +} + +/** + * @brief Get division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); +} + +/** + * @brief Set SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); +} + +/** + * @brief Get SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); +} + +/** + * @brief Set input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); +} + +/** + * @brief Get input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); +} + +/** + * @brief Configure CRS for the synchronization + * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n + * CFGR RELOAD LL_CRS_ConfigSynchronization\n + * CFGR FELIM LL_CRS_ConfigSynchronization\n + * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n + * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n + * CFGR SYNCPOL LL_CRS_ConfigSynchronization + * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 + * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF + * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 + * @param Settings This parameter can be a combination of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 + * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB + * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos); + MODIFY_REG(CRS->CFGR, + CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, + ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_CRS_Management CRS_Management + * @{ + */ + +/** + * @brief Generate software SYNC event + * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Get the frequency error direction latched in the time of the last + * SYNC event + * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP + * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Get the frequency error counter value latched in the time of the last SYNC event + * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture + * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if SYNC event OK signal occurred or not + * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)); +} + +/** + * @brief Check if SYNC warning signal occurred or not + * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)); +} + +/** + * @brief Check if Synchronization or trimming error signal occurred or not + * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)); +} + +/** + * @brief Check if Expected SYNC signal occurred or not + * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)); +} + +/** + * @brief Check if SYNC error signal occurred or not + * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)); +} + +/** + * @brief Check if SYNC missed error signal occurred or not + * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)); +} + +/** + * @brief Check if Trimming overflow or underflow occurred or not + * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)); +} + +/** + * @brief Clear the SYNC event OK flag + * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); +} + +/** + * @brief Clear the SYNC warning flag + * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); +} + +/** + * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also + * the ERR flag + * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); +} + +/** + * @brief Clear Expected SYNC flag + * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Disable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Check if SYNC event OK interrupt is enabled or not + * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)); +} + +/** + * @brief Enable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Disable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Check if SYNC warning interrupt is enabled or not + * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)); +} + +/** + * @brief Enable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ERR(void) +{ + SET_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Disable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ERR(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Check if Synchronization or trimming error interrupt is enabled or not + * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)); +} + +/** + * @brief Enable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Disable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Check if Expected SYNC interrupt is enabled or not + * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRS_DeInit(void); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRS) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_CRS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h new file mode 100644 index 0000000..2fd847b --- /dev/null +++ b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h @@ -0,0 +1,2236 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_DMA_H +#define __STM32F0xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ +static const uint8_t CHANNEL_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), +#if defined(DMA1_Channel6) + (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), +#endif /*DMA1_Channel6*/ +#if defined(DMA1_Channel7) + (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) +#endif /*DMA1_Channel7*/ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Constants DMA Private Constants + * @{ + */ +/* Define used to get CSELR register offset */ +#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) + +/* Defines used for the bit position in the register and perform offsets */ +#define DMA_POSITION_CSELR_CXS ((Channel-1U)*4U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note: The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Channel + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ +#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) + + uint32_t PeriphRequest; /*!< Specifies the peripheral request. + This parameter can be a value of @ref DMA_LL_EC_REQUEST + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ +#endif + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ +/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMA_WriteReg function + * @{ + */ +#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ +#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ +#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ +#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ +#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ +#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ +#if defined(DMA1_Channel6) +#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ +#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ +#endif +#if defined(DMA1_Channel7) +#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ +#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ +#endif +/** + * @} + */ + +/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA_ReadReg function + * @{ + */ +#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ +#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ +#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ +#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ +#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ +#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ +#if defined(DMA1_Channel6) +#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ +#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ +#endif +#if defined(DMA1_Channel7) +#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ +#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ +#endif +/** + * @} + */ + +/** @defgroup DMA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions + * @{ + */ +#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ +#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ +#if defined(DMA1_Channel6) +#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ +#endif +#if defined(DMA1_Channel7) +#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ +#endif +#if defined(USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#endif /*USE_FULL_LL_DRIVER*/ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE Transfer mode + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode + * @{ + */ +#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY Memory increment mode + * @{ + */ +#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) +/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request + * @{ + */ +#define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */ +#define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */ +#define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */ +#define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */ +#define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */ +#define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */ +#define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */ +#define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */ +#define LL_DMA_REQUEST_8 0x00000008U /*!< DMA peripheral request 8 */ +#define LL_DMA_REQUEST_9 0x00000009U /*!< DMA peripheral request 9 */ +#define LL_DMA_REQUEST_10 0x0000000AU /*!< DMA peripheral request 10 */ +#define LL_DMA_REQUEST_11 0x0000000BU /*!< DMA peripheral request 11 */ +#define LL_DMA_REQUEST_12 0x0000000CU /*!< DMA peripheral request 12 */ +#define LL_DMA_REQUEST_13 0x0000000DU /*!< DMA peripheral request 13 */ +#define LL_DMA_REQUEST_14 0x0000000EU /*!< DMA peripheral request 14 */ +#define LL_DMA_REQUEST_15 0x0000000FU /*!< DMA peripheral request 15 */ +/** + * @} + */ +#endif + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ +/** + * @brief Convert DMAx_Channely into DMAx + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval DMAx + */ +#if defined(DMA2) +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) +#else +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) +#endif + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval LL_DMA_CHANNEL_y + */ +#if defined (DMA2) +#if defined (DMA2_Channel6) && defined (DMA2_Channel7) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#endif +#else +#if defined (DMA1_Channel6) && defined (DMA1_Channel7) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#elif defined (DMA1_Channel6) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + LL_DMA_CHANNEL_6) +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + LL_DMA_CHANNEL_5) +#endif /* DMA1_Channel6 && DMA1_Channel7 */ +#endif + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely + * @param __DMA_INSTANCE__ DMAx + * @param __CHANNEL__ LL_DMA_CHANNEL_y + * @retval DMAx_Channely + */ +#if defined (DMA2) +#if defined (DMA2_Channel6) && defined (DMA2_Channel7) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ + DMA2_Channel7) +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#endif +#else +#if defined (DMA1_Channel6) && defined (DMA1_Channel7) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#elif defined (DMA1_Channel6) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + DMA1_Channel6) +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + DMA1_Channel5) +#endif /* DMA1_Channel6 && DMA1_Channel7 */ +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA channel. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable DMA channel. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Check if DMA channel is enabled or disabled. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)); +} + +/** + * @brief Configure all parameters link to DMA transfer. + * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n + * CCR MEM2MEM LL_DMA_ConfigTransfer\n + * CCR CIRC LL_DMA_ConfigTransfer\n + * CCR PINC LL_DMA_ConfigTransfer\n + * CCR MINC LL_DMA_ConfigTransfer\n + * CCR PSIZE LL_DMA_ConfigTransfer\n + * CCR MSIZE LL_DMA_ConfigTransfer\n + * CCR PL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); +} + +/** + * @brief Set DMA mode circular or normal. + * @note The circular buffer mode cannot be used if the memory-to-memory + * data transfer is configured on the selected Channel. + * @rmtoll CCR CIRC LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, + Mode); +} + +/** + * @brief Get DMA mode circular or normal. + * @rmtoll CCR CIRC LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_CIRC)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, + PeriphOrM2MSrcIncMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, + MemoryOrM2MDstIncMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, + PeriphOrM2MSrcDataSize); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CCR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, + MemoryOrM2MDstDataSize); +} + +/** + * @brief Get Memory size. + * @rmtoll CCR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MSIZE)); +} + +/** + * @brief Set Channel priority level. + * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, + Priority); +} + +/** + * @brief Get Channel priority level. + * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @note This action has no effect if + * channel is enabled. + * @rmtoll CNDTR NDT LL_DMA_SetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @note Once the channel is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @rmtoll CNDTR NDT LL_DMA_GetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT)); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA channel is enabled. + * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). + * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n + * CMAR MA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, + uint32_t DstAddress, uint32_t Direction) +{ + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); +} + +/** + * @brief Get Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CMAR MA LL_DMA_GetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + +/** + * @brief Get Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CPAR PA LL_DMA_GetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + +#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) +/** + * @brief Set DMA request for DMA instance on Channel x. + * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection. + * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n + * CSELR C2S LL_DMA_SetPeriphRequest\n + * CSELR C3S LL_DMA_SetPeriphRequest\n + * CSELR C4S LL_DMA_SetPeriphRequest\n + * CSELR C5S LL_DMA_SetPeriphRequest\n + * CSELR C6S LL_DMA_SetPeriphRequest\n + * CSELR C7S LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphRequest This parameter can be one of the following values: + * @arg @ref LL_DMA_REQUEST_0 + * @arg @ref LL_DMA_REQUEST_1 + * @arg @ref LL_DMA_REQUEST_2 + * @arg @ref LL_DMA_REQUEST_3 + * @arg @ref LL_DMA_REQUEST_4 + * @arg @ref LL_DMA_REQUEST_5 + * @arg @ref LL_DMA_REQUEST_6 + * @arg @ref LL_DMA_REQUEST_7 + * @arg @ref LL_DMA_REQUEST_8 + * @arg @ref LL_DMA_REQUEST_9 + * @arg @ref LL_DMA_REQUEST_10 + * @arg @ref LL_DMA_REQUEST_11 + * @arg @ref LL_DMA_REQUEST_12 + * @arg @ref LL_DMA_REQUEST_13 + * @arg @ref LL_DMA_REQUEST_14 + * @arg @ref LL_DMA_REQUEST_15 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest) +{ + MODIFY_REG(DMAx->CSELR, + DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); +} + +/** + * @brief Get DMA request for DMA instance on Channel x. + * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n + * CSELR C2S LL_DMA_GetPeriphRequest\n + * CSELR C3S LL_DMA_GetPeriphRequest\n + * CSELR C4S LL_DMA_GetPeriphRequest\n + * CSELR C5S LL_DMA_GetPeriphRequest\n + * CSELR C6S LL_DMA_GetPeriphRequest\n + * CSELR C7S LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_REQUEST_0 + * @arg @ref LL_DMA_REQUEST_1 + * @arg @ref LL_DMA_REQUEST_2 + * @arg @ref LL_DMA_REQUEST_3 + * @arg @ref LL_DMA_REQUEST_4 + * @arg @ref LL_DMA_REQUEST_5 + * @arg @ref LL_DMA_REQUEST_6 + * @arg @ref LL_DMA_REQUEST_7 + * @arg @ref LL_DMA_REQUEST_8 + * @arg @ref LL_DMA_REQUEST_9 + * @arg @ref LL_DMA_REQUEST_10 + * @arg @ref LL_DMA_REQUEST_11 + * @arg @ref LL_DMA_REQUEST_12 + * @arg @ref LL_DMA_REQUEST_13 + * @arg @ref LL_DMA_REQUEST_14 + * @arg @ref LL_DMA_REQUEST_15 + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(DMAx->CSELR, + DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS); +} +#endif + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Channel 1 global interrupt flag. + * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); +} + +/** + * @brief Get Channel 2 global interrupt flag. + * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); +} + +/** + * @brief Get Channel 3 global interrupt flag. + * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); +} + +/** + * @brief Get Channel 4 global interrupt flag. + * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); +} + +/** + * @brief Get Channel 5 global interrupt flag. + * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 global interrupt flag. + * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 global interrupt flag. + * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); +} +#endif + +/** + * @brief Get Channel 1 transfer complete flag. + * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); +} + +/** + * @brief Get Channel 2 transfer complete flag. + * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); +} + +/** + * @brief Get Channel 3 transfer complete flag. + * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); +} + +/** + * @brief Get Channel 4 transfer complete flag. + * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); +} + +/** + * @brief Get Channel 5 transfer complete flag. + * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 transfer complete flag. + * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 transfer complete flag. + * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); +} +#endif + +/** + * @brief Get Channel 1 half transfer flag. + * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); +} + +/** + * @brief Get Channel 2 half transfer flag. + * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); +} + +/** + * @brief Get Channel 3 half transfer flag. + * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); +} + +/** + * @brief Get Channel 4 half transfer flag. + * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); +} + +/** + * @brief Get Channel 5 half transfer flag. + * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 half transfer flag. + * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 half transfer flag. + * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); +} +#endif + +/** + * @brief Get Channel 1 transfer error flag. + * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); +} + +/** + * @brief Get Channel 2 transfer error flag. + * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); +} + +/** + * @brief Get Channel 3 transfer error flag. + * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); +} + +/** + * @brief Get Channel 4 transfer error flag. + * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); +} + +/** + * @brief Get Channel 5 transfer error flag. + * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 transfer error flag. + * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 transfer error flag. + * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); +} +#endif + +/** + * @brief Clear Channel 1 global interrupt flag. + * @note Do not Clear Channel 1 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1, + LL_DMA_ClearFlag_TE1. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); +} + +/** + * @brief Clear Channel 2 global interrupt flag. + * @note Do not Clear Channel 2 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2, + LL_DMA_ClearFlag_TE2. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); +} + +/** + * @brief Clear Channel 3 global interrupt flag. + * @note Do not Clear Channel 3 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3, + LL_DMA_ClearFlag_TE3. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); +} + +/** + * @brief Clear Channel 4 global interrupt flag. + * @note Do not Clear Channel 4 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4, + LL_DMA_ClearFlag_TE4. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); +} + +/** + * @brief Clear Channel 5 global interrupt flag. + * @note Do not Clear Channel 5 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5, + LL_DMA_ClearFlag_TE5. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 global interrupt flag. + * @note Do not Clear Channel 6 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6, + LL_DMA_ClearFlag_TE6. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 global interrupt flag. + * @note Do not Clear Channel 7 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7, + LL_DMA_ClearFlag_TE7. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); +} +#endif + +/** + * @brief Clear Channel 1 transfer complete flag. + * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); +} + +/** + * @brief Clear Channel 2 transfer complete flag. + * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); +} + +/** + * @brief Clear Channel 3 transfer complete flag. + * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); +} + +/** + * @brief Clear Channel 4 transfer complete flag. + * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); +} + +/** + * @brief Clear Channel 5 transfer complete flag. + * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 transfer complete flag. + * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 transfer complete flag. + * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); +} +#endif + +/** + * @brief Clear Channel 1 half transfer flag. + * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); +} + +/** + * @brief Clear Channel 2 half transfer flag. + * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); +} + +/** + * @brief Clear Channel 3 half transfer flag. + * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); +} + +/** + * @brief Clear Channel 4 half transfer flag. + * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); +} + +/** + * @brief Clear Channel 5 half transfer flag. + * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 half transfer flag. + * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 half transfer flag. + * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); +} +#endif + +/** + * @brief Clear Channel 1 transfer error flag. + * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); +} + +/** + * @brief Clear Channel 2 transfer error flag. + * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); +} + +/** + * @brief Clear Channel 3 transfer error flag. + * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); +} + +/** + * @brief Clear Channel 4 transfer error flag. + * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); +} + +/** + * @brief Clear Channel 5 transfer error flag. + * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 transfer error flag. + * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 transfer error flag. + * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); +} +#endif + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Check if Transfer complete Interrupt is enabled. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)); +} + +/** + * @brief Check if Half transfer Interrupt is enabled. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)); +} + +/** + * @brief Check if Transfer error Interrupt is enabled. + * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h new file mode 100644 index 0000000..f488959 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h @@ -0,0 +1,1016 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_EXTI_H +#define __STM32F0xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ +#if defined(EXTI_IMR_IM16) +#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ +#endif +#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#endif +#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ +#if defined(EXTI_IMR_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ +#endif +#if defined(EXTI_IMR_IM21) +#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ +#endif +#if defined(EXTI_IMR_IM22) +#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ +#endif +#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ +#if defined(EXTI_IMR_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ +#endif +#if defined(EXTI_IMR_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ +#endif +#if defined(EXTI_IMR_IM26) +#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ +#endif +#if defined(EXTI_IMR_IM27) +#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ +#endif +#if defined(EXTI_IMR_IM28) +#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ +#endif +#if defined(EXTI_IMR_IM29) +#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ +#endif +#if defined(EXTI_IMR_IM30) +#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ +#endif +#if defined(EXTI_IMR_IM31) +#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ +#endif +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ + + +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); + +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER, ExtiLine); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); +} + + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR, ExtiLine); +} + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h new file mode 100644 index 0000000..1123dd3 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h @@ -0,0 +1,940 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_GPIO_H +#define __STM32F0xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ + GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ + GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ + GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ + GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ + GPIO_BSRR_BS_15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEEDR0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEEDR0 /*!< Select I/O high output speed */ +/** + * @} + */ +#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW +#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM +#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_HIGH + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0), ((Pin * Pin) * Mode)); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0), ((Pin * Pin) * Speed)); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0), ((Pin * Pin) * Pull)); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF7 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), + ((((Pin * Pin) * Pin) * Pin) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF7 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF7 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * + (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +{ + return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BRR, PinMask); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h new file mode 100644 index 0000000..d50b86a --- /dev/null +++ b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h @@ -0,0 +1,552 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_PWR_H +#define __STM32F0xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ +#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ +#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ +#if defined(PWR_PVD_SUPPORT) +#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ +#endif /* PWR_PVD_SUPPORT */ +#if defined(PWR_CSR_VREFINTRDYF) +#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ +#endif /* PWR_CSR_VREFINTRDYF */ +#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ +#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ +#if defined(PWR_CSR_EWUP3) +#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ +#endif /* PWR_CSR_EWUP3 */ +#if defined(PWR_CSR_EWUP4) +#define LL_PWR_CSR_EWUP4 PWR_CSR_EWUP4 /*!< Enable WKUP pin 4 */ +#endif /* PWR_CSR_EWUP4 */ +#if defined(PWR_CSR_EWUP5) +#define LL_PWR_CSR_EWUP5 PWR_CSR_EWUP5 /*!< Enable WKUP pin 5 */ +#endif /* PWR_CSR_EWUP5 */ +#if defined(PWR_CSR_EWUP6) +#define LL_PWR_CSR_EWUP6 PWR_CSR_EWUP6 /*!< Enable WKUP pin 6 */ +#endif /* PWR_CSR_EWUP6 */ +#if defined(PWR_CSR_EWUP7) +#define LL_PWR_CSR_EWUP7 PWR_CSR_EWUP7 /*!< Enable WKUP pin 7 */ +#endif /* PWR_CSR_EWUP7 */ +#if defined(PWR_CSR_EWUP8) +#define LL_PWR_CSR_EWUP8 PWR_CSR_EWUP8 /*!< Enable WKUP pin 8 */ +#endif /* PWR_CSR_EWUP8 */ +/** + * @} + */ + + +/** @defgroup PWR_LL_EC_MODE_PWR Mode Power + * @{ + */ +#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ +/** + * @} + */ + +#if defined(PWR_CR_LPDS) +/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ +/** + * @} + */ +#endif /* PWR_CR_LPDS */ + +#if defined(PWR_PVD_SUPPORT) +/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level + * @{ + */ +#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold 0 */ +#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold 1 */ +#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold 2 */ +#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold 3 */ +#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold 4 */ +#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold 5 */ +#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold 6 */ +#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold 7 */ +/** + * @} + */ +#endif /* PWR_PVD_SUPPORT */ +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ +#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ +#if defined(PWR_CSR_EWUP3) +#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ +#endif /* PWR_CSR_EWUP3 */ +#if defined(PWR_CSR_EWUP4) +#define LL_PWR_WAKEUP_PIN4 (PWR_CSR_EWUP4) /*!< WKUP pin 4 : LLG TBD */ +#endif /* PWR_CSR_EWUP4 */ +#if defined(PWR_CSR_EWUP5) +#define LL_PWR_WAKEUP_PIN5 (PWR_CSR_EWUP5) /*!< WKUP pin 5 : LLG TBD */ +#endif /* PWR_CSR_EWUP5 */ +#if defined(PWR_CSR_EWUP6) +#define LL_PWR_WAKEUP_PIN6 (PWR_CSR_EWUP6) /*!< WKUP pin 6 : LLG TBD */ +#endif /* PWR_CSR_EWUP6 */ +#if defined(PWR_CSR_EWUP7) +#define LL_PWR_WAKEUP_PIN7 (PWR_CSR_EWUP7) /*!< WKUP pin 7 : LLG TBD */ +#endif /* PWR_CSR_EWUP7 */ +#if defined(PWR_CSR_EWUP8) +#define LL_PWR_WAKEUP_PIN8 (PWR_CSR_EWUP8) /*!< WKUP pin 8 : LLG TBD */ +#endif /* PWR_CSR_EWUP8 */ +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable access to the backup domain + * @rmtoll CR DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); +} + +#if defined(PWR_CR_LPDS) +/** + * @brief Set voltage Regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_SetRegulModeDS + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); +} + +/** + * @brief Get voltage Regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_GetRegulModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); +} +#endif /* PWR_CR_LPDS */ + +/** + * @brief Set Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_SetPowerMode\n + * @rmtoll CR LPDS LL_PWR_SetPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); +} + +/** + * @brief Get Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_GetPowerMode\n + * @rmtoll CR LPDS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); +} + +#if defined(PWR_PVD_SUPPORT) +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); +} +#endif /* PWR_PVD_SUPPORT */ + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP4 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP5 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP6 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP7 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP8 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 (*) + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 (*) + * @arg @ref LL_PWR_WAKEUP_PIN7 (*) + * @arg @ref LL_PWR_WAKEUP_PIN8 (*) + * + * (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP4 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP5 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP6 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP7 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP8 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 (*) + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 (*) + * @arg @ref LL_PWR_WAKEUP_PIN7 (*) + * @arg @ref LL_PWR_WAKEUP_PIN8 (*) + * + * (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP4 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP5 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP6 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP7 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP8 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 (*) + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 (*) + * @arg @ref LL_PWR_WAKEUP_PIN7 (*) + * @arg @ref LL_PWR_WAKEUP_PIN8 (*) + * + * (*) not available on all devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); +} + + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Wake-up Flag + * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); +} + +/** + * @brief Get Standby Flag + * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); +} + +#if defined(PWR_PVD_SUPPORT) +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); +} +#endif /* PWR_PVD_SUPPORT */ + +#if defined(PWR_CSR_VREFINTRDYF) +/** + * @brief Get Internal Reference VrefInt Flag + * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF)); +} +#endif /* PWR_CSR_VREFINTRDYF */ +/** + * @brief Clear Standby Flag + * @rmtoll CR CSBF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + SET_BIT(PWR->CR, PWR_CR_CSBF); +} + +/** + * @brief Clear Wake-up Flags + * @rmtoll CR CWUF LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + SET_BIT(PWR->CR, PWR_CR_CWUF); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h new file mode 100644 index 0000000..0206b9d --- /dev/null +++ b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h @@ -0,0 +1,2261 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_RCC_H +#define __STM32F0xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Constants RCC Private Constants + * @{ + */ +/* Defines used for the bit position in the register and perform offsets*/ +#define RCC_POSITION_HPRE (uint32_t)4U /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_PPRE1 (uint32_t)8U /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_PLLMUL (uint32_t)18U /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_HSICAL (uint32_t)8U /*!< field position in register RCC_CR */ +#define RCC_POSITION_HSITRIM (uint32_t)3U /*!< field position in register RCC_CR */ +#define RCC_POSITION_HSI14TRIM (uint32_t)3U /*!< field position in register RCC_CR2 */ +#define RCC_POSITION_HSI14CAL (uint32_t)8U /*!< field position in register RCC_CR2 */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_POSITION_HSI48CAL (uint32_t)24U /*!< field position in register RCC_CR2 */ +#endif /* RCC_HSI48_SUPPORT */ +#define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */ +#define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */ +#define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ +#if defined(RCC_HSI48_SUPPORT) + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ +#endif /* HSI48_VALUE */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#define LL_RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC /*!< HSI14 Ready Interrupt Clear */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIR_HSI48RDYC RCC_CIR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define LL_RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF /*!< HSI14 Ready Interrupt flag */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIR_HSI48RDYF RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +#if defined(RCC_CSR_V18PWRRSTF) +#define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */ +#endif /* RCC_CSR_V18PWRRSTF */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#define LL_RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE /*!< HSI14 Ready Interrupt Enable */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIR_HSI48RDYIE RCC_CIR_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ +#if defined(RCC_CFGR_SW_HSI48) +#define LL_RCC_SYS_CLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 /*!< HSI48 selection as system clock */ +#endif /* RCC_CFGR_SW_HSI48 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +#if defined(RCC_CFGR_SWS_HSI48) +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 /*!< HSI48 used as system clock */ +#endif /* RCC_CFGR_SWS_HSI48 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCOSEL_HSI14 /*!< HSI14 oscillator clock selected */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */ +#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */ +#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */ +#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */ +#if defined(RCC_CFGR_MCOSEL_HSI48) +#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /*!< HSI48 selection as MCO source */ +#endif /* RCC_CFGR_MCOSEL_HSI48 */ +#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/ +#if defined(RCC_CFGR_PLLNODIV) +#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/ +#endif /* RCC_CFGR_PLLNODIV */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */ +#if defined(RCC_CFGR_MCOPRE) +#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ +#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ +#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ +#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ +#define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */ +#define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */ +#define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */ +#endif /* RCC_CFGR_MCOPRE */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_PCLK) /*!< PCLK1 clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */ +#if defined(RCC_CFGR3_USART2SW) +#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */ +#endif /* RCC_CFGR3_USART2SW */ +#if defined(RCC_CFGR3_USART3SW) +#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */ +#endif /* RCC_CFGR3_USART3SW */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI /*!< HSI oscillator clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK /*!< System clock selected as I2C1 clock source */ +/** + * @} + */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */ +#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */ +/** + * @} + */ + +#endif /* CEC */ + +#if defined(USB) +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#if defined(RCC_CFGR3_USBSW_HSI48) +#define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 oscillator clock used as USB clock source */ +#else +#define LL_RCC_USB_CLKSOURCE_NONE ((uint32_t)0x00000000) /*!< USB Clock disabled */ +#endif /*RCC_CFGR3_USBSW_HSI48*/ +#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL selected as USB clock source */ +/** + * @} + */ + +#endif /* USB */ + +/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */ +#if defined(RCC_CFGR3_USART2SW) +#define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */ +#endif /* RCC_CFGR3_USART2SW */ +#if defined(RCC_CFGR3_USART3SW) +#define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */ +#endif /* RCC_CFGR3_USART3SW */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */ +/** + * @} + */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */ +/** + * @} + */ +#endif /* CEC */ + +#if defined(USB) +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#define LL_RCC_USB_CLKSOURCE RCC_CFGR3_USBSW /*!< USB Clock source selection */ +/** + * @} + */ +#endif /* USB */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor + * @{ + */ +#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */ +#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */ +#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */ +#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */ +#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */ +#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */ +#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */ +#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */ +#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */ +#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */ +#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */ +#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */ +#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */ +#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */ +#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE + * @{ + */ +#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as main PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) +#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */ +#if defined(RCC_CFGR_SW_HSI48) +#define LL_RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< HSI48/PREDIV clock selected as PLL entry clock source */ +#endif /* RCC_CFGR_SW_HSI48 */ +#else +#define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor + * @{ + */ +#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */ +#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */ +#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */ +#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */ +#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */ +#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */ +#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */ +#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */ +#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */ +#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */ +#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */ +#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */ +#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */ +#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */ +#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */ +#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) +/** + * @brief Helper macro to calculate the PLLCLK frequency + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator() + * , @ref LL_RCC_PLL_GetPrediv()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/HSI48) + * @param __PLLMUL__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @param __PLLPREDIV__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PREDIV_DIV_1 + * @arg @ref LL_RCC_PREDIV_DIV_2 + * @arg @ref LL_RCC_PREDIV_DIV_3 + * @arg @ref LL_RCC_PREDIV_DIV_4 + * @arg @ref LL_RCC_PREDIV_DIV_5 + * @arg @ref LL_RCC_PREDIV_DIV_6 + * @arg @ref LL_RCC_PREDIV_DIV_7 + * @arg @ref LL_RCC_PREDIV_DIV_8 + * @arg @ref LL_RCC_PREDIV_DIV_9 + * @arg @ref LL_RCC_PREDIV_DIV_10 + * @arg @ref LL_RCC_PREDIV_DIV_11 + * @arg @ref LL_RCC_PREDIV_DIV_12 + * @arg @ref LL_RCC_PREDIV_DIV_13 + * @arg @ref LL_RCC_PREDIV_DIV_14 + * @arg @ref LL_RCC_PREDIV_DIV_15 + * @arg @ref LL_RCC_PREDIV_DIV_16 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \ + (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) + +#else +/** + * @brief Helper macro to calculate the PLLCLK frequency + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2) + * @param __PLLMUL__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ + ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ +/** + * @brief Helper macro to calculate the HCLK frequency + * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler + * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) + * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler + * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos]) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Disable the Clock Security System. + * @note Cannot be disabled in HSE is ready (only by hardware) + * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 16, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value between Min_Data = 0x00 and Max_Data = 0x1F + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); +} + +/** + * @} + */ + +#if defined(RCC_HSI48_SUPPORT) +/** @defgroup RCC_LL_EF_HSI48 HSI48 + * @{ + */ + +/** + * @brief Enable HSI48 + * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Enable(void) +{ + SET_BIT(RCC->CR2, RCC_CR2_HSI48ON); +} + +/** + * @brief Disable HSI48 + * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Disable(void) +{ + CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON); +} + +/** + * @brief Check if HSI48 oscillator Ready + * @rmtoll CR2 HSI48RDY LL_RCC_HSI48_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) +{ + return (READ_BIT(RCC->CR2, RCC_CR2_HSI48RDY) == (RCC_CR2_HSI48RDY)); +} + +/** + * @brief Get HSI48 Calibration value + * @rmtoll CR2 HSI48CAL LL_RCC_HSI48_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48CAL) >> RCC_POSITION_HSI48CAL); +} + +/** + * @} + */ + +#endif /* RCC_HSI48_SUPPORT */ + +/** @defgroup RCC_LL_EF_HSI14 HSI14 + * @{ + */ + +/** + * @brief Enable HSI14 + * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI14_Enable(void) +{ + SET_BIT(RCC->CR2, RCC_CR2_HSI14ON); +} + +/** + * @brief Disable HSI14 + * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI14_Disable(void) +{ + CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON); +} + +/** + * @brief Check if HSI14 oscillator Ready + * @rmtoll CR2 HSI14RDY LL_RCC_HSI14_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI14_IsReady(void) +{ + return (READ_BIT(RCC->CR2, RCC_CR2_HSI14RDY) == (RCC_CR2_HSI14RDY)); +} + +/** + * @brief ADC interface can turn on the HSI14 oscillator + * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_EnableADCControl + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI14_EnableADCControl(void) +{ + CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS); +} + +/** + * @brief ADC interface can not turn on the HSI14 oscillator + * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_DisableADCControl + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI14_DisableADCControl(void) +{ + SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS); +} + +/** + * @brief Set HSI14 Calibration trimming + * @note user-programmable trimming value that is added to the HSI14CAL + * @note Default value is 16, which, when added to the HSI14CAL value, + * should trim the HSI14 to 14 MHz +/- 1 % + * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_SetCalibTrimming + * @param Value between Min_Data = 0x00 and Max_Data = 0xFF + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI14_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, Value << RCC_POSITION_HSI14TRIM); +} + +/** + * @brief Get HSI14 Calibration value + * @note When HSI14TRIM is written, HSI14CAL is updated with the sum of + * HSI14TRIM and the factory trim value + * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_GetCalibTrimming + * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + */ +__STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14TRIM) >> RCC_POSITION_HSI14TRIM); +} + +/** + * @brief Get HSI14 Calibration trimming + * @rmtoll CR2 HSI14CAL LL_RCC_HSI14_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + */ +__STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14CAL) >> RCC_POSITION_HSI14CAL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI48 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n + * CFGR MCOPRE LL_RCC_ConfigMCO\n + * CFGR PLLNODIV LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_HSI14 + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*) + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 + * + * (*) value not defined in all devices + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 (*) + * @arg @ref LL_RCC_MCO1_DIV_4 (*) + * @arg @ref LL_RCC_MCO1_DIV_8 (*) + * @arg @ref LL_RCC_MCO1_DIV_16 (*) + * @arg @ref LL_RCC_MCO1_DIV_32 (*) + * @arg @ref LL_RCC_MCO1_DIV_64 (*) + * @arg @ref LL_RCC_MCO1_DIV_128 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ +#if defined(RCC_CFGR_MCOPRE) +#if defined(RCC_CFGR_PLLNODIV) + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler); +#else + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); +#endif /* RCC_CFGR_PLLNODIV */ +#else + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); +#endif /* RCC_CFGR_MCOPRE */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure USARTx clock source + * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n + * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n + * CFGR3 USART3SW LL_RCC_SetUSARTClockSource + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +{ + MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU)); +} + +/** + * @brief Configure I2Cx clock source + * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +{ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, I2CxSource); +} + +#if defined(CEC) +/** + * @brief Configure CEC clock source + * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource + * @param CECxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource) +{ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource); +} +#endif /* CEC */ + +#if defined(USB) +/** + * @brief Configure USB clock source + * @rmtoll CFGR3 USBSW LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, USBxSource); +} +#endif /* USB */ + +/** + * @brief Get USARTx clock source + * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n + * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n + * CFGR3 USART3SW LL_RCC_GetUSARTClockSource + * @param USARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U)); +} + +/** + * @brief Get I2Cx clock source + * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource + * @param I2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx)); +} + +#if defined(CEC) +/** + * @brief Get CEC clock source + * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource + * @param CECx This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, CECx)); +} +#endif /* CEC */ + +#if defined(USB) +/** + * @brief Get USBx clock source + * @rmtoll CFGR3 USBSW LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, USBx)); +} +#endif /* USB */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed any more unless + * the Backup domain is reset. The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); +} + +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) +/** + * @brief Configure PLL used for SYSCLK Domain + * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) + * + * (*) value not defined in all devices + * @param PLLMul This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @param PLLDiv This parameter can be one of the following values: + * @arg @ref LL_RCC_PREDIV_DIV_1 + * @arg @ref LL_RCC_PREDIV_DIV_2 + * @arg @ref LL_RCC_PREDIV_DIV_3 + * @arg @ref LL_RCC_PREDIV_DIV_4 + * @arg @ref LL_RCC_PREDIV_DIV_5 + * @arg @ref LL_RCC_PREDIV_DIV_6 + * @arg @ref LL_RCC_PREDIV_DIV_7 + * @arg @ref LL_RCC_PREDIV_DIV_8 + * @arg @ref LL_RCC_PREDIV_DIV_9 + * @arg @ref LL_RCC_PREDIV_DIV_10 + * @arg @ref LL_RCC_PREDIV_DIV_11 + * @arg @ref LL_RCC_PREDIV_DIV_12 + * @arg @ref LL_RCC_PREDIV_DIV_13 + * @arg @ref LL_RCC_PREDIV_DIV_14 + * @arg @ref LL_RCC_PREDIV_DIV_15 + * @arg @ref LL_RCC_PREDIV_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); +} + +#else + +/** + * @brief Configure PLL used for SYSCLK Domain + * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 + * @param PLLMul This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV)); +} +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + +/** + * @brief Configure PLL clock source + * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI (*) + * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI (*) + * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); +} + +/** + * @brief Get PLL multiplication Factor + * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); +} + +/** + * @brief Get PREDIV division factor for the main PLL + * @note They can be written only when the PLL is disabled + * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PREDIV_DIV_1 + * @arg @ref LL_RCC_PREDIV_DIV_2 + * @arg @ref LL_RCC_PREDIV_DIV_3 + * @arg @ref LL_RCC_PREDIV_DIV_4 + * @arg @ref LL_RCC_PREDIV_DIV_5 + * @arg @ref LL_RCC_PREDIV_DIV_6 + * @arg @ref LL_RCC_PREDIV_DIV_7 + * @arg @ref LL_RCC_PREDIV_DIV_8 + * @arg @ref LL_RCC_PREDIV_DIV_9 + * @arg @ref LL_RCC_PREDIV_DIV_10 + * @arg @ref LL_RCC_PREDIV_DIV_11 + * @arg @ref LL_RCC_PREDIV_DIV_12 + * @arg @ref LL_RCC_PREDIV_DIV_13 + * @arg @ref LL_RCC_PREDIV_DIV_14 + * @arg @ref LL_RCC_PREDIV_DIV_15 + * @arg @ref LL_RCC_PREDIV_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); +} + +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); +} + +/** + * @brief Clear HSI14 ready interrupt flag + * @rmtoll CIR HSI14RDYC LL_RCC_ClearFlag_HSI14RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI14RDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYC); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Clear HSI48 ready interrupt flag + * @rmtoll CIR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYC); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_CSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); +} + +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); +} + +/** + * @brief Check if HSI14 ready interrupt occurred or not + * @rmtoll CIR HSI14RDYF LL_RCC_IsActiveFlag_HSI14RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI14RDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYF) == (RCC_CIR_HSI14RDYF)); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Check if HSI48 ready interrupt occurred or not + * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYF) == (RCC_CIR_HSI48RDYF)); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); +} + +/** + * @brief Check if RCC flag is set or not. + * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); +} + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); +} + +#if defined(RCC_CSR_V18PWRRSTF) +/** + * @brief Check if RCC Reset flag of the 1.8 V domain is set or not. + * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF)); +} +#endif /* RCC_CSR_V18PWRRSTF */ + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +/** + * @brief Enable HSI14 ready interrupt + * @rmtoll CIR HSI14RDYIE LL_RCC_EnableIT_HSI14RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI14RDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Enable HSI48 ready interrupt + * @rmtoll CIR HSI48RDYIE LL_RCC_EnableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +/** + * @brief Disable HSI14 ready interrupt + * @rmtoll CIR HSI14RDYIE LL_RCC_DisableIT_HSI14RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI14RDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Disable HSI48 ready interrupt + * @rmtoll CIR HSI48RDYIE LL_RCC_DisableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); +} + +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); +} + +/** + * @brief Checks if HSI14 ready interrupt source is enabled or disabled. + * @rmtoll CIR HSI14RDYIE LL_RCC_IsEnabledIT_HSI14RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI14RDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE) == (RCC_CIR_HSI14RDYIE)); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Checks if HSI48 ready interrupt source is enabled or disabled. + * @rmtoll CIR HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE) == (RCC_CIR_HSI48RDYIE)); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +#if defined(USB_OTG_FS) || defined(USB) +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif /* USB_OTG_FS || USB */ +#if defined(CEC) +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); +#endif /* CEC */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RCC */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h new file mode 100644 index 0000000..5f101d8 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h @@ -0,0 +1,1852 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_SYSTEM_H +#define __STM32F0xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Remap +* @{ +*/ +#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000U /*!< Main Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x00000000 */ +/** + * @} + */ + +#if defined(SYSCFG_CFGR1_IR_MOD) +/** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation + * @{ + */ +#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< Timer16 is selected as IR Modulation enveloppe source */ +#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< USART1 is selected as IR Modulation enveloppe source */ +#define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< USART4 is selected as IR Modulation enveloppe source */ +/** + * @} + */ + +#endif /* SYSCFG_CFGR1_IR_MOD */ + +#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) || defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) || defined(SYSCFG_CFGR1_USART2_DMA_RMP) || defined(SYSCFG_CFGR1_USART3_DMA_RMP) +/** @defgroup SYSTEM_LL_EC_USART1TX_RMP SYSCFG USART DMA Remap + * @{ + */ +#if defined (SYSCFG_CFGR1_USART1TX_DMA_RMP) +#define LL_SYSCFG_USART1TX_RMP_DMA1CH2 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART1_TX DMA request mapped on DMA channel 2U */ +#define LL_SYSCFG_USART1TX_RMP_DMA1CH4 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1_TX DMA request mapped on DMA channel 4U */ +#endif /*SYSCFG_CFGR1_USART1TX_DMA_RMP*/ +#if defined (SYSCFG_CFGR1_USART1RX_DMA_RMP) +#define LL_SYSCFG_USART1RX_RMP_DMA1CH3 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART1_RX DMA request mapped on DMA channel 3U */ +#define LL_SYSCFG_USART1RX_RMP_DMA1CH5 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1_RX DMA request mapped on DMA channel 5 */ +#endif /*SYSCFG_CFGR1_USART1RX_DMA_RMP*/ +#if defined (SYSCFG_CFGR1_USART2_DMA_RMP) +#define LL_SYSCFG_USART2_RMP_DMA1CH54 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4U respectively */ +#define LL_SYSCFG_USART2_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively */ +#endif /*SYSCFG_CFGR1_USART2_DMA_RMP*/ +#if defined (SYSCFG_CFGR1_USART3_DMA_RMP) +#define LL_SYSCFG_USART3_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively */ +#define LL_SYSCFG_USART3_RMP_DMA1CH32 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 3U and 2U respectively */ +#endif /* SYSCFG_CFGR1_USART3_DMA_RMP */ +/** + * @} + */ +#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP || SYSCFG_CFGR1_USART1RX_DMA_RMP || SYSCFG_CFGR1_USART2_DMA_RMP || SYSCFG_CFGR1_USART3_DMA_RMP */ + +#if defined (SYSCFG_CFGR1_SPI2_DMA_RMP) +/** @defgroup SYSTEM_LL_EC_SPI2_RMP_DMA1 SYSCFG SPI2 DMA Remap + * @{ + */ +#define LL_SYSCFG_SPI2_RMP_DMA1_CH45 (uint32_t)0x00000000U /*!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4U and 5 respectively */ +#define LL_SYSCFG_SPI2_RMP_DMA1_CH67 SYSCFG_CFGR1_SPI2_DMA_RMP /*!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively */ +/** + * @} + */ + +#endif /*SYSCFG_CFGR1_SPI2_DMA_RMP*/ + +#if defined (SYSCFG_CFGR1_I2C1_DMA_RMP) +/** @defgroup SYSTEM_LL_EC_I2C1_RMP_DMA1 SYSCFG I2C1 DMA Remap + * @{ + */ +#define LL_SYSCFG_I2C1_RMP_DMA1_CH32 (uint32_t)0x00000000U /*!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3U and 2U respectively */ +#define LL_SYSCFG_I2C1_RMP_DMA1_CH76 SYSCFG_CFGR1_I2C1_DMA_RMP /*!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively */ +/** + * @} + */ + +#endif /*SYSCFG_CFGR1_I2C1_DMA_RMP*/ + +#if defined(SYSCFG_CFGR1_ADC_DMA_RMP) +/** @defgroup SYSTEM_LL_EC_ADC1_RMP_DMA1 SYSCFG ADC1 DMA Remap + * @{ + */ +#define LL_SYSCFG_ADC1_RMP_DMA1_CH1 (uint32_t)0x00000000U /*!< ADC DMA request mapped on DMA channel 1U */ +#define LL_SYSCFG_ADC1_RMP_DMA1_CH2 SYSCFG_CFGR1_ADC_DMA_RMP /*!< ADC DMA request mapped on DMA channel 2U */ +/** + * @} + */ + +#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) || defined(SYSCFG_CFGR1_TIM17_DMA_RMP) || defined(SYSCFG_CFGR1_TIM1_DMA_RMP) || defined(SYSCFG_CFGR1_TIM2_DMA_RMP) || defined(SYSCFG_CFGR1_TIM3_DMA_RMP) +/** @defgroup SYSTEM_LL_EC_TIM16_RMP_DMA1 SYSCFG TIM DMA Remap + * @{ + */ +#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) +#if defined (SYSCFG_CFGR1_TIM16_DMA_RMP2) +#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 (((SYSCFG_CFGR1_TIM16_DMA_RMP | SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 */ +#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 (((SYSCFG_CFGR1_TIM16_DMA_RMP | SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 */ +#define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP2 >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6 */ +#else +#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 */ +#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 */ +#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP2 */ +#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP */ +#if defined(SYSCFG_CFGR1_TIM17_DMA_RMP) +#if defined (SYSCFG_CFGR1_TIM17_DMA_RMP2) +#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 (((SYSCFG_CFGR1_TIM17_DMA_RMP | SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 */ +#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 (((SYSCFG_CFGR1_TIM17_DMA_RMP | SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 */ +#define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP2 >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7 */ +#else +#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 */ +#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 */ +#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP2 */ +#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP */ +#if defined (SYSCFG_CFGR1_TIM1_DMA_RMP) +#define LL_SYSCFG_TIM1_RMP_DMA1_CH234 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMAchannel 2, 3 and 4 respectively */ +#define LL_SYSCFG_TIM1_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ +#endif /*SYSCFG_CFGR1_TIM1_DMA_RMP*/ +#if defined (SYSCFG_CFGR1_TIM2_DMA_RMP) +#define LL_SYSCFG_TIM2_RMP_DMA1_CH34 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively */ +#define LL_SYSCFG_TIM2_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ +#endif /*SYSCFG_CFGR1_TIM2_DMA_RMP*/ +#if defined (SYSCFG_CFGR1_TIM3_DMA_RMP) +#define LL_SYSCFG_TIM3_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 */ +#define LL_SYSCFG_TIM3_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 */ +#endif /*SYSCFG_CFGR1_TIM3_DMA_RMP*/ +/** + * @} + */ + +#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP || SYSCFG_CFGR1_TIM17_DMA_RMP || SYSCFG_CFGR1_TIM1_DMA_RMP || SYSCFG_CFGR1_TIM2_DMA_RMP || SYSCFG_CFGR1_TIM3_DMA_RMP */ + +/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + * @{ + */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< I2C PB6 Fast mode plus */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< I2C PB7 Fast mode plus */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< I2C PB8 Fast mode plus */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< I2C PB9 Fast mode plus */ +#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */ +#endif /*SYSCFG_CFGR1_I2C_FMP_I2C1*/ +#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable I2C2 Fast mode plus */ +#endif /*SYSCFG_CFGR1_I2C_FMP_I2C2*/ +#if defined(SYSCFG_CFGR1_I2C_FMP_PA9) +#define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */ +#endif /*SYSCFG_CFGR1_I2C_FMP_PA9*/ +#if defined(SYSCFG_CFGR1_I2C_FMP_PA10) +#define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */ +#endif /*SYSCFG_CFGR1_I2C_FMP_PA10*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT + * @{ + */ +#define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /*!< EXTI PORT A */ +#define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /*!< EXTI PORT B */ +#define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /*!< EXTI PORT C */ +#if defined(GPIOD_BASE) +#define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /*!< EXTI PORT D */ +#endif /*GPIOD_BASE*/ +#if defined(GPIOE_BASE) +#define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /*!< EXTI PORT E */ +#endif /*GPIOE_BASE*/ +#define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /*!< EXTI PORT F */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE + * @{ + */ +#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0U << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(4U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(8U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(12U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0U << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(4U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(8U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(12U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0U << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(4U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(8U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(12U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0U << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(4U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(8U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(12U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#if defined(SYSCFG_CFGR2_PVD_LOCK) +#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection + with TIM1/15/16U/17 Break Input and also + the PVDE and PLS bits of the Power Control Interface */ +#endif /*SYSCFG_CFGR2_PVD_LOCK*/ +#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal + with Break Input of TIM1/15/16/17 */ +#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of + CortexM0 with Break Input of TIM1/15/16/17 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ +#endif /*DBGMCU_APB1_FZ_DBG_TIM2_STOP*/ +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ +#endif /*DBGMCU_APB1_FZ_DBG_TIM6_STOP*/ +#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ +#endif /*DBGMCU_APB1_FZ_DBG_TIM7_STOP*/ +#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Calendar frozen when core is halted */ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /*!< CAN debug stopped when Core is halted */ +#endif /*DBGMCU_APB1_FZ_DBG_CAN_STOP*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1 GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ +#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) +#define LL_DBGMCU_APB1_GRP2_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */ +#endif /*DBGMCU_APB2_FZ_DBG_TIM15_STOP*/ +#define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ + +/** + * @brief Set memory mapping at address 0x00000000 + * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory + * @param Memory This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory); +} + +/** + * @brief Get memory mapping at address 0x00000000 + * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)); +} + +#if defined(SYSCFG_CFGR1_IR_MOD) +/** + * @brief Set IR Modulation Envelope signal source. + * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_IR_MOD_TIM16 + * @arg @ref LL_SYSCFG_IR_MOD_USART1 + * @arg @ref LL_SYSCFG_IR_MOD_USART4 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source); +} + +/** + * @brief Get IR Modulation Envelope signal source. + * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_IR_MOD_TIM16 + * @arg @ref LL_SYSCFG_IR_MOD_USART1 + * @arg @ref LL_SYSCFG_IR_MOD_USART4 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD)); +} +#endif /* SYSCFG_CFGR1_IR_MOD */ + +#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) || defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) || defined(SYSCFG_CFGR1_USART2_DMA_RMP) || defined(SYSCFG_CFGR1_USART3_DMA_RMP) +/** + * @brief Set DMA request remapping bits for USART + * @rmtoll SYSCFG_CFGR1 USART1TX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n + * SYSCFG_CFGR1 USART1RX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n + * SYSCFG_CFGR1 USART2_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n + * SYSCFG_CFGR1 USART3_DMA_RMP LL_SYSCFG_SetRemapDMA_USART + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH2 (*) + * @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH4 (*) + * @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH3 (*) + * @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH5 (*) + * @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH54 (*) + * @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH67 (*) + * @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH67 (*) + * @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH32 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_USART(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U)); +} +#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP || SYSCFG_CFGR1_USART1RX_DMA_RMP || SYSCFG_CFGR1_USART2_DMA_RMP || SYSCFG_CFGR1_USART3_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_SPI2_DMA_RMP) +/** + * @brief Set DMA request remapping bits for SPI + * @rmtoll SYSCFG_CFGR1 SPI2_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH45 + * @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH67 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_SPI2_DMA_RMP, Remap); +} +#endif /* SYSCFG_CFGR1_SPI2_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_I2C1_DMA_RMP) +/** + * @brief Set DMA request remapping bits for I2C + * @rmtoll SYSCFG_CFGR1 I2C1_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH32 + * @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH76 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_I2C1_DMA_RMP, Remap); +} +#endif /* SYSCFG_CFGR1_I2C1_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_ADC_DMA_RMP) +/** + * @brief Set DMA request remapping bits for ADC + * @rmtoll SYSCFG_CFGR1 ADC_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH1 + * @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH2 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ADC_DMA_RMP, Remap); +} +#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) || defined(SYSCFG_CFGR1_TIM17_DMA_RMP) || defined(SYSCFG_CFGR1_TIM1_DMA_RMP) || defined(SYSCFG_CFGR1_TIM2_DMA_RMP) || defined(SYSCFG_CFGR1_TIM3_DMA_RMP) +/** + * @brief Set DMA request remapping bits for TIM + * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM16_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM17_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM3_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 (*) + * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH4 (*) + * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6 (*) + * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 (*) + * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH2 (*) + * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7 (*) + * @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH234 (*) + * @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH6 (*) + * @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH34 (*) + * @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH7 (*) + * @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH4 (*) + * @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH6 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U)); +} +#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP || SYSCFG_CFGR1_TIM17_DMA_RMP || SYSCFG_CFGR1_TIM1_DMA_RMP || SYSCFG_CFGR1_TIM2_DMA_RMP || SYSCFG_CFGR1_TIM3_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) +/** + * @brief Enable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either + * PA9/10 or PA11/12 pin pair on small pin-count packages) + * @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_EnablePinRemap + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnablePinRemap(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP); +} + +/** + * @brief Disable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either + * PA9/10 or PA11/12 pin pair on small pin-count packages) + * @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_DisablePinRemap + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisablePinRemap(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP); +} +#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD (*) + * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + * @arg @ref LL_SYSCFG_EXTI_PORTF + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], SYSCFG_EXTICR1_EXTI0 << (Line >> 16), Port << (Line >> 16)); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD (*) + * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + * @arg @ref LL_SYSCFG_EXTI_PORTF + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16))) >> (Line >> 16)); +} + +#if defined(SYSCFG_ITLINE0_SR_EWDG) +/** + * @brief Check if Window watchdog interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG)); +} +#endif /* SYSCFG_ITLINE0_SR_EWDG */ + +#if defined(SYSCFG_ITLINE1_SR_PVDOUT) +/** + * @brief Check if PVD supply monitoring interrupt occurred or not (EXTI line 16). + * @rmtoll SYSCFG_ITLINE1 SR_PVDOUT LL_SYSCFG_IsActiveFlag_PVDOUT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT)); +} +#endif /* SYSCFG_ITLINE1_SR_PVDOUT */ + +#if defined(SYSCFG_ITLINE1_SR_VDDIO2) +/** + * @brief Check if VDDIO2 supply monitoring interrupt occurred or not (EXTI line 31). + * @rmtoll SYSCFG_ITLINE1 SR_VDDIO2 LL_SYSCFG_IsActiveFlag_VDDIO2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VDDIO2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_VDDIO2) == (SYSCFG_ITLINE1_SR_VDDIO2)); +} +#endif /* SYSCFG_ITLINE1_SR_VDDIO2 */ + +#if defined(SYSCFG_ITLINE2_SR_RTC_WAKEUP) +/** + * @brief Check if RTC Wake Up interrupt occurred or not (EXTI line 20). + * @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP LL_SYSCFG_IsActiveFlag_RTC_WAKEUP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_WAKEUP) == (SYSCFG_ITLINE2_SR_RTC_WAKEUP)); +} +#endif /* SYSCFG_ITLINE2_SR_RTC_WAKEUP */ + +#if defined(SYSCFG_ITLINE2_SR_RTC_TSTAMP) +/** + * @brief Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 19). + * @rmtoll SYSCFG_ITLINE2 SR_RTC_TSTAMP LL_SYSCFG_IsActiveFlag_RTC_TSTAMP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_TSTAMP(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_TSTAMP) == (SYSCFG_ITLINE2_SR_RTC_TSTAMP)); +} +#endif /* SYSCFG_ITLINE2_SR_RTC_TSTAMP */ + +#if defined(SYSCFG_ITLINE2_SR_RTC_ALRA) +/** + * @brief Check if RTC Alarm interrupt occurred or not (EXTI line 17). + * @rmtoll SYSCFG_ITLINE2 SR_RTC_ALRA LL_SYSCFG_IsActiveFlag_RTC_ALRA + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_ALRA(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_ALRA) == (SYSCFG_ITLINE2_SR_RTC_ALRA)); +} +#endif /* SYSCFG_ITLINE2_SR_RTC_ALRA */ + +#if defined(SYSCFG_ITLINE3_SR_FLASH_ITF) +/** + * @brief Check if Flash interface interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF)); +} +#endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */ + +#if defined(SYSCFG_ITLINE4_SR_CRS) +/** + * @brief Check if Clock recovery system interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS)); +} +#endif /* SYSCFG_ITLINE4_SR_CRS */ + +#if defined(SYSCFG_ITLINE4_SR_CLK_CTRL) +/** + * @brief Check if Reset and clock control interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTRL)); +} +#endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */ + +#if defined(SYSCFG_ITLINE5_SR_EXTI0) +/** + * @brief Check if EXTI line 0 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0)); +} +#endif /* SYSCFG_ITLINE5_SR_EXTI0 */ + +#if defined(SYSCFG_ITLINE5_SR_EXTI1) +/** + * @brief Check if EXTI line 1 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1)); +} +#endif /* SYSCFG_ITLINE5_SR_EXTI1 */ + +#if defined(SYSCFG_ITLINE6_SR_EXTI2) +/** + * @brief Check if EXTI line 2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2)); +} +#endif /* SYSCFG_ITLINE6_SR_EXTI2 */ + +#if defined(SYSCFG_ITLINE6_SR_EXTI3) +/** + * @brief Check if EXTI line 3 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3)); +} +#endif /* SYSCFG_ITLINE6_SR_EXTI3 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI4) +/** + * @brief Check if EXTI line 4 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI4 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI5) +/** + * @brief Check if EXTI line 5 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI5 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI6) +/** + * @brief Check if EXTI line 6 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI6 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI7) +/** + * @brief Check if EXTI line 7 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI7 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI8) +/** + * @brief Check if EXTI line 8 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI8 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI9) +/** + * @brief Check if EXTI line 9 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI9 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI10) +/** + * @brief Check if EXTI line 10 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI10 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI11) +/** + * @brief Check if EXTI line 11 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI11 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI12) +/** + * @brief Check if EXTI line 12 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI12 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI13) +/** + * @brief Check if EXTI line 13 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI13 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI14) +/** + * @brief Check if EXTI line 14 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI14 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI15) +/** + * @brief Check if EXTI line 15 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI15 */ + +#if defined(SYSCFG_ITLINE8_SR_TSC_EOA) +/** + * @brief Check if Touch sensing controller end of acquisition interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE8 SR_TSC_EOA LL_SYSCFG_IsActiveFlag_TSC_EOA + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_EOA(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_EOA) == (SYSCFG_ITLINE8_SR_TSC_EOA)); +} +#endif /* SYSCFG_ITLINE8_SR_TSC_EOA */ + +#if defined(SYSCFG_ITLINE8_SR_TSC_MCE) +/** + * @brief Check if Touch sensing controller max counterror interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE8 SR_TSC_MCE LL_SYSCFG_IsActiveFlag_TSC_MCE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_MCE(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_MCE) == (SYSCFG_ITLINE8_SR_TSC_MCE)); +} +#endif /* SYSCFG_ITLINE8_SR_TSC_MCE */ + +#if defined(SYSCFG_ITLINE9_SR_DMA1_CH1) +/** + * @brief Check if DMA1 channel 1 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1)); +} +#endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */ + +#if defined(SYSCFG_ITLINE10_SR_DMA1_CH2) +/** + * @brief Check if DMA1 channel 2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2)); +} +#endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */ + +#if defined(SYSCFG_ITLINE10_SR_DMA1_CH3) +/** + * @brief Check if DMA1 channel 3 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3)); +} +#endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */ + +#if defined(SYSCFG_ITLINE10_SR_DMA2_CH1) +/** + * @brief Check if DMA2 channel 1 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH1 LL_SYSCFG_IsActiveFlag_DMA2_CH1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH1) == (SYSCFG_ITLINE10_SR_DMA2_CH1)); +} +#endif /* SYSCFG_ITLINE10_SR_DMA2_CH1 */ + +#if defined(SYSCFG_ITLINE10_SR_DMA2_CH2) +/** + * @brief Check if DMA2 channel 2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH2 LL_SYSCFG_IsActiveFlag_DMA2_CH2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH2) == (SYSCFG_ITLINE10_SR_DMA2_CH2)); +} +#endif /* SYSCFG_ITLINE10_SR_DMA2_CH2 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH4) +/** + * @brief Check if DMA1 channel 4 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH5) +/** + * @brief Check if DMA1 channel 5 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6) +/** + * @brief Check if DMA1 channel 6 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7) +/** + * @brief Check if DMA1 channel 7 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA2_CH3) +/** + * @brief Check if DMA2 channel 3 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3 LL_SYSCFG_IsActiveFlag_DMA2_CH3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2_CH3)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA2_CH3 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA2_CH4) +/** + * @brief Check if DMA2 channel 4 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4 LL_SYSCFG_IsActiveFlag_DMA2_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2_CH4)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA2_CH4 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA2_CH5) +/** + * @brief Check if DMA2 channel 5 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5 LL_SYSCFG_IsActiveFlag_DMA2_CH5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2_CH5)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA2_CH5 */ + +#if defined(SYSCFG_ITLINE12_SR_ADC) +/** + * @brief Check if ADC interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC)); +} +#endif /* SYSCFG_ITLINE12_SR_ADC */ + +#if defined(SYSCFG_ITLINE12_SR_COMP1) +/** + * @brief Check if Comparator 1 interrupt occurred or not (EXTI line 21). + * @rmtoll SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1)); +} +#endif /* SYSCFG_ITLINE12_SR_COMP1 */ + +#if defined(SYSCFG_ITLINE12_SR_COMP2) +/** + * @brief Check if Comparator 2 interrupt occurred or not (EXTI line 22). + * @rmtoll SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2)); +} +#endif /* SYSCFG_ITLINE12_SR_COMP2 */ + +#if defined(SYSCFG_ITLINE13_SR_TIM1_BRK) +/** + * @brief Check if Timer 1 break interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK)); +} +#endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */ + +#if defined(SYSCFG_ITLINE13_SR_TIM1_UPD) +/** + * @brief Check if Timer 1 update interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD)); +} +#endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */ + +#if defined(SYSCFG_ITLINE13_SR_TIM1_TRG) +/** + * @brief Check if Timer 1 trigger interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG)); +} +#endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */ + +#if defined(SYSCFG_ITLINE13_SR_TIM1_CCU) +/** + * @brief Check if Timer 1 commutation interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU)); +} +#endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */ + +#if defined(SYSCFG_ITLINE14_SR_TIM1_CC) +/** + * @brief Check if Timer 1 capture compare interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC)); +} +#endif /* SYSCFG_ITLINE14_SR_TIM1_CC */ + +#if defined(SYSCFG_ITLINE15_SR_TIM2_GLB) +/** + * @brief Check if Timer 2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2_GLB) == (SYSCFG_ITLINE15_SR_TIM2_GLB)); +} +#endif /* SYSCFG_ITLINE15_SR_TIM2_GLB */ + +#if defined(SYSCFG_ITLINE16_SR_TIM3_GLB) +/** + * @brief Check if Timer 3 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB)); +} +#endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */ + +#if defined(SYSCFG_ITLINE17_SR_DAC) +/** + * @brief Check if DAC underrun interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE17 SR_DAC LL_SYSCFG_IsActiveFlag_DAC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC)); +} +#endif /* SYSCFG_ITLINE17_SR_DAC */ + +#if defined(SYSCFG_ITLINE17_SR_TIM6_GLB) +/** + * @brief Check if Timer 6 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB LL_SYSCFG_IsActiveFlag_TIM6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6_GLB) == (SYSCFG_ITLINE17_SR_TIM6_GLB)); +} +#endif /* SYSCFG_ITLINE17_SR_TIM6_GLB */ + +#if defined(SYSCFG_ITLINE18_SR_TIM7_GLB) +/** + * @brief Check if Timer 7 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB LL_SYSCFG_IsActiveFlag_TIM7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7_GLB) == (SYSCFG_ITLINE18_SR_TIM7_GLB)); +} +#endif /* SYSCFG_ITLINE18_SR_TIM7_GLB */ + +#if defined(SYSCFG_ITLINE19_SR_TIM14_GLB) +/** + * @brief Check if Timer 14 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM14_GLB)); +} +#endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */ + +#if defined(SYSCFG_ITLINE20_SR_TIM15_GLB) +/** + * @brief Check if Timer 15 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == (SYSCFG_ITLINE20_SR_TIM15_GLB)); +} +#endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */ + +#if defined(SYSCFG_ITLINE21_SR_TIM16_GLB) +/** + * @brief Check if Timer 16 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM16_GLB)); +} +#endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */ + +#if defined(SYSCFG_ITLINE22_SR_TIM17_GLB) +/** + * @brief Check if Timer 17 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM17_GLB)); +} +#endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */ + +#if defined(SYSCFG_ITLINE23_SR_I2C1_GLB) +/** + * @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23. + * @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB)); +} +#endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */ + +#if defined(SYSCFG_ITLINE24_SR_I2C2_GLB) +/** + * @brief Check if I2C2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2_GLB)); +} +#endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */ + +#if defined(SYSCFG_ITLINE25_SR_SPI1) +/** + * @brief Check if SPI1 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1)); +} +#endif /* SYSCFG_ITLINE25_SR_SPI1 */ + +#if defined(SYSCFG_ITLINE26_SR_SPI2) +/** + * @brief Check if SPI2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE26 SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2)); +} +#endif /* SYSCFG_ITLINE26_SR_SPI2 */ + +#if defined(SYSCFG_ITLINE27_SR_USART1_GLB) +/** + * @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25. + * @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_USART1_GLB)); +} +#endif /* SYSCFG_ITLINE27_SR_USART1_GLB */ + +#if defined(SYSCFG_ITLINE28_SR_USART2_GLB) +/** + * @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26. + * @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_USART2_GLB)); +} +#endif /* SYSCFG_ITLINE28_SR_USART2_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART3_GLB) +/** + * @brief Check if USART3 interrupt occurred or not, combined with EXTI line 28. + * @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == (SYSCFG_ITLINE29_SR_USART3_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART3_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART4_GLB) +/** + * @brief Check if USART4 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == (SYSCFG_ITLINE29_SR_USART4_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART4_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART5_GLB) +/** + * @brief Check if USART5 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE29 SR_USART5_GLB LL_SYSCFG_IsActiveFlag_USART5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART5_GLB) == (SYSCFG_ITLINE29_SR_USART5_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART5_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART6_GLB) +/** + * @brief Check if USART6 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE29 SR_USART6_GLB LL_SYSCFG_IsActiveFlag_USART6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART6_GLB) == (SYSCFG_ITLINE29_SR_USART6_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART6_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART7_GLB) +/** + * @brief Check if USART7 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE29 SR_USART7_GLB LL_SYSCFG_IsActiveFlag_USART7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART7(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART7_GLB) == (SYSCFG_ITLINE29_SR_USART7_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART7_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART8_GLB) +/** + * @brief Check if USART8 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE29 SR_USART8_GLB LL_SYSCFG_IsActiveFlag_USART8 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART8(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART8_GLB) == (SYSCFG_ITLINE29_SR_USART8_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART8_GLB */ + +#if defined(SYSCFG_ITLINE30_SR_CAN) +/** + * @brief Check if CAN interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE30 SR_CAN LL_SYSCFG_IsActiveFlag_CAN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CAN(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CAN) == (SYSCFG_ITLINE30_SR_CAN)); +} +#endif /* SYSCFG_ITLINE30_SR_CAN */ + +#if defined(SYSCFG_ITLINE30_SR_CEC) +/** + * @brief Check if CEC interrupt occurred or not, combined with EXTI line 27. + * @rmtoll SYSCFG_ITLINE30 SR_CEC LL_SYSCFG_IsActiveFlag_CEC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CEC) == (SYSCFG_ITLINE30_SR_CEC)); +} +#endif /* SYSCFG_ITLINE30_SR_CEC */ + +/** + * @brief Set connections to TIMx Break inputs + * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +{ +#if defined(SYSCFG_CFGR2_PVD_LOCK) + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break); +#else + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK, Break); +#endif /*SYSCFG_CFGR2_PVD_LOCK*/ +} + +/** + * @brief Get connections to TIMx Break inputs + * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +{ +#if defined(SYSCFG_CFGR2_PVD_LOCK) + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, + SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)); +#else + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK)); +#endif /*SYSCFG_CFGR2_PVD_LOCK*/ +} + +/** + * @brief Check if SRAM parity error detected + * @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_IsActiveFlag_SP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void) +{ + return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF) == (SYSCFG_CFGR2_SRAM_PEF)); +} + +/** + * @brief Clear SRAM parity error flag + * @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_ClearFlag_SP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) +{ + SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF); +} + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @note For STM32F03x devices, the device ID is 0x444 + * @note For STM32F04x devices, the device ID is 0x445. + * @note For STM32F05x devices, the device ID is 0x440 + * @note For STM32F07x devices, the device ID is 0x448 + * @note For STM32F09x devices, the device ID is 0x442 + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + For example, it is read as 0x1000 for Revision 1.0. + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Freeze APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZ, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZ, Periphs); +} +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Prefetch + * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); +} + +/** + * @brief Disable Prefetch + * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); +} + +/** + * @brief Check if Prefetch buffer is enabled + * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) +{ + return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); +} + + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_SYSTEM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h new file mode 100644 index 0000000..3b7c020 --- /dev/null +++ b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h @@ -0,0 +1,274 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_UTILS_H +#define __STM32F0xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock. + This parameter can be a value of @ref RCC_LL_EC_PLL_MUL + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock. + This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +#else + uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source. + This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); +} + + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +#if defined(FLASH_ACR_LATENCY) +ErrorStatus LL_SetFlashLatency(uint32_t Frequency); +#endif /* FLASH_ACR_LATENCY */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +#if defined(RCC_CFGR_SW_HSI48) +ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +#endif /*RCC_CFGR_SW_HSI48*/ +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_UTILS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c new file mode 100644 index 0000000..ef4d16d --- /dev/null +++ b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c @@ -0,0 +1,223 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_exti.c + * @author MCD Application Team + * @brief EXTI LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_ll_exti.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Private_Macros + * @{ + */ + +#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) + +#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ + || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ + || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) + + +#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the EXTI registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are de-initialized + * - ERROR: not applicable + */ +uint32_t LL_EXTI_DeInit(void) +{ + /* Interrupt mask register set to default reset values */ +#if defined(STM32F030x6) || defined(STM32F031x6) ||defined(STM32F038xx) + LL_EXTI_WriteReg(IMR, 0x0FF40000U); +#elif defined(STM32F070x6) || defined(STM32F042x6) || defined(STM32F048xx) + LL_EXTI_WriteReg(IMR, 0x7FF40000U); +#elif defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) + LL_EXTI_WriteReg(IMR, 0x0F940000U); +#else + LL_EXTI_WriteReg(IMR, 0x7F840000U); +#endif + /* Event mask register set to default reset values */ + LL_EXTI_WriteReg(EMR, 0x00000000U); + /* Rising Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(RTSR, 0x00000000U); + /* Falling Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(FTSR, 0x00000000U); + /* Software interrupt event register set to default reset values */ + LL_EXTI_WriteReg(SWIER, 0x00000000U); + /* Pending register clear */ + LL_EXTI_WriteReg(PR, 0x007BFFFFU); + + return SUCCESS; +} + +/** + * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. + * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are initialized + * - ERROR: not applicable + */ +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + ErrorStatus status = SUCCESS; + /* Check the parameters */ + assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); + assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); + + /* ENABLE LineCommand */ + if (EXTI_InitStruct->LineCommand != DISABLE) + { + assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); + + /* Configure EXTI Lines in range from 0 to 31 */ + if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) + { + switch (EXTI_InitStruct->Mode) + { + case LL_EXTI_MODE_IT: + /* First Disable Event on provided Lines */ + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_EVENT: + /* First Disable IT on provided Lines */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Event on provided Lines */ + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_IT_EVENT: + /* Directly Enable IT & Event on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + { + switch (EXTI_InitStruct->Trigger) + { + case LL_EXTI_TRIGGER_RISING: + /* First Disable Falling Trigger on provided Lines */ + LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Rising Trigger on provided Lines */ + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_FALLING: + /* First Disable Rising Trigger on provided Lines */ + LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_RISING_FALLING: + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + } + } + } + /* DISABLE LineCommand */ + else + { + /* De-configure EXTI Lines in range from 0 to 31 */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + } + return status; +} + +/** + * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. + * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval None + */ +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; + EXTI_InitStruct->LineCommand = DISABLE; + EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; + EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (EXTI) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c new file mode 100644 index 0000000..83d14aa --- /dev/null +++ b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c @@ -0,0 +1,277 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_gpio.c + * @author MCD Application Team + * @brief GPIO LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_ll_gpio.h" +#include "stm32f0xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) + +/** @addtogroup GPIO_LL + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + * range of the shift operator in following API : + * LL_GPIO_Init + * LL_GPIO_DeInit + * LL_GPIO_SetPinMode + * LL_GPIO_GetPinMode + * LL_GPIO_SetPinSpeed + * LL_GPIO_GetPinSpeed + * LL_GPIO_SetPinPull + * LL_GPIO_GetPinPull + * LL_GPIO_GetAFPin_0_7 + * LL_GPIO_SetAFPin_0_7 + * LL_GPIO_SetAFPin_8_15 + * LL_GPIO_GetAFPin_8_15 + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Private_Macros + * @{ + */ +#define IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) + +#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ + ((__VALUE__) == LL_GPIO_MODE_ANALOG)) + +#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ + ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) + +#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)) + +#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ + ((__VALUE__) == LL_GPIO_PULL_UP) ||\ + ((__VALUE__) == LL_GPIO_PULL_DOWN)) + +#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ + ((__VALUE__) == LL_GPIO_AF_1 ) ||\ + ((__VALUE__) == LL_GPIO_AF_2 ) ||\ + ((__VALUE__) == LL_GPIO_AF_3 ) ||\ + ((__VALUE__) == LL_GPIO_AF_4 ) ||\ + ((__VALUE__) == LL_GPIO_AF_5 ) ||\ + ((__VALUE__) == LL_GPIO_AF_6 ) ||\ + ((__VALUE__) == LL_GPIO_AF_7 )) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize GPIO registers (Registers restored to their default values). + * @param GPIOx GPIO Port + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are de-initialized + * - ERROR: Wrong GPIO Port + */ +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Force and Release reset on clock of GPIOx Port */ + if (GPIOx == GPIOA) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA); + } + else if (GPIOx == GPIOB) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB); + } + else if (GPIOx == GPIOC) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC); + } +#if defined(GPIOD) + else if (GPIOx == GPIOD) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD); + } +#endif /* GPIOD */ +#if defined(GPIOE) + else if (GPIOx == GPIOE) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE); + } +#endif /* GPIOE */ +#if defined(GPIOF) + else if (GPIOx == GPIOF) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF); + } +#endif /* GPIOF */ + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. + * @param GPIOx GPIO Port + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * that contains the configuration information for the specified GPIO peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content + * - ERROR: Not applicable + */ +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t pinpos; + uint32_t currentpin; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); + assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); + + /* ------------------------- Configure the port pins ---------------- */ + /* Initialize pinpos on first pin set */ + pinpos = 0; + + /* Configure the port pins */ + while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u) + { + /* Get current io position */ + currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos); + + if (currentpin != 0x00u) + { + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) + { + /* Check Speed mode parameters */ + assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); + + /* Speed mode configuration */ + LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); + } + + /* Pull-up Pull down resistor configuration*/ + LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); + + if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) + { + /* Check Alternate parameter */ + assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); + + /* Speed mode configuration */ + if (currentpin < LL_GPIO_PIN_8) + { + LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + else + { + LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + } + + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); + } + pinpos++; + } + + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; + GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct->Alternate = LL_GPIO_AF_0; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c new file mode 100644 index 0000000..0f841ae --- /dev/null +++ b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c @@ -0,0 +1,86 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_pwr.c + * @author MCD Application Team + * @brief PWR LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_ll_pwr.h" +#include "stm32f0xx_ll_bus.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_LL_Exported_Functions + * @{ + */ + +/** @addtogroup PWR_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the PWR registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PWR registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_PWR_DeInit(void) +{ + /* Force reset of PWR clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR); + + /* Release reset of PWR clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR); + + return SUCCESS; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined(PWR) */ +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c new file mode 100644 index 0000000..94c157e --- /dev/null +++ b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c @@ -0,0 +1,609 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_rcc.c + * @author MCD Application Team + * @brief RCC LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_ll_rcc.h" +#ifdef USE_FULL_ASSERT + #include "stm32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_LL_Private_Macros + * @{ + */ +#if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) +#elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) +#elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) +#else +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE)) +#endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */ + +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) + +#if defined(USB) +#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) +#endif /* USB */ + +#if defined(CEC) +#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE)) +#endif /* CEC */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_LL_Private_Functions RCC Private functions + * @{ + */ +uint32_t RCC_GetSystemClockFreq(void); +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +uint32_t RCC_PLL_GetFreqDomain_SYS(void); +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_LL_EF_Init + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL OFF + * - AHB and APB1 prescaler set to 1. + * - CSS, MCO OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RCC registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_RCC_DeInit(void) +{ + __IO uint32_t vl_mask; + + /* Set HSION bit */ + LL_RCC_HSI_Enable(); + + /* Wait for HSI READY bit */ + while(LL_RCC_HSI_IsReady() != 1U) + {} + + /* Set HSITRIM bits to the reset value*/ + LL_RCC_HSI_SetCalibTrimming(0x10U); + + /* Reset SW, HPRE, PPRE and MCOSEL bits */ + vl_mask = 0xFFFFFFFFU; + CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCOSEL)); + + /* Write new value in CFGR register */ + LL_RCC_WriteReg(CFGR, vl_mask); + + /* Wait till system clock source is ready */ + while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) + {} + + /* Read CR register */ + vl_mask = LL_RCC_ReadReg(CR); + + /* Reset HSEON, CSSON, PLLON bits */ + CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON)); + + /* Write new value in CR register */ + LL_RCC_WriteReg(CR, vl_mask); + + /* Wait for PLL READY bit to be reset */ + while(LL_RCC_PLL_IsReady() != 0U) + {} + + /* Reset HSEBYP bit */ + LL_RCC_HSE_DisableBypass(); + + /* Reset CFGR register */ + LL_RCC_WriteReg(CFGR, 0x00000000U); + +#if defined(RCC_HSI48_SUPPORT) + /* Reset CR2 register */ + LL_RCC_WriteReg(CR2, 0x00000000U); + + /* Disable HSI48 */ + LL_RCC_HSI48_Disable(); + +#endif /*RCC_HSI48_SUPPORT*/ + /* Set HSI14TRIM/HSI14ON/HSI14DIS bits to the reset value*/ + LL_RCC_HSI14_SetCalibTrimming(0x10U); + LL_RCC_HSI14_Disable(); + LL_RCC_HSI14_EnableADCControl(); + + /* Reset CFGR2 register */ + LL_RCC_WriteReg(CFGR2, 0x00000000U); + + /* Reset CFGR3 register */ + LL_RCC_WriteReg(CFGR3, 0x00000000U); + + /* Clear pending flags */ +#if defined(RCC_HSI48_SUPPORT) + vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC |\ + LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_HSI48RDYC | LL_RCC_CIR_CSSC); +#else + vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC |\ + LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_CSSC); +#endif /* RCC_HSI48_SUPPORT */ + + /* Write new value in CIR register */ + LL_RCC_WriteReg(CIR, vl_mask); + + /* Disable all interrupts */ + LL_RCC_WriteReg(CIR, 0x00000000U); + + /* Clear reset flags */ + LL_RCC_ClearResetFlags(); + + return SUCCESS; +} + +/** + * @} + */ + +/** @addtogroup RCC_LL_EF_Get_Freq + * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks + * and different peripheral clocks available on the device. + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is PLL, function returns values based on + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * @note (**) HSI_VALUE is a defined constant but the real value may vary + * depending on the variations in voltage and temperature. + * @note (***) HSE_VALUE is a defined constant, user has to ensure that + * HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * @note The result of this function could be incorrect when using fractional + * value for HSE crystal. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * @{ + */ + +/** + * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks + * @note Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function + * must be called to update structure fields. Otherwise, any + * configuration based on this function will be incorrect. + * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies + * @retval None + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) +{ + /* Get SYSCLK frequency */ + RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); + + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); + + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); +} + +/** + * @brief Return USARTx clock frequency + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval USART clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) +{ + uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); +#if defined(RCC_CFGR3_USART1SW) + if (USARTxSource == LL_RCC_USART1_CLKSOURCE) + { + /* USART1CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /* RCC_CFGR3_USART1SW */ + +#if defined(RCC_CFGR3_USART2SW) + if (USARTxSource == LL_RCC_USART2_CLKSOURCE) + { + /* USART2CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /* RCC_CFGR3_USART2SW */ + +#if defined(RCC_CFGR3_USART3SW) + if (USARTxSource == LL_RCC_USART3_CLKSOURCE) + { + /* USART3CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + +#endif /* RCC_CFGR3_USART3SW */ + return usart_frequency; +} + +/** + * @brief Return I2Cx clock frequency + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @retval I2C clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready + */ +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) +{ + uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); + + /* I2C1 CLK clock frequency */ + if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) + { + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ + default: + if (LL_RCC_HSI_IsReady()) + { + i2c_frequency = HSI_VALUE; + } + break; + } + } + + return i2c_frequency; +} + +#if defined(USB) +/** + * @brief Return USBx clock frequency + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval USB clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) +{ + uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); + + /* USBCLK clock frequency */ + switch (LL_RCC_GetUSBClockSource(USBxSource)) + { + case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ + if (LL_RCC_PLL_IsReady()) + { + usb_frequency = RCC_PLL_GetFreqDomain_SYS(); + } + break; + +#if defined(RCC_CFGR3_USBSW_HSI48) + case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */ + default: + if (LL_RCC_HSI48_IsReady()) + { + usb_frequency = HSI48_VALUE; + } + break; +#else + case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */ + default: + usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; +#endif /* RCC_CFGR3_USBSW_HSI48 */ + } + + return usb_frequency; +} +#endif /* USB */ + +#if defined(CEC) +/** + * @brief Return CECx clock frequency + * @param CECxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval CEC clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready + */ +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) +{ + uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource)); + + /* CECCLK clock frequency */ + switch (LL_RCC_GetCECClockSource(CECxSource)) + { + case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */ + if (LL_RCC_HSI_IsReady()) + { + cec_frequency = HSI_VALUE / 244U; + } + break; + + case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */ + default: + if (LL_RCC_LSE_IsReady()) + { + cec_frequency = LSE_VALUE; + } + break; + } + + return cec_frequency; +} +#endif /* CEC */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_LL_Private_Functions + * @{ + */ + +/** + * @brief Return SYSTEM clock frequency + * @retval SYSTEM clock frequency (in Hz) + */ +uint32_t RCC_GetSystemClockFreq(void) +{ + uint32_t frequency = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (LL_RCC_GetSysClkSource()) + { + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + frequency = HSI_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + frequency = HSE_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ + frequency = RCC_PLL_GetFreqDomain_SYS(); + break; + +#if defined(RCC_HSI48_SUPPORT) + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI48:/* HSI48 used as system clock source */ + frequency = HSI48_VALUE; + break; +#endif /* RCC_HSI48_SUPPORT */ + + default: + frequency = HSI_VALUE; + break; + } + + return frequency; +} + +/** + * @brief Return HCLK clock frequency + * @param SYSCLK_Frequency SYSCLK clock frequency + * @retval HCLK clock frequency (in Hz) + */ +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +{ + /* HCLK clock frequency */ + return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); +} + +/** + * @brief Return PCLK1 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK1 clock frequency (in Hz) + */ +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK1 clock frequency */ + return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); +} +/** + * @brief Return PLL clock frequency used for system domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_SYS(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */ + + /* Get PLL source */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE; +#else + case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE / 2U; +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + break; + +#if defined(RCC_HSI48_SUPPORT) + case LL_RCC_PLLSOURCE_HSI48: /* HSI48 used as PLL clock source */ + pllinputfreq = HSI48_VALUE; + break; +#endif /* RCC_HSI48_SUPPORT */ + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + pllinputfreq = HSI_VALUE; +#else + pllinputfreq = HSI_VALUE / 2U; +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + break; + } +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv()); +#else + return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator()); +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c new file mode 100644 index 0000000..59a78ee --- /dev/null +++ b/bsl/makeLowLayer/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c @@ -0,0 +1,622 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_utils.c + * @author MCD Application Team + * @brief UTILS LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_ll_rcc.h" +#include "stm32f0xx_ll_utils.h" +#include "stm32f0xx_ll_system.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +/** @addtogroup UTILS_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Constants + * @{ + */ + +/* Defines used for PLL range */ +#define UTILS_PLL_OUTPUT_MIN 16000000U /*!< Frequency min for PLL output, in Hz */ +#define UTILS_PLL_OUTPUT_MAX 48000000U /*!< Frequency max for PLL output, in Hz */ + +/* Defines used for HSE range */ +#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ +#define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */ + +/* Defines used for FLASH latency according to SYSCLK Frequency */ +#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Macros + * @{ + */ +#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) + +#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_16)) + +#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_3) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_4) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_5) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_6) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_7) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_8) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_9) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_10) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_11) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_12) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_13) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_14) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_15) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_16)) + +#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16)) + +#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((UTILS_PLL_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)) + + +#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ + || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) + +#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Functions UTILS Private functions + * @{ + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +static ErrorStatus UTILS_PLL_IsBusy(void); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Exported_Functions + * @{ + */ + +/** @addtogroup UTILS_LL_EF_DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param HCLKFrequency HCLK frequency in Hz + * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq + * @retval None + */ +void LL_Init1msTick(uint32_t HCLKFrequency) +{ + /* Use frequency provided in argument */ + LL_InitTick(HCLKFrequency, 1000U); +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on SysTick counter flag + * @note When a RTOS is used, it is recommended to avoid using blocking delay + * and use rather osDelay service. + * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which + * will configure Systick to 1ms + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +void LL_mDelay(uint32_t Delay) +{ + __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + /* Add this code to indicate that local variable is not used */ + ((void)tmp); + + /* Add a period to guaranty minimum wait */ + if (Delay < LL_MAX_DELAY) + { + Delay++; + } + + while (Delay) + { + if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) + { + Delay--; + } + } +} + +/** + * @} + */ + +/** @addtogroup UTILS_EF_SYSTEM + * @brief System Configuration functions + * + @verbatim + =============================================================================== + ##### System Configuration functions ##### + =============================================================================== + [..] + System, AHB and APB buses clocks configuration + + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 48000000 Hz. + @endverbatim + @internal + Depending on the SYSCLK frequency, the flash latency should be adapted accordingly: + (++) +-----------------------------------------------+ + (++) | Latency | SYSCLK clock frequency (MHz) | + (++) |---------------|-------------------------------| + (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | + (++) |---------------|-------------------------------| + (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | + (++) +-----------------------------------------------+ + @endinternal + * @{ + */ + +/** + * @brief This function sets directly SystemCoreClock CMSIS variable. + * @note Variable can be calculated also through SystemCoreClockUpdate function. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @retval None + */ +void LL_SetSystemCoreClock(uint32_t HCLKFrequency) +{ + /* HCLK clock frequency */ + SystemCoreClock = HCLKFrequency; +} + +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @param Frequency SYSCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +#if defined(FLASH_ACR_LATENCY) +ErrorStatus LL_SetFlashLatency(uint32_t Frequency) +{ + uint32_t timeout; + uint32_t getlatency; + uint32_t latency; + ErrorStatus status = SUCCESS; + + /* Frequency cannot be equal to 0 */ + if (Frequency == 0U) + { + status = ERROR; + } + else + { + if (Frequency > UTILS_LATENCY1_FREQ) + { + /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + else + { + /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */ + latency = LL_FLASH_LATENCY_0; + } + if (status != ERROR) + { + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + timeout = 2; + do + { + /* Wait for Flash latency to be updated */ + getlatency = LL_FLASH_GetLatency(); + timeout--; + } while ((getlatency != latency) && (timeout > 0)); + + if(getlatency != latency) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + } + + return status; +} +#endif /* FLASH_ACR_LATENCY */ + +/** + * @brief This function configures system clock with HSI as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL) + * - PREDIV: Set to 2 for few devices + * - PLLMUL: The application software must set correctly the PLL multiplication factor to + * be in the range 16-48MHz + * @note FLASH latency can be modified through this function. + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t pllfreq = 0U; + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + /* Check PREDIV value */ + assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); +#else + /* Force PREDIV value to 2 */ + UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2; +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); + + /* Enable HSI if not enabled */ + if (LL_RCC_HSI_IsReady() != 1U) + { + LL_RCC_HSI_Enable(); + while (LL_RCC_HSI_IsReady() != 1U) + { + /* Wait for HSI ready */ + } + } + + /* Configure PLL */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); +#else + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul); +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +#if defined(RCC_CFGR_SW_HSI48) +/** + * @brief This function configures system clock with HSI48 as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = ((HSI48 frequency / PREDIV) * PLLMUL) + * - PLLMUL: The application software must set correctly the PLL multiplication factor to + * be in the range 16-48MHz + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t pllfreq = 0U; + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { + /* Check PREDIV value */ + assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); + + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSI48_VALUE, UTILS_PLLInitStruct); + + /* Enable HSI48 if not enabled */ + if (LL_RCC_HSI48_IsReady() != 1U) + { + LL_RCC_HSI48_Enable(); + while (LL_RCC_HSI48_IsReady() != 1U) + { + /* Wait for HSI48 ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI48, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +#endif /*RCC_CFGR_SW_HSI48*/ +/** + * @brief This function configures system clock with HSE as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = ((HSE frequency / PREDIV) * PLLMUL) + * - PLLMUL: The application software must set correctly the PLL multiplication factor to + * be in the range 16-48MHz + * @note FLASH latency can be modified through this function. + * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 32000000 + * @param HSEBypass This parameter can be one of the following values: + * @arg @ref LL_UTILS_HSEBYPASS_ON + * @arg @ref LL_UTILS_HSEBYPASS_OFF + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t pllfreq = 0U; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); + assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { + /* Check PREDIV value */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); +#else + assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv)); +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); + + /* Enable HSE if not enabled */ + if (LL_RCC_HSE_IsReady() != 1U) + { + /* Check if need to enable HSE bypass feature or not */ + if (HSEBypass == LL_UTILS_HSEBYPASS_ON) + { + LL_RCC_HSE_EnableBypass(); + } + else + { + LL_RCC_HSE_DisableBypass(); + } + + /* Enable HSE */ + LL_RCC_HSE_Enable(); + while (LL_RCC_HSE_IsReady() != 1U) + { + /* Wait for HSE ready */ + } + } + + /* Configure PLL */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); +#else + LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul); +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UTILS_LL_Private_Functions + * @{ + */ +/** + * @brief Function to check that PLL can be modified + * @param PLL_InputFrequency PLL input frequency (in Hz) + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @retval PLL output frequency (in Hz) + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) +{ + uint32_t pllfreq = 0U; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul)); + + /* Check different PLL parameters according to RM */ + /* The application software must set correctly the PLL multiplication factor to + be in the range 16-48MHz */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); +#else + pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul); +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); + + return pllfreq; +} + +/** + * @brief Function to check that PLL can be modified + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PLL modification can be done + * - ERROR: PLL is busy + */ +static ErrorStatus UTILS_PLL_IsBusy(void) +{ + ErrorStatus status = SUCCESS; + + /* Check if PLL is busy*/ + if (LL_RCC_PLL_IsReady() != 0U) + { + /* PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @brief Function to enable PLL and switch system clock to PLL + * @param SYSCLK_Frequency SYSCLK frequency + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: No problem to switch system to PLL + * - ERROR: Problem to switch system to PLL + */ +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t sysclk_frequency_current = 0U; + + assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); + assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); + + /* Calculate current SYSCLK frequency */ + sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]); + + /* Increasing the number of wait states because of higher CPU frequency */ + if (sysclk_frequency_current < SYSCLK_Frequency) + { + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(SYSCLK_Frequency); + } + + /* Update system clock configuration */ + if (status == SUCCESS) + { + /* Enable PLL */ + LL_RCC_PLL_Enable(); + while (LL_RCC_PLL_IsReady() != 1U) + { + /* Wait for PLL ready */ + } + + /* Sysclk activation on the main PLL */ + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + { + /* Wait for system clock switch to PLL */ + } + + /* Set APB1 & APB2 prescaler*/ + LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (sysclk_frequency_current > SYSCLK_Frequency) + { + /* Set FLASH latency to lowest latency */ + status = LL_SetFlashLatency(SYSCLK_Frequency); + } + + /* Update SystemCoreClock variable */ + if (status == SUCCESS) + { + LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider)); + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Inc/main.h b/bsl/makeLowLayer/Inc/main.h new file mode 100644 index 0000000..a7cb631 --- /dev/null +++ b/bsl/makeLowLayer/Inc/main.h @@ -0,0 +1,98 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_ll_crs.h" +#include "stm32f0xx_ll_rcc.h" +#include "stm32f0xx_ll_bus.h" +#include "stm32f0xx_ll_system.h" +#include "stm32f0xx_ll_exti.h" +#include "stm32f0xx_ll_cortex.h" +#include "stm32f0xx_ll_utils.h" +#include "stm32f0xx_ll_pwr.h" +#include "stm32f0xx_ll_dma.h" +#include "stm32f0xx_ll_gpio.h" + +#if defined(USE_FULL_ASSERT) +#include "stm32_assert.h" +#endif /* USE_FULL_ASSERT */ + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define LED_G_Pin LL_GPIO_PIN_3 +#define LED_G_GPIO_Port GPIOB +#ifndef NVIC_PRIORITYGROUP_0 +#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority, + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority, + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority, + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority, + 1 bit for subpriority */ +#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority, + 0 bit for subpriority */ +#endif +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Inc/stm32_assert.h b/bsl/makeLowLayer/Inc/stm32_assert.h new file mode 100644 index 0000000..03511c4 --- /dev/null +++ b/bsl/makeLowLayer/Inc/stm32_assert.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file stm32_assert.h + * @brief STM32 assert file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ASSERT_H +#define __STM32_ASSERT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Includes ------------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ASSERT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Inc/stm32f0xx_it.h b/bsl/makeLowLayer/Inc/stm32f0xx_it.h new file mode 100644 index 0000000..41e320e --- /dev/null +++ b/bsl/makeLowLayer/Inc/stm32f0xx_it.h @@ -0,0 +1,65 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f0xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_IT_H +#define __STM32F0xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Makefile b/bsl/makeLowLayer/Makefile new file mode 100644 index 0000000..2f1f47c --- /dev/null +++ b/bsl/makeLowLayer/Makefile @@ -0,0 +1,189 @@ +########################################################################################################################## +# File automatically-generated by tool: [projectgenerator] version: [3.14.1] date: [Wed Sep 22 16:48:53 CEST 2021] +########################################################################################################################## + +# ------------------------------------------------ +# Generic Makefile (based on gcc) +# +# ChangeLog : +# 2017-02-10 - Several enhancements + project update mode +# 2015-07-22 - first version +# ------------------------------------------------ + +###################################### +# target +###################################### +TARGET = cmakeLowLayer + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -Og + + +####################################### +# paths +####################################### +# Build path +BUILD_DIR = build + +###################################### +# source +###################################### +# C sources +C_SOURCES = \ +Src/main.c \ +Src/stm32f0xx_it.c \ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c \ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c \ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c \ +Src/system_stm32f0xx.c \ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c \ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c + +# ASM sources +ASM_SOURCES = \ +startup_stm32f042x6.s + + +####################################### +# binaries +####################################### +PREFIX = arm-none-eabi- +# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) +# either it can be added to the PATH environment variable. +GCC_PATH = /usr/bin +ifdef GCC_PATH +CC = $(GCC_PATH)/$(PREFIX)gcc +AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp +CP = $(GCC_PATH)/$(PREFIX)objcopy +SZ = $(GCC_PATH)/$(PREFIX)size +else +CC = $(PREFIX)gcc +AS = $(PREFIX)gcc -x assembler-with-cpp +CP = $(PREFIX)objcopy +SZ = $(PREFIX)size +endif +HEX = $(CP) -O ihex +BIN = $(CP) -O binary -S + +####################################### +# CFLAGS +####################################### +# cpu +CPU = -mcpu=cortex-m0 + +# fpu +# NONE for Cortex-M0/M0+/M3 + +# float-abi + + +# mcu +MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) + +# macros for gcc +# AS defines +AS_DEFS = + +# C defines +C_DEFS = \ +-DUSE_FULL_LL_DRIVER \ +-DSTM32F042x6 \ +-DHSE_VALUE=8000000 \ +-DHSE_STARTUP_TIMEOUT=100 \ +-DLSE_STARTUP_TIMEOUT=5000 \ +-DLSE_VALUE=32768 \ +-DHSI_VALUE=8000000 \ +-DLSI_VALUE=40000 \ +-DVDD_VALUE=3300 \ +-DPREFETCH_ENABLE=1 \ +-DINSTRUCTION_CACHE_ENABLE=0 \ +-DDATA_CACHE_ENABLE=0 + + +# AS includes +AS_INCLUDES = + +# C includes +C_INCLUDES = \ +-IInc \ +-IDrivers/STM32F0xx_HAL_Driver/Inc \ +-IDrivers/CMSIS/Device/ST/STM32F0xx/Include \ +-IDrivers/CMSIS/Include + + +# compile gcc flags +ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf-2 +endif + + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" + + +####################################### +# LDFLAGS +####################################### +# link script +LDSCRIPT = STM32F042K6Tx_FLASH.ld + +# libraries +LIBS = -lc -lm -lnosys +LIBDIR = +LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections + +# default action: build all +all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin + + +####################################### +# build the application +####################################### +# list of objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) +# list of ASM program objects +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o))) +vpath %.s $(sort $(dir $(ASM_SOURCES))) + +$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) + $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ + +$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) + $(AS) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile + $(CC) $(OBJECTS) $(LDFLAGS) -o $@ + $(SZ) $@ + +$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(HEX) $< $@ + +$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(BIN) $< $@ + +$(BUILD_DIR): + mkdir $@ + +####################################### +# clean up +####################################### +clean: + -rm -fR $(BUILD_DIR) + +####################################### +# dependencies +####################################### +-include $(wildcard $(BUILD_DIR)/*.d) + +# *** EOF *** diff --git a/bsl/makeLowLayer/STM32F042K6Tx_FLASH.ld b/bsl/makeLowLayer/STM32F042K6Tx_FLASH.ld new file mode 100644 index 0000000..3dd25d2 --- /dev/null +++ b/bsl/makeLowLayer/STM32F042K6Tx_FLASH.ld @@ -0,0 +1,189 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** Author : Auto-generated by System Workbench for STM32 +** +** Abstract : Linker script for STM32F042K6Tx series +** 32Kbytes FLASH and 6Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed “as is,†without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2019 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20001800; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 6K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 32K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsl/makeLowLayer/Src/main.c b/bsl/makeLowLayer/Src/main.c new file mode 100644 index 0000000..447ad68 --- /dev/null +++ b/bsl/makeLowLayer/Src/main.c @@ -0,0 +1,202 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG); + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); + + /* System interrupt init*/ + /* SysTick_IRQn interrupt configuration */ + NVIC_SetPriority(SysTick_IRQn, 3); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + LL_GPIO_TogglePin(LED_G_GPIO_Port,LED_G_Pin); + LL_mDelay(500); + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + LL_FLASH_SetLatency(LL_FLASH_LATENCY_0); + while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_0) + { + } + LL_RCC_HSI_Enable(); + + /* Wait till HSI is ready */ + while(LL_RCC_HSI_IsReady() != 1) + { + + } + LL_RCC_HSI_SetCalibTrimming(16); + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI); + + /* Wait till System clock is ready */ + while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) + { + + } + LL_Init1msTick(8000000); + LL_SetSystemCoreClock(8000000); +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB); + + /**/ + LL_GPIO_ResetOutputPin(LED_G_GPIO_Port, LED_G_Pin); + + /**/ + GPIO_InitStruct.Pin = LED_G_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(LED_G_GPIO_Port, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Src/stm32f0xx_it.c b/bsl/makeLowLayer/Src/stm32f0xx_it.c new file mode 100644 index 0000000..f325c53 --- /dev/null +++ b/bsl/makeLowLayer/Src/stm32f0xx_it.c @@ -0,0 +1,147 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f0xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f0xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVC_IRQn 0 */ + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F0xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f0xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/makeLowLayer/Src/system_stm32f0xx.c b/bsl/makeLowLayer/Src/system_stm32f0xx.c new file mode 100644 index 0000000..4761a85 --- /dev/null +++ b/bsl/makeLowLayer/Src/system_stm32f0xx.c @@ -0,0 +1,247 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** @addtogroup STM32F0xx_System_Private_Includes + * @{ + */ + +#include "stm32f0xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI48_VALUE */ +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 8000000; + +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* NOTE :SystemInit(): This function is called at startup just after reset and + before branch to main program. This call is made inside + the "startup_stm32f0xx.s" file. + User can setups the default system clock (System clock source, PLL Multiplier + and Divider factors, AHB/APBx prescalers and Flash settings). + */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ + SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; + } +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) + else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) + { + /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ + SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + else + { +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ + || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ + || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ + SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; +#else + /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || + STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || + STM32F091xC || STM32F098xx || STM32F030xC */ + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/bsl/makeLowLayer/build/cmakeLowLayer.bin b/bsl/makeLowLayer/build/cmakeLowLayer.bin new file mode 100755 index 0000000000000000000000000000000000000000..cc9674d9404d727636675771dd9fdb658fbc8d2b GIT binary patch literal 1580 zcmbu9U1%It6vxk<+0A}6$z(SP+0EBxHrCi|i>9_#Qku!!upgNiY^xAs)k&asHV?8; zEmaX~lOpMgpiyWV@j+26SO}%tLg{KSwIGdUwv%8#K=y5)3JXGan`p*!uNFd4UmQ4d ze>3NQ&b{Z(nF~!2KH&uSn+|ZljRya5y|cmpF7kV5&Z_@!52j?f7;nt^@bkkON5ZK| z*-2G29U63lc`7dD8~|ZvEVe4)N_s-m(zV(bnxt$}`Zt}Fbqz(1LboSxmse~j<`PUt z0t)awiA2(Wis;FlB@1v_doj5xiH2)uukMscG49ypKF6Hs(JmK0OBJ;Ap~T1ueHCWG2N|J z@?v!BEnD^~4MGFm;%K0?(Z*Ykg4EaN*+b69+8_kd&Q}K-^yl?Y^%Y&}IfpT|GI^?x z+zHkzVzlPg=JpHji*Pv>g7(%!1K}SoslVq%ne4m(bEtr*)BNdNOE8!w+dos+@}*oo zh_G11dS&X)sIOb1C!@Y%iQbGlV2Qqr+GUBGGHSJD%O1ghiLqe${T|_<$-F@e3Lftw z60xp{3!#1elbkc0DQAr{QxnU_c@eXtUf_Dp8P1fm#+j`E^_+jcv52d}2*M*cXE;;N z8fUh0jNrV8wV)ojo^ysXtC3h5=l&4fAhCV@QY;;}izJIZR;sE9?At$9Hjfn3@pK$H zJ3ZedLx=E6>U4n!O9MzbZg|<97LL+b&Ppo@62=I*!SH zF`&5R<1|1sW2<2W=WDB!Sii9P?&3d%HLe%e`EI4-08)0fV;b!8FY9ENsEz0#pVpl{ zA)T#JDnQ}*yc=s~`$k*9B#%Rv(-hghi1$~>u5wYBPsf>#XiYlbfBXm2@lqD#`odMC z1rE@Iur+v>Zc}Pghv*)9RUbBlZJnlQv?`i$fJUi9Cp|t?E-O1s()o!JQSO;T2H8!b zzuufOTHz)78XO6prym+`pn6KLHU^Au>2>}zpf45eZr@GU#AbMz9;R*NUg#nnP93Jb zR2*L_#wVJ+ZRmN}N5{V_Lb#Lz2qaF#0tsSxY662Fsm{DV5l9j}@b|qwSw9F7p|Cu1 z>=LO^%)e4(yccKLn$0zdv?ms{=iBH)>h=O47AHQ}BU907>J m2izNWHg@6J!p1NfMnEOI5UX5vU;Z3Bdn4~4;P#-g{`eD<%f7_` literal 0 HcmV?d00001 diff --git a/bsl/makeLowLayer/build/main.lst b/bsl/makeLowLayer/build/main.lst new file mode 100644 index 0000000..b66c4ae --- /dev/null +++ b/bsl/makeLowLayer/build/main.lst @@ -0,0 +1,6306 @@ +ARM GAS /tmp/cc58GRFF.s page 1 + + + 1 .cpu cortex-m0 + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "main.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.MX_GPIO_Init,"ax",%progbits + 16 .align 1 + 17 .syntax unified + 18 .code 16 + 19 .thumb_func + 20 .fpu softvfp + 22 MX_GPIO_Init: + 23 .LFB419: + 24 .file 1 "Src/main.c" + 1:Src/main.c **** /* USER CODE BEGIN Header */ + 2:Src/main.c **** /** + 3:Src/main.c **** ****************************************************************************** + 4:Src/main.c **** * @file : main.c + 5:Src/main.c **** * @brief : Main program body + 6:Src/main.c **** ****************************************************************************** + 7:Src/main.c **** * @attention + 8:Src/main.c **** * + 9:Src/main.c **** *

© Copyright (c) 2021 STMicroelectronics. + 10:Src/main.c **** * All rights reserved.

+ 11:Src/main.c **** * + 12:Src/main.c **** * This software component is licensed by ST under BSD 3-Clause license, + 13:Src/main.c **** * the "License"; You may not use this file except in compliance with the + 14:Src/main.c **** * License. You may obtain a copy of the License at: + 15:Src/main.c **** * opensource.org/licenses/BSD-3-Clause + 16:Src/main.c **** * + 17:Src/main.c **** ****************************************************************************** + 18:Src/main.c **** */ + 19:Src/main.c **** /* USER CODE END Header */ + 20:Src/main.c **** /* Includes ------------------------------------------------------------------*/ + 21:Src/main.c **** #include "main.h" + 22:Src/main.c **** + 23:Src/main.c **** /* Private includes ----------------------------------------------------------*/ + 24:Src/main.c **** /* USER CODE BEGIN Includes */ + 25:Src/main.c **** + 26:Src/main.c **** /* USER CODE END Includes */ + 27:Src/main.c **** + 28:Src/main.c **** /* Private typedef -----------------------------------------------------------*/ + 29:Src/main.c **** /* USER CODE BEGIN PTD */ + 30:Src/main.c **** + 31:Src/main.c **** /* USER CODE END PTD */ + 32:Src/main.c **** + 33:Src/main.c **** /* Private define ------------------------------------------------------------*/ + 34:Src/main.c **** /* USER CODE BEGIN PD */ + ARM GAS /tmp/cc58GRFF.s page 2 + + + 35:Src/main.c **** /* USER CODE END PD */ + 36:Src/main.c **** + 37:Src/main.c **** /* Private macro -------------------------------------------------------------*/ + 38:Src/main.c **** /* USER CODE BEGIN PM */ + 39:Src/main.c **** + 40:Src/main.c **** /* USER CODE END PM */ + 41:Src/main.c **** + 42:Src/main.c **** /* Private variables ---------------------------------------------------------*/ + 43:Src/main.c **** + 44:Src/main.c **** /* USER CODE BEGIN PV */ + 45:Src/main.c **** + 46:Src/main.c **** /* USER CODE END PV */ + 47:Src/main.c **** + 48:Src/main.c **** /* Private function prototypes -----------------------------------------------*/ + 49:Src/main.c **** void SystemClock_Config(void); + 50:Src/main.c **** static void MX_GPIO_Init(void); + 51:Src/main.c **** /* USER CODE BEGIN PFP */ + 52:Src/main.c **** + 53:Src/main.c **** /* USER CODE END PFP */ + 54:Src/main.c **** + 55:Src/main.c **** /* Private user code ---------------------------------------------------------*/ + 56:Src/main.c **** /* USER CODE BEGIN 0 */ + 57:Src/main.c **** + 58:Src/main.c **** /* USER CODE END 0 */ + 59:Src/main.c **** + 60:Src/main.c **** /** + 61:Src/main.c **** * @brief The application entry point. + 62:Src/main.c **** * @retval int + 63:Src/main.c **** */ + 64:Src/main.c **** int main(void) + 65:Src/main.c **** { + 66:Src/main.c **** /* USER CODE BEGIN 1 */ + 67:Src/main.c **** + 68:Src/main.c **** /* USER CODE END 1 */ + 69:Src/main.c **** + 70:Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ + 71:Src/main.c **** + 72:Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + 73:Src/main.c **** + 74:Src/main.c **** LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG); + 75:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); + 76:Src/main.c **** + 77:Src/main.c **** /* System interrupt init*/ + 78:Src/main.c **** /* SysTick_IRQn interrupt configuration */ + 79:Src/main.c **** NVIC_SetPriority(SysTick_IRQn, 3); + 80:Src/main.c **** + 81:Src/main.c **** /* USER CODE BEGIN Init */ + 82:Src/main.c **** + 83:Src/main.c **** /* USER CODE END Init */ + 84:Src/main.c **** + 85:Src/main.c **** /* Configure the system clock */ + 86:Src/main.c **** SystemClock_Config(); + 87:Src/main.c **** + 88:Src/main.c **** /* USER CODE BEGIN SysInit */ + 89:Src/main.c **** + 90:Src/main.c **** /* USER CODE END SysInit */ + 91:Src/main.c **** + ARM GAS /tmp/cc58GRFF.s page 3 + + + 92:Src/main.c **** /* Initialize all configured peripherals */ + 93:Src/main.c **** MX_GPIO_Init(); + 94:Src/main.c **** /* USER CODE BEGIN 2 */ + 95:Src/main.c **** + 96:Src/main.c **** /* USER CODE END 2 */ + 97:Src/main.c **** + 98:Src/main.c **** /* Infinite loop */ + 99:Src/main.c **** /* USER CODE BEGIN WHILE */ + 100:Src/main.c **** while (1) + 101:Src/main.c **** { + 102:Src/main.c **** /* USER CODE END WHILE */ + 103:Src/main.c **** LL_GPIO_TogglePin(LED_G_GPIO_Port,LED_G_Pin); + 104:Src/main.c **** LL_mDelay(500); + 105:Src/main.c **** /* USER CODE BEGIN 3 */ + 106:Src/main.c **** } + 107:Src/main.c **** /* USER CODE END 3 */ + 108:Src/main.c **** } + 109:Src/main.c **** + 110:Src/main.c **** /** + 111:Src/main.c **** * @brief System Clock Configuration + 112:Src/main.c **** * @retval None + 113:Src/main.c **** */ + 114:Src/main.c **** void SystemClock_Config(void) + 115:Src/main.c **** { + 116:Src/main.c **** LL_FLASH_SetLatency(LL_FLASH_LATENCY_0); + 117:Src/main.c **** while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_0) + 118:Src/main.c **** { + 119:Src/main.c **** } + 120:Src/main.c **** LL_RCC_HSI_Enable(); + 121:Src/main.c **** + 122:Src/main.c **** /* Wait till HSI is ready */ + 123:Src/main.c **** while(LL_RCC_HSI_IsReady() != 1) + 124:Src/main.c **** { + 125:Src/main.c **** + 126:Src/main.c **** } + 127:Src/main.c **** LL_RCC_HSI_SetCalibTrimming(16); + 128:Src/main.c **** LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + 129:Src/main.c **** LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + 130:Src/main.c **** LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI); + 131:Src/main.c **** + 132:Src/main.c **** /* Wait till System clock is ready */ + 133:Src/main.c **** while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) + 134:Src/main.c **** { + 135:Src/main.c **** + 136:Src/main.c **** } + 137:Src/main.c **** LL_Init1msTick(8000000); + 138:Src/main.c **** LL_SetSystemCoreClock(8000000); + 139:Src/main.c **** } + 140:Src/main.c **** + 141:Src/main.c **** /** + 142:Src/main.c **** * @brief GPIO Initialization Function + 143:Src/main.c **** * @param None + 144:Src/main.c **** * @retval None + 145:Src/main.c **** */ + 146:Src/main.c **** static void MX_GPIO_Init(void) + 147:Src/main.c **** { + 25 .loc 1 147 0 + ARM GAS /tmp/cc58GRFF.s page 4 + + + 26 .cfi_startproc + 27 @ args = 0, pretend = 0, frame = 32 + 28 @ frame_needed = 0, uses_anonymous_args = 0 + 29 0000 00B5 push {lr} + 30 .LCFI0: + 31 .cfi_def_cfa_offset 4 + 32 .cfi_offset 14, -4 + 33 0002 89B0 sub sp, sp, #36 + 34 .LCFI1: + 35 .cfi_def_cfa_offset 40 + 148:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + 36 .loc 1 148 0 + 37 0004 1822 movs r2, #24 + 38 0006 0021 movs r1, #0 + 39 0008 02A8 add r0, sp, #8 + 40 000a FFF7FEFF bl memset + 41 .LVL0: + 42 .LBB34: + 43 .LBB35: + 44 .file 2 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h" + 1:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @file stm32f0xx_ll_bus.h + 4:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 7:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** [..] + 11:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 17:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** [..] + 18:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 22:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @attention + 25:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 26:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** *

© Copyright (c) 2016 STMicroelectronics. + 27:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * All rights reserved.

+ 28:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 29:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * This software component is licensed by ST under BSD 3-Clause license, + 30:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * the "License"; You may not use this file except in compliance with the + 31:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * License. You may obtain a copy of the License at: + 32:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * opensource.org/licenses/BSD-3-Clause + 33:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 34:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** ****************************************************************************** + 35:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 36:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 37:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + ARM GAS /tmp/cc58GRFF.s page 5 + + + 38:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #ifndef __STM32F0xx_LL_BUS_H + 39:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define __STM32F0xx_LL_BUS_H + 40:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 41:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #ifdef __cplusplus + 42:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** extern "C" { + 43:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif + 44:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 45:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 46:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #include "stm32f0xx.h" + 47:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 48:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @addtogroup STM32F0xx_LL_Driver + 49:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 50:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 51:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 52:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(RCC) + 53:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 54:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 55:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 56:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 57:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 58:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 59:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 60:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 61:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 62:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 63:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 64:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 65:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 66:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 67:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 68:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 69:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 70:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 71:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 72:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 73:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 74:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 75:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN + 76:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(DMA2) + 77:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN + 78:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*DMA2*/ + 79:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN + 80:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN + 81:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN + 82:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN + 83:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN + 84:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN + 85:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(GPIOD) + 86:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN + 87:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*GPIOD*/ + 88:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(GPIOE) + 89:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN + 90:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*GPIOE*/ + 91:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN + 92:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(TSC) + 93:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN + 94:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*TSC*/ + ARM GAS /tmp/cc58GRFF.s page 6 + + + 95:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 96:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @} + 97:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 98:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 99:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(TIM2) + 104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN + 105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*TIM2*/ + 106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN + 107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(TIM6) + 108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN + 109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*TIM6*/ + 110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(TIM7) + 111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN + 112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*TIM7*/ + 113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN + 114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN + 115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(SPI2) + 116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN + 117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*SPI2*/ + 118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART2) + 119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN + 120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /* USART2 */ + 121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART3) + 122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN + 123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /* USART3 */ + 124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART4) + 125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN + 126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /* USART4 */ + 127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART5) + 128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN + 129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /* USART5 */ + 130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN + 131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(I2C2) + 132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN + 133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*I2C2*/ + 134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USB) + 135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN + 136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /* USB */ + 137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(CAN) + 138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN + 139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*CAN*/ + 140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(CRS) + 141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN + 142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*CRS*/ + 143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN + 144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(DAC) + 145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN + 146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*DAC*/ + 147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(CEC) + 148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN + 149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*CEC*/ + 150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @} + ARM GAS /tmp/cc58GRFF.s page 7 + + + 152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + 155:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 156:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 157:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 158:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN + 159:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN + 160:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART8) + 161:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN + 162:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*USART8*/ + 163:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART7) + 164:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN + 165:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*USART7*/ + 166:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART6) + 167:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN + 168:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*USART6*/ + 169:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN + 170:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN + 171:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN + 172:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(TIM15) + 173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN + 174:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*TIM15*/ + 175:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN + 176:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN + 177:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN + 178:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 179:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @} + 180:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 181:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 182:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 183:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @} + 184:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 185:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 186:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 187:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 189:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 190:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 191:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 192:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 193:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 194:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 195:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 196:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 197:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 198:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n + 199:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n + 200:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n + 201:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n + 202:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + 203:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + 204:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + 205:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + 206:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n + 207:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + 208:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + ARM GAS /tmp/cc58GRFF.s page 8 + + + 209:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock + 210:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 211:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 212:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + 213:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 214:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + 215:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 216:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 217:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 218:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 219:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + 220:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + 221:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 222:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 223:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 224:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 225:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 226:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 227:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 228:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 229:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __IO uint32_t tmpreg; + 230:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 45 .loc 2 230 0 + 46 000e 0A4A ldr r2, .L2 + 47 0010 5169 ldr r1, [r2, #20] + 48 0012 8020 movs r0, #128 + 49 0014 C002 lsls r0, r0, #11 + 50 0016 0143 orrs r1, r0 + 51 0018 5161 str r1, [r2, #20] + 231:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 232:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 52 .loc 2 232 0 + 53 001a 5369 ldr r3, [r2, #20] + 54 001c 0340 ands r3, r0 + 55 001e 0193 str r3, [sp, #4] + 233:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** (void)tmpreg; + 56 .loc 2 233 0 + 57 0020 019B ldr r3, [sp, #4] + 58 .LVL1: + 59 .LBE35: + 60 .LBE34: + 61 .LBB36: + 62 .LBB37: + 63 .file 3 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h" + 1:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @file stm32f0xx_ll_gpio.h + 4:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Header file of GPIO LL module. + 6:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** ****************************************************************************** + 7:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @attention + 8:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * + 9:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** *

© Copyright (c) 2016 STMicroelectronics. + 10:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * All rights reserved.

+ 11:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * + 12:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * This software component is licensed by ST under BSD 3-Clause license, + 13:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * the "License"; You may not use this file except in compliance with the + ARM GAS /tmp/cc58GRFF.s page 9 + + + 14:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * License. You may obtain a copy of the License at: + 15:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * opensource.org/licenses/BSD-3-Clause + 16:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * + 17:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** ****************************************************************************** + 18:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 19:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 20:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 21:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #ifndef __STM32F0xx_LL_GPIO_H + 22:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define __STM32F0xx_LL_GPIO_H + 23:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 24:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #ifdef __cplusplus + 25:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** extern "C" { + 26:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #endif + 27:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 28:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Includes ------------------------------------------------------------------*/ + 29:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #include "stm32f0xx.h" + 30:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 31:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @addtogroup STM32F0xx_LL_Driver + 32:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 33:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 34:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 35:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || + 36:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 37:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL GPIO + 38:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 39:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 40:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 41:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Private types -------------------------------------------------------------*/ + 42:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Private variables ---------------------------------------------------------*/ + 43:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Private constants ---------------------------------------------------------*/ + 44:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Private macros ------------------------------------------------------------*/ + 45:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #if defined(USE_FULL_LL_DRIVER) + 46:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + 47:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 48:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 49:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 50:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 51:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 52:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 53:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #endif /*USE_FULL_LL_DRIVER*/ + 54:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 55:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Exported types ------------------------------------------------------------*/ + 56:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #if defined(USE_FULL_LL_DRIVER) + 57:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + 58:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 59:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 60:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 61:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 62:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief LL GPIO Init Structure definition + 63:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 64:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** typedef struct + 65:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 66:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + 67:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** This parameter can be any value of @ref GPIO_LL_EC_PIN */ + 68:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 69:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + 70:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_MODE. + ARM GAS /tmp/cc58GRFF.s page 10 + + + 71:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 72:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi + 73:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 74:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** uint32_t Speed; /*!< Specifies the speed for the selected pins. + 75:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_SPEED. + 76:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 77:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi + 78:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 79:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + 80:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + 81:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 82:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi + 83:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 84:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + 85:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_PULL. + 86:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 87:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi + 88:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 89:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + 90:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_AF. + 91:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 92:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi + 93:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } LL_GPIO_InitTypeDef; + 94:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 95:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 96:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 97:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 98:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #endif /* USE_FULL_LL_DRIVER */ + 99:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Exported constants --------------------------------------------------------*/ + 101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + 102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_PIN PIN + 106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ + 109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ + 110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ + 111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ + 112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ + 113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ + 114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ + 115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ + 116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ + 117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ + 118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ + 119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ + 120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ + 121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ + 122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ + 123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ + 124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ + 125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ + 126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ + 127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ + ARM GAS /tmp/cc58GRFF.s page 11 + + + 128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ + 129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO_BSRR_BS_15) /*!< Select all pins */ + 130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_MODE Mode + 135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ + 138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ + 139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode + 140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ + 141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_OUTPUT Output Type + 146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ + 149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type * + 150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_SPEED Output Speed + 155:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 156:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 157:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ + 158:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEEDR0_0 /*!< Select I/O medium output sp + 159:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEEDR0 /*!< Select I/O high output spee + 160:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 161:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 162:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 163:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW + 164:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM + 165:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_HIGH + 166:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 167:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + 168:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 169:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 170:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ + 171:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ + 172:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ + 173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 174:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 175:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 176:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 177:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_AF Alternate Function + 178:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 179:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 180:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ + 181:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ + 182:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ + 183:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ + 184:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ + ARM GAS /tmp/cc58GRFF.s page 12 + + + 185:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ + 186:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ + 187:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ + 188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 189:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 190:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 191:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 192:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 193:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 194:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 195:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 196:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Exported macro ------------------------------------------------------------*/ + 197:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + 198:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 199:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 200:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 201:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + 202:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 203:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 204:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 205:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 206:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Write a value in GPIO register + 207:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param __INSTANCE__ GPIO Instance + 208:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param __REG__ Register to be written + 209:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param __VALUE__ Value to be written in the register + 210:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 211:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 212:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALU + 213:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 214:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 215:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Read a value in GPIO register + 216:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param __INSTANCE__ GPIO Instance + 217:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param __REG__ Register to be read + 218:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval Register value + 219:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 220:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 221:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 222:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 223:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 224:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 225:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 226:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 227:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 228:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 229:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Exported functions --------------------------------------------------------*/ + 230:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + 231:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 232:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 233:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 234:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + 235:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 236:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 237:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 238:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 239:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Configure gpio mode for a dedicated pin on dedicated port. + 240:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + 241:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + ARM GAS /tmp/cc58GRFF.s page 13 + + + 242:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll MODER MODEy LL_GPIO_SetPinMode + 243:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 244:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 245:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 246:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 247:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 248:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 249:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 250:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 251:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 252:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 253:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 254:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 255:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 256:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 257:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 258:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 259:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 260:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 261:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Mode This parameter can be one of the following values: + 262:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_INPUT + 263:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_OUTPUT + 264:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ALTERNATE + 265:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ANALOG + 266:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 267:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 268:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) + 269:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 270:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0), ((Pin * Pin) * Mode)); + 271:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 272:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 273:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 274:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return gpio mode for a dedicated pin on dedicated port. + 275:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + 276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 277:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll MODER MODEy LL_GPIO_GetPinMode + 278:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 279:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 280:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 281:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 282:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 283:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 284:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 285:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 286:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 287:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 288:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 289:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 290:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 291:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 292:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 293:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 294:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 295:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 296:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 297:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_INPUT + 298:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_OUTPUT + ARM GAS /tmp/cc58GRFF.s page 14 + + + 299:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ALTERNATE + 300:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ANALOG + 301:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 302:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) + 303:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 304:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin)); + 305:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 306:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 307:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 308:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Configure gpio output type for several pins on dedicated port. + 309:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Output type as to be set when gpio pin is in output or + 310:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * alternate modes. Possible type are Push-pull or Open-drain. + 311:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + 312:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 313:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values: + 314:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 315:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 316:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 317:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 318:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 319:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 320:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 321:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 322:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 323:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 325:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 326:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 327:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 328:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 329:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 330:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL + 331:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param OutputType This parameter can be one of the following values: + 332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + 333:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + 334:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 335:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 336:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t Outpu + 337:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 338:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); + 339:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 340:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 341:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 342:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return gpio output type for several pins on dedicated port. + 343:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Output type as to be set when gpio pin is in output or + 344:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * alternate modes. Possible type are Push-pull or Open-drain. + 345:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 346:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + 347:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 348:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 349:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 350:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 351:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 352:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 353:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 354:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 355:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + ARM GAS /tmp/cc58GRFF.s page 15 + + + 356:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 357:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 358:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 359:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 360:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 361:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 362:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 363:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 364:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 365:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL + 366:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 367:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + 368:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + 369:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 370:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) + 371:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 372:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); + 373:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 374:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 375:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 376:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Configure gpio speed for a dedicated pin on dedicated port. + 377:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note I/O speed can be Low, Medium, Fast or High speed. + 378:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 379:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Refer to datasheet for frequency specifications and the power + 380:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * supply and load conditions for each speed. + 381:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + 382:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 383:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 384:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 385:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 386:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 387:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 388:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 389:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 390:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 391:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 392:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 393:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 394:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 395:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 396:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 397:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 398:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 399:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 400:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Speed This parameter can be one of the following values: + 401:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_LOW + 402:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + 403:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + 404:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 405:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 406:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) + 407:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 408:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0), ((Pin * Pin) * Speed)); + 409:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 410:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 411:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 412:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return gpio speed for a dedicated pin on dedicated port. + ARM GAS /tmp/cc58GRFF.s page 16 + + + 413:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note I/O speed can be Low, Medium, Fast or High speed. + 414:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 415:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Refer to datasheet for frequency specifications and the power + 416:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * supply and load conditions for each speed. + 417:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + 418:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 419:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 420:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 421:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 422:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 423:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 424:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 425:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 426:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 427:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 428:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 429:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 430:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 431:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 432:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 433:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 434:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 435:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 436:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 437:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_LOW + 438:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + 439:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + 440:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 441:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) + 442:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 443:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0)) / (Pin * Pin)); + 444:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 445:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 446:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 447:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + 448:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 449:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + 450:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 451:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 452:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 453:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 454:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 455:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 456:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 457:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 458:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 459:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 460:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 461:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 462:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 463:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 464:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 465:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 466:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 467:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 468:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pull This parameter can be one of the following values: + 469:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_NO + ARM GAS /tmp/cc58GRFF.s page 17 + + + 470:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_UP + 471:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_DOWN + 472:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 473:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 474:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) + 475:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 476:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0), ((Pin * Pin) * Pull)); + 477:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 478:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 479:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 480:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + 481:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 482:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + 483:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 484:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 485:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 486:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 487:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 488:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 489:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 490:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 491:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 492:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 493:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 494:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 495:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 496:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 497:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 498:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 499:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 500:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 501:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 502:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_NO + 503:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_UP + 504:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_DOWN + 505:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 506:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) + 507:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 508:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0)) / (Pin * Pin)); + 509:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 510:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 511:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 512:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + 513:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Possible values are from AF0 to AF7 depending on target. + 514:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 515:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + 516:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 517:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 518:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 519:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 520:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 521:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 522:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 523:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 524:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 525:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 526:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Alternate This parameter can be one of the following values: + ARM GAS /tmp/cc58GRFF.s page 18 + + + 527:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_0 + 528:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_1 + 529:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_2 + 530:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_3 + 531:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_4 + 532:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_5 + 533:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_6 + 534:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_7 + 535:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 536:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 537:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) + 538:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 539:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), + 540:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** ((((Pin * Pin) * Pin) * Pin) * Alternate)); + 541:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 542:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 543:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 544:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + 545:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + 546:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 547:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 548:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 549:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 550:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 551:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 552:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 553:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 554:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 555:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 556:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 557:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_0 + 558:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_1 + 559:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_2 + 560:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_3 + 561:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_4 + 562:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_5 + 563:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_6 + 564:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_7 + 565:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 566:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) + 567:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 568:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->AFR[0], + 569:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pi + 570:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 571:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 572:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 573:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + 574:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Possible values are from AF0 to AF7 depending on target. + 575:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 576:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + 577:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 578:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 579:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 580:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 581:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 582:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 583:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + ARM GAS /tmp/cc58GRFF.s page 19 + + + 584:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 585:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 586:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 587:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Alternate This parameter can be one of the following values: + 588:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_0 + 589:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_1 + 590:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_2 + 591:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_3 + 592:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_4 + 593:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_5 + 594:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_6 + 595:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_7 + 596:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 597:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 598:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) + 599:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 600:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFR + 601:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); + 602:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 603:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 604:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 605:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + 606:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Possible values are from AF0 to AF7 depending on target. + 607:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + 608:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 609:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 610:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 611:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 612:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 613:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 614:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 615:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 616:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 617:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 618:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 619:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_0 + 620:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_1 + 621:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_2 + 622:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_3 + 623:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_4 + 624:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_5 + 625:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_6 + 626:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_7 + 627:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 628:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) + 629:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 630:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->AFR[1], + 631:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AF + 632:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); + 633:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 634:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 635:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 636:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 637:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Lock configuration of several pins for a dedicated port. + 638:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note When the lock sequence has been applied on a port bit, the + 639:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * value of this port bit can no longer be modified until the + 640:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * next reset. + ARM GAS /tmp/cc58GRFF.s page 20 + + + 641:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Each lock bit freezes a specific configuration register + 642:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * (control and alternate function registers). + 643:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll LCKR LCKK LL_GPIO_LockPin + 644:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 645:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values: + 646:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 647:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 648:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 649:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 650:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 651:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 652:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 653:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 654:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 655:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 656:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 657:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 658:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 659:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 660:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 661:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 662:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL + 663:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 664:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 665:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) + 666:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 667:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __IO uint32_t temp; + 668:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + 669:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** WRITE_REG(GPIOx->LCKR, PinMask); + 670:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + 671:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** temp = READ_REG(GPIOx->LCKR); + 672:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** (void) temp; + 673:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 674:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 675:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 676:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return + 677:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + 678:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 679:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values: + 680:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 681:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 682:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 683:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 684:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 685:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 686:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 687:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 688:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 689:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 690:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 691:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 692:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 693:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 694:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 695:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 696:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL + 697:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval State of bit (1 or 0). + ARM GAS /tmp/cc58GRFF.s page 21 + + + 698:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 699:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) + 700:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 701:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); + 702:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 703:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 704:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 705:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + 706:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + 707:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 708:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval State of bit (1 or 0). + 709:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 710:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) + 711:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 712:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); + 713:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 714:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 715:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 716:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 717:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 718:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 719:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EF_Data_Access Data Access + 720:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 721:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 722:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 723:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 724:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return full input data register value for a dedicated port. + 725:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll IDR IDy LL_GPIO_ReadInputPort + 726:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 727:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval Input data register value of port + 728:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 729:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) + 730:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 731:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (uint32_t)(READ_REG(GPIOx->IDR)); + 732:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 733:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 734:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 735:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return if input data level for several pins of dedicated port is high or low. + 736:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + 737:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 738:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values: + 739:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 740:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 741:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 742:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 743:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 744:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 745:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 746:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 747:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 748:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 749:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 750:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 751:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 752:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 753:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 754:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + ARM GAS /tmp/cc58GRFF.s page 22 + + + 755:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL + 756:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval State of bit (1 or 0). + 757:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 758:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) + 759:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 760:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); + 761:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 762:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 763:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 764:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Write output data register for the port. + 765:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + 766:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 767:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param PortValue Level value for each pin of the port + 768:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 769:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 770:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) + 771:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 772:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** WRITE_REG(GPIOx->ODR, PortValue); + 773:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 774:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 775:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 776:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return full output data register value for a dedicated port. + 777:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + 778:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 779:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval Output data register value of port + 780:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 781:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) + 782:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 783:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (uint32_t)(READ_REG(GPIOx->ODR)); + 784:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 785:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 786:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 787:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return if input data level for several pins of dedicated port is high or low. + 788:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + 789:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 790:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values: + 791:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 792:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 793:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 794:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 795:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 796:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 797:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 798:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 799:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 800:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 801:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 802:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 803:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 804:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 805:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 806:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 807:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL + 808:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval State of bit (1 or 0). + 809:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 810:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) + 811:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + ARM GAS /tmp/cc58GRFF.s page 23 + + + 812:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); + 813:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 814:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 815:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 816:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Set several pins to high level on dedicated gpio port. + 817:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + 818:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 819:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values: + 820:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 821:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 822:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 823:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 824:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 825:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 826:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 827:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 828:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 829:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 830:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 831:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 832:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 833:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 834:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 835:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 836:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL + 837:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 838:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 839:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) + 840:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 841:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** WRITE_REG(GPIOx->BSRR, PinMask); + 842:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 843:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 844:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 845:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Set several pins to low level on dedicated gpio port. + 846:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll BRR BRy LL_GPIO_ResetOutputPin + 847:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 848:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values: + 849:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 850:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 851:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 852:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 853:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 854:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 855:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 856:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 857:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 858:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 859:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 860:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 861:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 862:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 863:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 864:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 865:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL + 866:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 867:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 868:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) + ARM GAS /tmp/cc58GRFF.s page 24 + + + 869:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 870:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** WRITE_REG(GPIOx->BRR, PinMask); + 64 .loc 3 870 0 + 65 0022 0648 ldr r0, .L2+4 + 66 0024 0823 movs r3, #8 + 67 0026 8362 str r3, [r0, #40] + 68 .LVL2: + 69 .LBE37: + 70 .LBE36: + 149:Src/main.c **** + 150:Src/main.c **** /* GPIO Ports Clock Enable */ + 151:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB); + 152:Src/main.c **** + 153:Src/main.c **** /**/ + 154:Src/main.c **** LL_GPIO_ResetOutputPin(LED_G_GPIO_Port, LED_G_Pin); + 155:Src/main.c **** + 156:Src/main.c **** /**/ + 157:Src/main.c **** GPIO_InitStruct.Pin = LED_G_Pin; + 71 .loc 1 157 0 + 72 0028 0293 str r3, [sp, #8] + 158:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + 73 .loc 1 158 0 + 74 002a 073B subs r3, r3, #7 + 75 002c 0393 str r3, [sp, #12] + 159:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + 160:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 161:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 162:Src/main.c **** LL_GPIO_Init(LED_G_GPIO_Port, &GPIO_InitStruct); + 76 .loc 1 162 0 + 77 002e 02A9 add r1, sp, #8 + 78 0030 FFF7FEFF bl LL_GPIO_Init + 79 .LVL3: + 163:Src/main.c **** + 164:Src/main.c **** } + 80 .loc 1 164 0 + 81 0034 09B0 add sp, sp, #36 + 82 @ sp needed + 83 0036 00BD pop {pc} + 84 .L3: + 85 .align 2 + 86 .L2: + 87 0038 00100240 .word 1073876992 + 88 003c 00040048 .word 1207960576 + 89 .cfi_endproc + 90 .LFE419: + 92 .section .text.SystemClock_Config,"ax",%progbits + 93 .align 1 + 94 .global SystemClock_Config + 95 .syntax unified + 96 .code 16 + 97 .thumb_func + 98 .fpu softvfp + 100 SystemClock_Config: + 101 .LFB418: + 115:Src/main.c **** LL_FLASH_SetLatency(LL_FLASH_LATENCY_0); + 102 .loc 1 115 0 + 103 .cfi_startproc + ARM GAS /tmp/cc58GRFF.s page 25 + + + 104 @ args = 0, pretend = 0, frame = 0 + 105 @ frame_needed = 0, uses_anonymous_args = 0 + 106 0000 10B5 push {r4, lr} + 107 .LCFI2: + 108 .cfi_def_cfa_offset 8 + 109 .cfi_offset 4, -8 + 110 .cfi_offset 14, -4 + 111 .LVL4: + 112 .LBB38: + 113 .LBB39: + 114 .file 4 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h" + 1:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @file stm32f0xx_ll_system.h + 4:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Header file of SYSTEM LL module. + 6:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** @verbatim + 7:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** ============================================================================== + 8:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** ##### How to use this driver ##### + 9:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** ============================================================================== + 10:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** [..] + 11:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** The LL SYSTEM driver contains a set of generic APIs that can be + 12:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** used by user: + 13:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** (+) Some of the FLASH features need to be handled in the SYSTEM file. + 14:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** (+) Access to DBGCMU registers + 15:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** (+) Access to SYSCFG registers + 16:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 17:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** @endverbatim + 18:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** ****************************************************************************** + 19:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @attention + 20:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + 21:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** *

© Copyright (c) 2016 STMicroelectronics. + 22:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * All rights reserved.

+ 23:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + 24:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * This software component is licensed by ST under BSD 3-Clause license, + 25:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * the "License"; You may not use this file except in compliance with the + 26:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * License. You may obtain a copy of the License at: + 27:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * opensource.org/licenses/BSD-3-Clause + 28:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + 29:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** ****************************************************************************** + 30:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 31:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 32:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 33:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #ifndef __STM32F0xx_LL_SYSTEM_H + 34:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define __STM32F0xx_LL_SYSTEM_H + 35:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 36:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #ifdef __cplusplus + 37:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** extern "C" { + 38:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif + 39:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 40:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Includes ------------------------------------------------------------------*/ + 41:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #include "stm32f0xx.h" + 42:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 43:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @addtogroup STM32F0xx_LL_Driver + 44:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 45:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 46:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + ARM GAS /tmp/cc58GRFF.s page 26 + + + 47:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + 48:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 49:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL SYSTEM + 50:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 51:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 52:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 53:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Private types -------------------------------------------------------------*/ + 54:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Private variables ---------------------------------------------------------*/ + 55:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 56:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Private constants ---------------------------------------------------------*/ + 57:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + 58:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 59:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 60:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 61:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 62:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 63:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 64:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 65:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Private macros ------------------------------------------------------------*/ + 66:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 67:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Exported types ------------------------------------------------------------*/ + 68:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Exported constants --------------------------------------------------------*/ + 69:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + 70:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 71:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 72:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 73:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Remap + 74:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 75:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 76:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000U /*!< + 77:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< + 78:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< + 79:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 80:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 81:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 82:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 83:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_IR_MOD) + 84:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation + 85:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 86:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 87:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< Timer1 + 88:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< USART1 + 89:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< USART4 + 90:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 91:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 92:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 93:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 94:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_IR_MOD */ + 95:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 96:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) || defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) || defined(SYS + 97:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_USART1TX_RMP SYSCFG USART DMA Remap + 98:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 99:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_USART1TX_DMA_RMP) + 101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_USART1TX_RMP_DMA1CH2 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) | (uint32_t)0x000 + 102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_USART1TX_RMP_DMA1CH4 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) | SYSCFG_CFGR1_US + 103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_USART1TX_DMA_RMP*/ + ARM GAS /tmp/cc58GRFF.s page 27 + + + 104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_USART1RX_DMA_RMP) + 105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_USART1RX_RMP_DMA1CH3 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) | (uint32_t)0x000 + 106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_USART1RX_RMP_DMA1CH5 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) | SYSCFG_CFGR1_US + 107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_USART1RX_DMA_RMP*/ + 108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_USART2_DMA_RMP) + 109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_USART2_RMP_DMA1CH54 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) | (uint32_t)0x00000 + 110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_USART2_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) | SYSCFG_CFGR1_USAR + 111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_USART2_DMA_RMP*/ + 112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_USART3_DMA_RMP) + 113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_USART3_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) | (uint32_t)0x00000 + 114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_USART3_RMP_DMA1CH32 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) | SYSCFG_CFGR1_USAR + 115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_USART3_DMA_RMP */ + 116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP || SYSCFG_CFGR1_USART1RX_DMA_RMP || SYSCFG_CFGR1_USART2_DMA + 120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_SPI2_DMA_RMP) + 122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_SPI2_RMP_DMA1 SYSCFG SPI2 DMA Remap + 123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_SPI2_RMP_DMA1_CH45 (uint32_t)0x00000000U /*!< SPI2_RX and SPI2_TX DMA + 126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_SPI2_RMP_DMA1_CH67 SYSCFG_CFGR1_SPI2_DMA_RMP /*!< SPI2_RX and SPI2_TX DMA + 127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_SPI2_DMA_RMP*/ + 132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_I2C1_DMA_RMP) + 134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_I2C1_RMP_DMA1 SYSCFG I2C1 DMA Remap + 135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C1_RMP_DMA1_CH32 (uint32_t)0x00000000U /*!< I2C1_RX and I2C1_TX DMA + 138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C1_RMP_DMA1_CH76 SYSCFG_CFGR1_I2C1_DMA_RMP /*!< I2C1_RX and I2C1_TX DMA + 139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_I2C1_DMA_RMP*/ + 144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_ADC_DMA_RMP) + 146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_ADC1_RMP_DMA1 SYSCFG ADC1 DMA Remap + 147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_ADC1_RMP_DMA1_CH1 (uint32_t)0x00000000U /*!< ADC DMA request mapped on + 150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_ADC1_RMP_DMA1_CH2 SYSCFG_CFGR1_ADC_DMA_RMP /*!< ADC DMA request mapped on + 151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 155:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_ADC_DMA_RMP */ + 156:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 157:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) || defined(SYSCFG_CFGR1_TIM17_DMA_RMP) || defined(SYSCFG_CF + 158:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_TIM16_RMP_DMA1 SYSCFG TIM DMA Remap + 159:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 160:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + ARM GAS /tmp/cc58GRFF.s page 28 + + + 161:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) + 162:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_TIM16_DMA_RMP2) + 163:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM16_RMP_DMA1_CH3 (((SYSCFG_CFGR1_TIM16_DMA_RMP | SYSCFG_CFGR1_TIM16_DMA_R + 164:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM16_RMP_DMA1_CH4 (((SYSCFG_CFGR1_TIM16_DMA_RMP | SYSCFG_CFGR1_TIM16_DMA_R + 165:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP2 >> 8U) | SYSCFG_CFGR1_TIM1 + 166:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #else + 167:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) | (uint32_t)0x000000 + 168:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM16_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM16 + 169:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_TIM16_DMA_RMP2 */ + 170:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_TIM16_DMA_RMP */ + 171:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_TIM17_DMA_RMP) + 172:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_TIM17_DMA_RMP2) + 173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM17_RMP_DMA1_CH1 (((SYSCFG_CFGR1_TIM17_DMA_RMP | SYSCFG_CFGR1_TIM17_DMA_R + 174:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM17_RMP_DMA1_CH2 (((SYSCFG_CFGR1_TIM17_DMA_RMP | SYSCFG_CFGR1_TIM17_DMA_R + 175:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP2 >> 8U) | SYSCFG_CFGR1_TIM1 + 176:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #else + 177:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) | (uint32_t)0x000000 + 178:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM17_RMP_DMA1_CH2 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM17 + 179:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_TIM17_DMA_RMP2 */ + 180:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_TIM17_DMA_RMP */ + 181:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_TIM1_DMA_RMP) + 182:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM1_RMP_DMA1_CH234 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) | (uint32_t)0x0000000 + 183:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM1_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM1_D + 184:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_TIM1_DMA_RMP*/ + 185:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_TIM2_DMA_RMP) + 186:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM2_RMP_DMA1_CH34 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) | (uint32_t)0x0000000 + 187:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM2_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM2_D + 188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_TIM2_DMA_RMP*/ + 189:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_TIM3_DMA_RMP) + 190:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM3_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) | (uint32_t)0x0000000 + 191:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM3_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM3_D + 192:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_TIM3_DMA_RMP*/ + 193:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 194:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 195:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 196:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 197:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_TIM16_DMA_RMP || SYSCFG_CFGR1_TIM17_DMA_RMP || SYSCFG_CFGR1_TIM1_DMA_RMP || + 198:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 199:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + 200:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 201:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 202:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< I2C PB6 Fast mode plus */ + 203:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< I2C PB7 Fast mode plus */ + 204:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< I2C PB8 Fast mode plus */ + 205:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< I2C PB9 Fast mode plus */ + 206:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) + 207:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on + 208:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_I2C_FMP_I2C1*/ + 209:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) + 210:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable I2C2 Fast mode plu + 211:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_I2C_FMP_I2C2*/ + 212:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_I2C_FMP_PA9) + 213:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on P + 214:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_I2C_FMP_PA9*/ + 215:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_I2C_FMP_PA10) + 216:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on + 217:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_I2C_FMP_PA10*/ + ARM GAS /tmp/cc58GRFF.s page 29 + + + 218:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 219:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 220:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 221:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 222:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT + 223:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 224:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 225:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /*!< EXTI PORT A */ + 226:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /*!< EXTI PORT B */ + 227:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /*!< EXTI PORT C */ + 228:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(GPIOD_BASE) + 229:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /*!< EXTI PORT D */ + 230:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*GPIOD_BASE*/ + 231:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(GPIOE_BASE) + 232:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /*!< EXTI PORT E */ + 233:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*GPIOE_BASE*/ + 234:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /*!< EXTI PORT F */ + 235:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 236:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 237:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 238:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 239:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE + 240:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 241:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 242:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0U << 16U | 0U) /*!< EXTI_POSITION_0 | EXTI + 243:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(4U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTI + 244:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(8U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTI + 245:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(12U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTI + 246:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0U << 16U | 1U) /*!< EXTI_POSITION_0 | EXTI + 247:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(4U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTI + 248:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(8U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTI + 249:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(12U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTI + 250:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0U << 16U | 2U) /*!< EXTI_POSITION_0 | EXTI + 251:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(4U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTI + 252:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(8U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTI + 253:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(12U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTI + 254:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0U << 16U | 3U) /*!< EXTI_POSITION_0 | EXTI + 255:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(4U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTI + 256:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(8U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTI + 257:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(12U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTI + 258:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 259:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 260:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 261:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 262:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + 263:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 264:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 265:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR2_PVD_LOCK) + 266:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD co + 267:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** with TIM1/15/16U/17 Break In + 268:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** the PVDE and PLS bits of the + 269:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR2_PVD_LOCK*/ + 270:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks t + 271:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** with Break Input of + 272:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LO + 273:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** CortexM0 with Break Inpu + 274:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + ARM GAS /tmp/cc58GRFF.s page 30 + + + 275:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 277:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 278:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + 279:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 280:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 281:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) + 282:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter st + 283:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*DBGMCU_APB1_FZ_DBG_TIM2_STOP*/ + 284:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter st + 285:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) + 286:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter st + 287:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*DBGMCU_APB1_FZ_DBG_TIM6_STOP*/ + 288:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) + 289:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter st + 290:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*DBGMCU_APB1_FZ_DBG_TIM7_STOP*/ + 291:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter s + 292:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Calendar fr + 293:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Wa + 294:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independe + 295:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS ti + 296:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) + 297:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /*!< CAN debug stopp + 298:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*DBGMCU_APB1_FZ_DBG_CAN_STOP*/ + 299:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 300:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 301:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 302:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 303:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_APB1 GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP + 304:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 305:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 306:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter st + 307:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) + 308:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP2_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /*!< TIM15 counter s + 309:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*DBGMCU_APB2_FZ_DBG_TIM15_STOP*/ + 310:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /*!< TIM16 counter s + 311:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /*!< TIM17 counter s + 312:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 313:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 314:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 315:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 316:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + 317:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 318:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 319:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ + 320:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ + 321:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 322:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 323:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 325:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 326:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 327:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 328:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 329:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Exported macro ------------------------------------------------------------*/ + 330:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 331:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Exported functions --------------------------------------------------------*/ + ARM GAS /tmp/cc58GRFF.s page 31 + + + 332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + 333:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 334:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 335:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 336:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + 337:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 338:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 339:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 340:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 341:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set memory mapping at address 0x00000000 + 342:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory + 343:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Memory This parameter can be one of the following values: + 344:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_FLASH + 345:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + 346:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_SRAM + 347:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 348:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 349:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) + 350:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 351:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory); + 352:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 353:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 354:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 355:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Get memory mapping at address 0x00000000 + 356:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory + 357:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval Returned value can be one of the following values: + 358:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_FLASH + 359:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + 360:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_SRAM + 361:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 362:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) + 363:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 364:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)); + 365:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 366:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 367:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_IR_MOD) + 368:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 369:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set IR Modulation Envelope signal source. + 370:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal + 371:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Source This parameter can be one of the following values: + 372:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_IR_MOD_TIM16 + 373:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_IR_MOD_USART1 + 374:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_IR_MOD_USART4 + 375:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 376:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 377:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source) + 378:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 379:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source); + 380:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 381:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 382:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 383:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Get IR Modulation Envelope signal source. + 384:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal + 385:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval Returned value can be one of the following values: + 386:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_IR_MOD_TIM16 + 387:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_IR_MOD_USART1 + 388:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_IR_MOD_USART4 + ARM GAS /tmp/cc58GRFF.s page 32 + + + 389:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 390:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void) + 391:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 392:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD)); + 393:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 394:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_IR_MOD */ + 395:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 396:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) || defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) || defined(SYS + 397:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 398:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set DMA request remapping bits for USART + 399:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 USART1TX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n + 400:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 USART1RX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n + 401:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 USART2_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n + 402:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 USART3_DMA_RMP LL_SYSCFG_SetRemapDMA_USART + 403:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Remap This parameter can be one of the following values: + 404:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH2 (*) + 405:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH4 (*) + 406:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH3 (*) + 407:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH5 (*) + 408:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH54 (*) + 409:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH67 (*) + 410:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH67 (*) + 411:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH32 (*) + 412:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + 413:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices. + 414:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 415:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 416:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_USART(uint32_t Remap) + 417:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 418:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U)); + 419:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 420:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP || SYSCFG_CFGR1_USART1RX_DMA_RMP || SYSCFG_CFGR1_USART2_DMA + 421:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 422:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_SPI2_DMA_RMP) + 423:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 424:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set DMA request remapping bits for SPI + 425:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 SPI2_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI + 426:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Remap This parameter can be one of the following values: + 427:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH45 + 428:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH67 + 429:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 430:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 431:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap) + 432:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 433:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_SPI2_DMA_RMP, Remap); + 434:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 435:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_SPI2_DMA_RMP */ + 436:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 437:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_I2C1_DMA_RMP) + 438:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 439:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set DMA request remapping bits for I2C + 440:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 I2C1_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C + 441:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Remap This parameter can be one of the following values: + 442:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH32 + 443:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH76 + 444:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 445:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + ARM GAS /tmp/cc58GRFF.s page 33 + + + 446:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap) + 447:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 448:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_I2C1_DMA_RMP, Remap); + 449:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 450:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_I2C1_DMA_RMP */ + 451:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 452:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_ADC_DMA_RMP) + 453:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 454:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set DMA request remapping bits for ADC + 455:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 ADC_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC + 456:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Remap This parameter can be one of the following values: + 457:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH1 + 458:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH2 + 459:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 460:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 461:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap) + 462:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 463:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ADC_DMA_RMP, Remap); + 464:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 465:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_ADC_DMA_RMP */ + 466:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 467:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) || defined(SYSCFG_CFGR1_TIM17_DMA_RMP) || defined(SYSCFG_CF + 468:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 469:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set DMA request remapping bits for TIM + 470:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + 471:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + 472:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 TIM16_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n + 473:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 TIM17_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n + 474:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 TIM1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + 475:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 TIM2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + 476:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 TIM3_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM + 477:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Remap This parameter can be one of the following values: + 478:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 (*) + 479:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH4 (*) + 480:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6 (*) + 481:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 (*) + 482:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH2 (*) + 483:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7 (*) + 484:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH234 (*) + 485:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH6 (*) + 486:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH34 (*) + 487:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH7 (*) + 488:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH4 (*) + 489:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH6 (*) + 490:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + 491:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices. + 492:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 493:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 494:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap) + 495:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 496:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U)); + 497:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 498:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_TIM16_DMA_RMP || SYSCFG_CFGR1_TIM17_DMA_RMP || SYSCFG_CFGR1_TIM1_DMA_RMP || + 499:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 500:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_PA11_PA12_RMP) + 501:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 502:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Enable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either + ARM GAS /tmp/cc58GRFF.s page 34 + + + 503:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * PA9/10 or PA11/12 pin pair on small pin-count packages) + 504:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_EnablePinRemap + 505:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 506:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 507:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_EnablePinRemap(void) + 508:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 509:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP); + 510:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 511:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 512:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 513:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Disable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either + 514:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * PA9/10 or PA11/12 pin pair on small pin-count packages) + 515:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_DisablePinRemap + 516:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 517:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 518:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_DisablePinRemap(void) + 519:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 520:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP); + 521:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 522:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ + 523:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 524:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 525:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Enable the I2C fast mode plus driving capability. + 526:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n + 527:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n + 528:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n + 529:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n + 530:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n + 531:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus\n + 532:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n + 533:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus + 534:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param ConfigFastModePlus This parameter can be a combination of the following values: + 535:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + 536:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + 537:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + 538:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + 539:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*) + 540:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + 541:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*) + 542:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*) + 543:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + 544:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices + 545:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 546:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 547:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) + 548:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 549:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); + 550:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 551:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 552:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 553:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Disable the I2C fast mode plus driving capability. + 554:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n + 555:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n + 556:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n + 557:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n + 558:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n + 559:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus\n + ARM GAS /tmp/cc58GRFF.s page 35 + + + 560:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n + 561:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus + 562:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param ConfigFastModePlus This parameter can be a combination of the following values: + 563:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + 564:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + 565:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + 566:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + 567:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*) + 568:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + 569:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*) + 570:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*) + 571:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + 572:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices + 573:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 574:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 575:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) + 576:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 577:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); + 578:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 579:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 580:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 581:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Configure source input for the EXTI external interrupt. + 582:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n + 583:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n + 584:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n + 585:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n + 586:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n + 587:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n + 588:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n + 589:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n + 590:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n + 591:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n + 592:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n + 593:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n + 594:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n + 595:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n + 596:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n + 597:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource + 598:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Port This parameter can be one of the following values: + 599:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTA + 600:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTB + 601:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTC + 602:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTD (*) + 603:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + 604:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTF + 605:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + 606:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices + 607:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Line This parameter can be one of the following values: + 608:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE0 + 609:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE1 + 610:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE2 + 611:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE3 + 612:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE4 + 613:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE5 + 614:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE6 + 615:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE7 + 616:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE8 + ARM GAS /tmp/cc58GRFF.s page 36 + + + 617:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE9 + 618:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE10 + 619:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE11 + 620:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE12 + 621:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE13 + 622:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE14 + 623:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE15 + 624:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 625:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 626:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) + 627:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 628:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], SYSCFG_EXTICR1_EXTI0 << (Line >> 16), Port << (Line >> 16 + 629:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 630:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 631:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 632:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Get the configured defined for specific EXTI Line + 633:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n + 634:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n + 635:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n + 636:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n + 637:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n + 638:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n + 639:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n + 640:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n + 641:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n + 642:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n + 643:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n + 644:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n + 645:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n + 646:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n + 647:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n + 648:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource + 649:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Line This parameter can be one of the following values: + 650:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE0 + 651:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE1 + 652:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE2 + 653:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE3 + 654:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE4 + 655:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE5 + 656:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE6 + 657:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE7 + 658:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE8 + 659:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE9 + 660:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE10 + 661:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE11 + 662:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE12 + 663:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE13 + 664:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE14 + 665:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE15 + 666:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval Returned value can be one of the following values: + 667:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTA + 668:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTB + 669:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTC + 670:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTD (*) + 671:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + 672:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTF + 673:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + ARM GAS /tmp/cc58GRFF.s page 37 + + + 674:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices + 675:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 676:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) + 677:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 678:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16))) > + 679:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 680:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 681:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE0_SR_EWDG) + 682:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 683:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Window watchdog interrupt occurred or not. + 684:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG + 685:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 686:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 687:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void) + 688:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 689:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG)); + 690:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 691:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE0_SR_EWDG */ + 692:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 693:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE1_SR_PVDOUT) + 694:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 695:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if PVD supply monitoring interrupt occurred or not (EXTI line 16). + 696:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE1 SR_PVDOUT LL_SYSCFG_IsActiveFlag_PVDOUT + 697:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 698:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 699:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void) + 700:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 701:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT)); + 702:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 703:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE1_SR_PVDOUT */ + 704:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 705:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE1_SR_VDDIO2) + 706:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 707:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if VDDIO2 supply monitoring interrupt occurred or not (EXTI line 31). + 708:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE1 SR_VDDIO2 LL_SYSCFG_IsActiveFlag_VDDIO2 + 709:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 710:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 711:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VDDIO2(void) + 712:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 713:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_VDDIO2) == (SYSCFG_ITLINE1_SR_VDDIO2)); + 714:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 715:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE1_SR_VDDIO2 */ + 716:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 717:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE2_SR_RTC_WAKEUP) + 718:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 719:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if RTC Wake Up interrupt occurred or not (EXTI line 20). + 720:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP LL_SYSCFG_IsActiveFlag_RTC_WAKEUP + 721:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 722:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 723:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void) + 724:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 725:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_WAKEUP) == (SYSCFG_ITLINE2_SR_RTC_W + 726:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 727:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE2_SR_RTC_WAKEUP */ + 728:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 729:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE2_SR_RTC_TSTAMP) + 730:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + ARM GAS /tmp/cc58GRFF.s page 38 + + + 731:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 19). + 732:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE2 SR_RTC_TSTAMP LL_SYSCFG_IsActiveFlag_RTC_TSTAMP + 733:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 734:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 735:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_TSTAMP(void) + 736:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 737:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_TSTAMP) == (SYSCFG_ITLINE2_SR_RTC_T + 738:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 739:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE2_SR_RTC_TSTAMP */ + 740:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 741:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE2_SR_RTC_ALRA) + 742:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 743:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if RTC Alarm interrupt occurred or not (EXTI line 17). + 744:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE2 SR_RTC_ALRA LL_SYSCFG_IsActiveFlag_RTC_ALRA + 745:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 746:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 747:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_ALRA(void) + 748:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 749:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_ALRA) == (SYSCFG_ITLINE2_SR_RTC_ALR + 750:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 751:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE2_SR_RTC_ALRA */ + 752:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 753:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE3_SR_FLASH_ITF) + 754:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 755:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Flash interface interrupt occurred or not. + 756:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF + 757:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 758:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 759:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void) + 760:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 761:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ + 762:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 763:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */ + 764:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 765:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE4_SR_CRS) + 766:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 767:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Clock recovery system interrupt occurred or not. + 768:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS + 769:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 770:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 771:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void) + 772:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 773:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS)); + 774:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 775:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE4_SR_CRS */ + 776:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 777:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE4_SR_CLK_CTRL) + 778:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 779:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Reset and clock control interrupt occurred or not. + 780:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL + 781:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 782:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 783:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void) + 784:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 785:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTR + 786:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 787:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */ + ARM GAS /tmp/cc58GRFF.s page 39 + + + 788:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 789:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE5_SR_EXTI0) + 790:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 791:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 0 interrupt occurred or not. + 792:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0 + 793:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 794:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 795:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void) + 796:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 797:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0)); + 798:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 799:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE5_SR_EXTI0 */ + 800:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 801:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE5_SR_EXTI1) + 802:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 803:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 1 interrupt occurred or not. + 804:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1 + 805:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 806:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 807:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void) + 808:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 809:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1)); + 810:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 811:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE5_SR_EXTI1 */ + 812:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 813:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE6_SR_EXTI2) + 814:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 815:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 2 interrupt occurred or not. + 816:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2 + 817:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 818:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 819:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void) + 820:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 821:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2)); + 822:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 823:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE6_SR_EXTI2 */ + 824:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 825:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE6_SR_EXTI3) + 826:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 827:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 3 interrupt occurred or not. + 828:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3 + 829:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 830:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 831:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void) + 832:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 833:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3)); + 834:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 835:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE6_SR_EXTI3 */ + 836:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 837:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI4) + 838:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 839:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 4 interrupt occurred or not. + 840:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4 + 841:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 842:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 843:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void) + 844:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + ARM GAS /tmp/cc58GRFF.s page 40 + + + 845:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4)); + 846:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 847:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI4 */ + 848:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 849:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI5) + 850:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 851:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 5 interrupt occurred or not. + 852:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5 + 853:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 854:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 855:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void) + 856:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 857:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5)); + 858:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 859:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI5 */ + 860:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 861:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI6) + 862:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 863:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 6 interrupt occurred or not. + 864:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6 + 865:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 866:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 867:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void) + 868:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 869:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6)); + 870:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 871:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI6 */ + 872:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 873:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI7) + 874:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 875:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 7 interrupt occurred or not. + 876:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7 + 877:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 878:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 879:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void) + 880:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 881:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7)); + 882:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 883:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI7 */ + 884:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 885:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI8) + 886:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 887:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 8 interrupt occurred or not. + 888:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8 + 889:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 890:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 891:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void) + 892:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 893:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8)); + 894:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 895:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI8 */ + 896:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 897:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI9) + 898:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 899:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 9 interrupt occurred or not. + 900:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9 + 901:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + ARM GAS /tmp/cc58GRFF.s page 41 + + + 902:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 903:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void) + 904:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 905:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9)); + 906:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 907:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI9 */ + 908:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 909:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI10) + 910:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 911:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 10 interrupt occurred or not. + 912:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10 + 913:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 914:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 915:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void) + 916:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 917:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10)); + 918:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 919:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI10 */ + 920:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 921:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI11) + 922:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 923:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 11 interrupt occurred or not. + 924:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11 + 925:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 926:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 927:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void) + 928:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 929:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11)); + 930:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 931:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI11 */ + 932:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 933:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI12) + 934:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 935:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 12 interrupt occurred or not. + 936:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12 + 937:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 938:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 939:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void) + 940:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 941:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12)); + 942:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 943:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI12 */ + 944:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 945:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI13) + 946:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 947:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 13 interrupt occurred or not. + 948:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13 + 949:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 950:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 951:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void) + 952:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 953:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13)); + 954:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 955:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI13 */ + 956:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 957:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI14) + 958:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + ARM GAS /tmp/cc58GRFF.s page 42 + + + 959:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 14 interrupt occurred or not. + 960:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14 + 961:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 962:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 963:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void) + 964:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 965:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14)); + 966:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 967:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI14 */ + 968:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 969:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI15) + 970:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 971:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 15 interrupt occurred or not. + 972:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15 + 973:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 974:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 975:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void) + 976:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 977:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15)); + 978:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 979:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI15 */ + 980:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 981:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE8_SR_TSC_EOA) + 982:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 983:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Touch sensing controller end of acquisition interrupt occurred or not. + 984:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE8 SR_TSC_EOA LL_SYSCFG_IsActiveFlag_TSC_EOA + 985:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 986:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 987:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_EOA(void) + 988:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 989:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_EOA) == (SYSCFG_ITLINE8_SR_TSC_EOA) + 990:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 991:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE8_SR_TSC_EOA */ + 992:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 993:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE8_SR_TSC_MCE) + 994:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 995:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Touch sensing controller max counterror interrupt occurred or not. + 996:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE8 SR_TSC_MCE LL_SYSCFG_IsActiveFlag_TSC_MCE + 997:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 998:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 999:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_MCE(void) +1000:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1001:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_MCE) == (SYSCFG_ITLINE8_SR_TSC_MCE) +1002:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1003:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE8_SR_TSC_MCE */ +1004:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1005:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE9_SR_DMA1_CH1) +1006:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1007:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA1 channel 1 interrupt occurred or not. +1008:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1 +1009:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1010:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1011:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void) +1012:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1013:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH +1014:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1015:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */ + ARM GAS /tmp/cc58GRFF.s page 43 + + +1016:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1017:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE10_SR_DMA1_CH2) +1018:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1019:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA1 channel 2 interrupt occurred or not. +1020:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2 +1021:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1022:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1023:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void) +1024:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1025:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1 +1026:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1027:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */ +1028:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1029:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE10_SR_DMA1_CH3) +1030:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1031:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA1 channel 3 interrupt occurred or not. +1032:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3 +1033:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1034:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1035:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void) +1036:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1037:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1 +1038:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1039:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */ +1040:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1041:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE10_SR_DMA2_CH1) +1042:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1043:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA2 channel 1 interrupt occurred or not. +1044:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH1 LL_SYSCFG_IsActiveFlag_DMA2_CH1 +1045:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1046:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1047:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void) +1048:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1049:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH1) == (SYSCFG_ITLINE10_SR_DMA2 +1050:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1051:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE10_SR_DMA2_CH1 */ +1052:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1053:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE10_SR_DMA2_CH2) +1054:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1055:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA2 channel 2 interrupt occurred or not. +1056:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH2 LL_SYSCFG_IsActiveFlag_DMA2_CH2 +1057:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1058:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1059:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void) +1060:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1061:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH2) == (SYSCFG_ITLINE10_SR_DMA2 +1062:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1063:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE10_SR_DMA2_CH2 */ +1064:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1065:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE11_SR_DMA1_CH4) +1066:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1067:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA1 channel 4 interrupt occurred or not. +1068:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4 +1069:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1070:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1071:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void) +1072:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + ARM GAS /tmp/cc58GRFF.s page 44 + + +1073:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1 +1074:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1075:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */ +1076:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1077:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE11_SR_DMA1_CH5) +1078:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1079:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA1 channel 5 interrupt occurred or not. +1080:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5 +1081:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1082:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1083:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void) +1084:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1085:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1 +1086:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1087:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */ +1088:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1089:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE11_SR_DMA1_CH6) +1090:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1091:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA1 channel 6 interrupt occurred or not. +1092:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6 +1093:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1094:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1095:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void) +1096:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1097:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1 +1098:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1099:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */ +1100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE11_SR_DMA1_CH7) +1102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA1 channel 7 interrupt occurred or not. +1104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7 +1105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void) +1108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1 +1110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */ +1112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE11_SR_DMA2_CH3) +1114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA2 channel 3 interrupt occurred or not. +1116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3 LL_SYSCFG_IsActiveFlag_DMA2_CH3 +1117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void) +1120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2 +1122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE11_SR_DMA2_CH3 */ +1124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE11_SR_DMA2_CH4) +1126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA2 channel 4 interrupt occurred or not. +1128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4 LL_SYSCFG_IsActiveFlag_DMA2_CH4 +1129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + ARM GAS /tmp/cc58GRFF.s page 45 + + +1130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void) +1132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2 +1134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE11_SR_DMA2_CH4 */ +1136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE11_SR_DMA2_CH5) +1138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA2 channel 5 interrupt occurred or not. +1140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5 LL_SYSCFG_IsActiveFlag_DMA2_CH5 +1141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void) +1144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2 +1146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE11_SR_DMA2_CH5 */ +1148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE12_SR_ADC) +1150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if ADC interrupt occurred or not. +1152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC +1153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1155:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void) +1156:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1157:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC)); +1158:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1159:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE12_SR_ADC */ +1160:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1161:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE12_SR_COMP1) +1162:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1163:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Comparator 1 interrupt occurred or not (EXTI line 21). +1164:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1 +1165:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1166:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1167:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void) +1168:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1169:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1)) +1170:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1171:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE12_SR_COMP1 */ +1172:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE12_SR_COMP2) +1174:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1175:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Comparator 2 interrupt occurred or not (EXTI line 22). +1176:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2 +1177:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1178:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1179:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void) +1180:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1181:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2)) +1182:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1183:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE12_SR_COMP2 */ +1184:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1185:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE13_SR_TIM1_BRK) +1186:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + ARM GAS /tmp/cc58GRFF.s page 46 + + +1187:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 1 break interrupt occurred or not. +1188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK +1189:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1190:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1191:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void) +1192:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1193:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1 +1194:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1195:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */ +1196:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1197:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE13_SR_TIM1_UPD) +1198:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1199:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 1 update interrupt occurred or not. +1200:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD +1201:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1202:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1203:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void) +1204:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1205:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1 +1206:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1207:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */ +1208:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1209:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE13_SR_TIM1_TRG) +1210:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1211:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 1 trigger interrupt occurred or not. +1212:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG +1213:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1214:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1215:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void) +1216:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1217:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1 +1218:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1219:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */ +1220:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1221:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE13_SR_TIM1_CCU) +1222:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1223:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 1 commutation interrupt occurred or not. +1224:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU +1225:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1226:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1227:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void) +1228:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1229:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1 +1230:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1231:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */ +1232:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1233:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE14_SR_TIM1_CC) +1234:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1235:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 1 capture compare interrupt occurred or not. +1236:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC +1237:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1238:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1239:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void) +1240:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1241:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_ +1242:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1243:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE14_SR_TIM1_CC */ + ARM GAS /tmp/cc58GRFF.s page 47 + + +1244:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1245:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE15_SR_TIM2_GLB) +1246:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1247:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 2 interrupt occurred or not. +1248:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2 +1249:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1250:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1251:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void) +1252:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1253:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2_GLB) == (SYSCFG_ITLINE15_SR_TIM2 +1254:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1255:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE15_SR_TIM2_GLB */ +1256:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1257:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE16_SR_TIM3_GLB) +1258:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1259:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 3 interrupt occurred or not. +1260:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3 +1261:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1262:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1263:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void) +1264:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1265:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3 +1266:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1267:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */ +1268:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1269:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE17_SR_DAC) +1270:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1271:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DAC underrun interrupt occurred or not. +1272:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE17 SR_DAC LL_SYSCFG_IsActiveFlag_DAC +1273:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1274:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1275:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void) +1276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1277:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC)); +1278:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1279:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE17_SR_DAC */ +1280:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1281:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE17_SR_TIM6_GLB) +1282:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1283:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 6 interrupt occurred or not. +1284:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB LL_SYSCFG_IsActiveFlag_TIM6 +1285:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1286:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1287:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void) +1288:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1289:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6_GLB) == (SYSCFG_ITLINE17_SR_TIM6 +1290:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1291:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE17_SR_TIM6_GLB */ +1292:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1293:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE18_SR_TIM7_GLB) +1294:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1295:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 7 interrupt occurred or not. +1296:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB LL_SYSCFG_IsActiveFlag_TIM7 +1297:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1298:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1299:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void) +1300:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + ARM GAS /tmp/cc58GRFF.s page 48 + + +1301:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7_GLB) == (SYSCFG_ITLINE18_SR_TIM7 +1302:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1303:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE18_SR_TIM7_GLB */ +1304:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1305:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE19_SR_TIM14_GLB) +1306:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1307:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 14 interrupt occurred or not. +1308:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14 +1309:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1310:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1311:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void) +1312:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1313:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM +1314:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1315:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */ +1316:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1317:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE20_SR_TIM15_GLB) +1318:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1319:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 15 interrupt occurred or not. +1320:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15 +1321:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1322:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1323:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void) +1324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1325:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == (SYSCFG_ITLINE20_SR_TIM +1326:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1327:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */ +1328:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1329:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE21_SR_TIM16_GLB) +1330:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1331:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 16 interrupt occurred or not. +1332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16 +1333:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1334:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1335:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void) +1336:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1337:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM +1338:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1339:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */ +1340:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1341:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE22_SR_TIM17_GLB) +1342:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1343:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 17 interrupt occurred or not. +1344:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17 +1345:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1346:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1347:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void) +1348:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1349:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM +1350:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1351:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */ +1352:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1353:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE23_SR_I2C1_GLB) +1354:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1355:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23. +1356:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1 +1357:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + ARM GAS /tmp/cc58GRFF.s page 49 + + +1358:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1359:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void) +1360:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1361:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1 +1362:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1363:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */ +1364:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1365:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE24_SR_I2C2_GLB) +1366:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1367:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if I2C2 interrupt occurred or not. +1368:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2 +1369:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1370:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1371:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void) +1372:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1373:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2 +1374:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1375:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */ +1376:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1377:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE25_SR_SPI1) +1378:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1379:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if SPI1 interrupt occurred or not. +1380:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1 +1381:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1382:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1383:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void) +1384:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1385:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1)); +1386:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1387:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE25_SR_SPI1 */ +1388:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1389:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE26_SR_SPI2) +1390:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1391:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if SPI2 interrupt occurred or not. +1392:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE26 SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2 +1393:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1394:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1395:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void) +1396:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1397:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2)); +1398:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1399:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE26_SR_SPI2 */ +1400:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1401:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE27_SR_USART1_GLB) +1402:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1403:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25. +1404:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1 +1405:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1406:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1407:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void) +1408:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1409:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_US +1410:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1411:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE27_SR_USART1_GLB */ +1412:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1413:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE28_SR_USART2_GLB) +1414:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + ARM GAS /tmp/cc58GRFF.s page 50 + + +1415:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26. +1416:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2 +1417:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1418:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1419:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void) +1420:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1421:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_US +1422:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1423:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE28_SR_USART2_GLB */ +1424:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1425:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE29_SR_USART3_GLB) +1426:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1427:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if USART3 interrupt occurred or not, combined with EXTI line 28. +1428:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3 +1429:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1430:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1431:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void) +1432:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1433:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == (SYSCFG_ITLINE29_SR_US +1434:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1435:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE29_SR_USART3_GLB */ +1436:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1437:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE29_SR_USART4_GLB) +1438:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1439:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if USART4 interrupt occurred or not. +1440:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4 +1441:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1442:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1443:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void) +1444:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1445:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == (SYSCFG_ITLINE29_SR_US +1446:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1447:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE29_SR_USART4_GLB */ +1448:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1449:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE29_SR_USART5_GLB) +1450:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1451:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if USART5 interrupt occurred or not. +1452:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE29 SR_USART5_GLB LL_SYSCFG_IsActiveFlag_USART5 +1453:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1454:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1455:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5(void) +1456:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1457:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART5_GLB) == (SYSCFG_ITLINE29_SR_US +1458:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1459:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE29_SR_USART5_GLB */ +1460:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1461:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE29_SR_USART6_GLB) +1462:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1463:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if USART6 interrupt occurred or not. +1464:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE29 SR_USART6_GLB LL_SYSCFG_IsActiveFlag_USART6 +1465:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1466:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1467:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6(void) +1468:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1469:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART6_GLB) == (SYSCFG_ITLINE29_SR_US +1470:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1471:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE29_SR_USART6_GLB */ + ARM GAS /tmp/cc58GRFF.s page 51 + + +1472:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1473:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE29_SR_USART7_GLB) +1474:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1475:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if USART7 interrupt occurred or not. +1476:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE29 SR_USART7_GLB LL_SYSCFG_IsActiveFlag_USART7 +1477:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1478:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1479:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART7(void) +1480:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1481:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART7_GLB) == (SYSCFG_ITLINE29_SR_US +1482:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1483:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE29_SR_USART7_GLB */ +1484:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1485:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE29_SR_USART8_GLB) +1486:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1487:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if USART8 interrupt occurred or not. +1488:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE29 SR_USART8_GLB LL_SYSCFG_IsActiveFlag_USART8 +1489:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1490:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1491:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART8(void) +1492:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1493:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART8_GLB) == (SYSCFG_ITLINE29_SR_US +1494:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1495:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE29_SR_USART8_GLB */ +1496:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1497:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE30_SR_CAN) +1498:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1499:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if CAN interrupt occurred or not. +1500:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE30 SR_CAN LL_SYSCFG_IsActiveFlag_CAN +1501:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1502:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1503:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CAN(void) +1504:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1505:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CAN) == (SYSCFG_ITLINE30_SR_CAN)); +1506:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1507:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE30_SR_CAN */ +1508:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1509:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE30_SR_CEC) +1510:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1511:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if CEC interrupt occurred or not, combined with EXTI line 27. +1512:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE30 SR_CEC LL_SYSCFG_IsActiveFlag_CEC +1513:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1514:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1515:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC(void) +1516:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1517:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CEC) == (SYSCFG_ITLINE30_SR_CEC)); +1518:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1519:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE30_SR_CEC */ +1520:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1521:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1522:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set connections to TIMx Break inputs +1523:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n +1524:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n +1525:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs +1526:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Break This parameter can be a combination of the following values: +1527:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) +1528:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY + ARM GAS /tmp/cc58GRFF.s page 52 + + +1529:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP +1530:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * +1531:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices +1532:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1533:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1534:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +1535:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1536:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR2_PVD_LOCK) +1537:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2 +1538:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #else +1539:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK, Break); +1540:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR2_PVD_LOCK*/ +1541:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1542:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1543:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1544:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Get connections to TIMx Break inputs +1545:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n +1546:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n +1547:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs +1548:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval Returned value can be can be a combination of the following values: +1549:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) +1550:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY +1551:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP +1552:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * +1553:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices +1554:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1555:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +1556:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1557:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR2_PVD_LOCK) +1558:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->CFGR2, +1559:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR +1560:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #else +1561:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOC +1562:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR2_PVD_LOCK*/ +1563:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1564:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1565:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1566:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if SRAM parity error detected +1567:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_IsActiveFlag_SP +1568:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1569:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1570:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void) +1571:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1572:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF) == (SYSCFG_CFGR2_SRAM_PEF)); +1573:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1574:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1575:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1576:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Clear SRAM parity error flag +1577:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_ClearFlag_SP +1578:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1579:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1580:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) +1581:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1582:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF); +1583:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1584:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1585:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + ARM GAS /tmp/cc58GRFF.s page 53 + + +1586:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} +1587:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1588:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1589:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU +1590:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ +1591:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1592:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1593:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1594:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Return the device identifier +1595:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @note For STM32F03x devices, the device ID is 0x444 +1596:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @note For STM32F04x devices, the device ID is 0x445. +1597:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @note For STM32F05x devices, the device ID is 0x440 +1598:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @note For STM32F07x devices, the device ID is 0x448 +1599:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @note For STM32F09x devices, the device ID is 0x442 +1600:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID +1601:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval Values between Min_Data=0x00 and Max_Data=0xFFF +1602:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1603:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +1604:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1605:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +1606:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1607:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1608:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1609:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Return the device revision identifier +1610:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @note This field indicates the revision of the device. +1611:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** For example, it is read as 0x1000 for Revision 1.0. +1612:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID +1613:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF +1614:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1615:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +1616:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1617:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +1618:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1619:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1620:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1621:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Enable the Debug Module during STOP mode +1622:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode +1623:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1624:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1625:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +1626:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1627:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +1628:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1629:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1630:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1631:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Disable the Debug Module during STOP mode +1632:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode +1633:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1634:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1635:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +1636:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1637:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +1638:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1639:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1640:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1641:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Enable the Debug Module during STANDBY mode +1642:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + ARM GAS /tmp/cc58GRFF.s page 54 + + +1643:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1644:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1645:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +1646:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1647:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +1648:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1649:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1650:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1651:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Disable the Debug Module during STANDBY mode +1652:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode +1653:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1654:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1655:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +1656:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1657:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +1658:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1659:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1660:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1661:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Freeze APB1 peripherals (group1 peripherals) +1662:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1663:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1664:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1665:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1666:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1667:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1668:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1669:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1670:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1671:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph +1672:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values: +1673:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) +1674:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP +1675:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) +1676:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) +1677:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP +1678:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP +1679:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP +1680:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP +1681:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP +1682:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) +1683:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * +1684:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices +1685:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1686:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1687:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +1688:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1689:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** SET_BIT(DBGMCU->APB1FZ, Periphs); +1690:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1691:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1692:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1693:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Unfreeze APB1 peripherals (group1 peripherals) +1694:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n +1695:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n +1696:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n +1697:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n +1698:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n +1699:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + ARM GAS /tmp/cc58GRFF.s page 55 + + +1700:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n +1701:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n +1702:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n +1703:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph +1704:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values: +1705:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) +1706:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP +1707:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) +1708:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) +1709:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP +1710:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP +1711:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP +1712:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP +1713:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP +1714:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) +1715:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * +1716:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices +1717:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1718:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1719:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +1720:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1721:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** CLEAR_BIT(DBGMCU->APB1FZ, Periphs); +1722:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1723:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1724:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1725:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Freeze APB1 peripherals (group2 peripherals) +1726:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n +1727:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n +1728:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n +1729:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph +1730:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values: +1731:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP +1732:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*) +1733:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP +1734:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP +1735:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * +1736:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices +1737:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1738:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1739:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +1740:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1741:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** SET_BIT(DBGMCU->APB2FZ, Periphs); +1742:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1743:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1744:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1745:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Unfreeze APB1 peripherals (group2 peripherals) +1746:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n +1747:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n +1748:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n +1749:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph +1750:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values: +1751:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP +1752:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*) +1753:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP +1754:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP +1755:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * +1756:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices + ARM GAS /tmp/cc58GRFF.s page 56 + + +1757:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1758:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1759:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +1760:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1761:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** CLEAR_BIT(DBGMCU->APB2FZ, Periphs); +1762:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1763:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1764:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} +1765:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1766:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1767:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_FLASH FLASH +1768:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ +1769:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1770:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1771:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1772:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set FLASH Latency +1773:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency +1774:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Latency This parameter can be one of the following values: +1775:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_0 +1776:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_1 +1777:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1778:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1779:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +1780:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1781:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); + 115 .loc 4 1781 0 + 116 0002 194A ldr r2, .L8 + 117 0004 1368 ldr r3, [r2] + 118 0006 0121 movs r1, #1 + 119 0008 8B43 bics r3, r1 + 120 000a 1360 str r3, [r2] + 121 .L5: + 122 .LBE39: + 123 .LBE38: + 124 .LBB40: + 125 .LBB41: +1782:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1783:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1784:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1785:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Get FLASH Latency +1786:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency +1787:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval Returned value can be one of the following values: +1788:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_0 +1789:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_1 +1790:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1791:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +1792:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1793:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); + 126 .loc 4 1793 0 discriminator 1 + 127 000c 164B ldr r3, .L8 + 128 000e 1B68 ldr r3, [r3] + 129 .LBE41: + 130 .LBE40: + 117:Src/main.c **** { + 131 .loc 1 117 0 discriminator 1 + 132 0010 DB07 lsls r3, r3, #31 + 133 0012 FBD4 bmi .L5 + ARM GAS /tmp/cc58GRFF.s page 57 + + + 134 .LBB42: + 135 .LBB43: + 136 .file 5 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h" + 1:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @file stm32f0xx_ll_rcc.h + 4:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Header file of RCC LL module. + 6:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** ****************************************************************************** + 7:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @attention + 8:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * + 9:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** *

© Copyright (c) 2016 STMicroelectronics. + 10:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * All rights reserved.

+ 11:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * + 12:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * This software component is licensed by ST under BSD 3-Clause license, + 13:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * the "License"; You may not use this file except in compliance with the + 14:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * License. You may obtain a copy of the License at: + 15:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * opensource.org/licenses/BSD-3-Clause + 16:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * + 17:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** ****************************************************************************** + 18:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 19:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 20:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 21:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #ifndef __STM32F0xx_LL_RCC_H + 22:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define __STM32F0xx_LL_RCC_H + 23:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 24:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #ifdef __cplusplus + 25:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** extern "C" { + 26:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif + 27:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 28:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Includes ------------------------------------------------------------------*/ + 29:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #include "stm32f0xx.h" + 30:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 31:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @addtogroup STM32F0xx_LL_Driver + 32:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 33:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 34:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 35:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC) + 36:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 37:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL RCC + 38:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 39:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 40:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 41:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Private types -------------------------------------------------------------*/ + 42:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Private variables ---------------------------------------------------------*/ + 43:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Private constants ---------------------------------------------------------*/ + 44:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Constants RCC Private Constants + 45:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 46:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 47:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Defines used for the bit position in the register and perform offsets*/ + 48:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HPRE (uint32_t)4U /*!< field position in register RCC_CFGR */ + 49:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_PPRE1 (uint32_t)8U /*!< field position in register RCC_CFGR */ + 50:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_PLLMUL (uint32_t)18U /*!< field position in register RCC_CFGR */ + 51:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HSICAL (uint32_t)8U /*!< field position in register RCC_CR */ + 52:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HSITRIM (uint32_t)3U /*!< field position in register RCC_CR */ + 53:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HSI14TRIM (uint32_t)3U /*!< field position in register RCC_CR2 */ + 54:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HSI14CAL (uint32_t)8U /*!< field position in register RCC_CR2 */ + ARM GAS /tmp/cc58GRFF.s page 58 + + + 55:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 56:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HSI48CAL (uint32_t)24U /*!< field position in register RCC_CR2 */ + 57:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 58:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */ + 59:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */ + 60:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */ + 61:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 62:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 63:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 64:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 65:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 66:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Private macros ------------------------------------------------------------*/ + 67:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 68:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Macros RCC Private Macros + 69:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 70:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 71:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 72:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 73:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 74:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /*USE_FULL_LL_DRIVER*/ + 75:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Exported types ------------------------------------------------------------*/ + 76:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 77:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Types RCC Exported Types + 78:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 79:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 80:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 81:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + 82:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 83:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 84:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 85:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 86:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief RCC Clocks Frequency Structure + 87:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 88:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** typedef struct + 89:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 90:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + 91:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + 92:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + 93:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } LL_RCC_ClocksTypeDef; + 94:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 95:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 96:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 97:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 98:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 99:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */ + 103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Exported constants --------------------------------------------------------*/ + 105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + 106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + 110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Defines used to adapt values of different oscillators + 111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note These values could be modified in the user environment according to + ARM GAS /tmp/cc58GRFF.s page 59 + + + 112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * HW set-up. + 113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if !defined (HSE_VALUE) + 116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ + 117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* HSE_VALUE */ + 118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if !defined (HSI_VALUE) + 120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ + 121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* HSI_VALUE */ + 122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if !defined (LSE_VALUE) + 124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ + 125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* LSE_VALUE */ + 126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if !defined (LSI_VALUE) + 128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ + 129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* LSI_VALUE */ + 130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if !defined (HSI48_VALUE) + 133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ + 134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* HSI48_VALUE */ + 135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + 141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_WriteReg function + 142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ + 145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ + 146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ + 147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ + 148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ + 149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC /*!< HSI14 Ready Interrupt Clear */ + 150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI48RDYC RCC_CIR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ + 152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt + 154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 155:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 156:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 157:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 158:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + 159:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_ReadReg function + 160:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 161:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 162:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ + 163:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ + 164:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ + 165:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ + 166:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ + 167:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF /*!< HSI14 Ready Interrupt flag */ + 168:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + ARM GAS /tmp/cc58GRFF.s page 60 + + + 169:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI48RDYF RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ + 170:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 171:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt f + 172:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ + 173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ + 174:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ + 175:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ + 176:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset f + 177:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag * + 178:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ + 179:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CSR_V18PWRRSTF) + 180:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V doma + 181:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CSR_V18PWRRSTF */ + 182:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 183:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 184:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 185:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 186:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_IT IT Defines + 187:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + 188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 189:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 190:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ + 191:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ + 192:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ + 193:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ + 194:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ + 195:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE /*!< HSI14 Ready Interrupt Enable * + 196:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 197:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI48RDYIE RCC_CIR_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable * + 198:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 199:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 200:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 201:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 202:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 203:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + 204:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 205:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 206:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving cap + 207:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capa + 208:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving cap + 209:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capabili + 210:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 211:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 212:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 213:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 214:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + 215:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 216:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 217:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ + 218:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ + 219:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ + 220:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_SW_HSI48) + 221:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 /*!< HSI48 selection as system clock + 222:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_SW_HSI48 */ + 223:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 224:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 225:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + ARM GAS /tmp/cc58GRFF.s page 61 + + + 226:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 227:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + 228:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 229:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 230:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ + 231:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ + 232:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ + 233:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_SWS_HSI48) + 234:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 /*!< HSI48 used as system clock */ + 235:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_SWS_HSI48 */ + 236:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 237:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 238:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 239:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 240:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + 241:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 242:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 243:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ + 244:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ + 245:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ + 246:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ + 247:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ + 248:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ + 249:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ + 250:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ + 251:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ + 252:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 253:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 254:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 255:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 256:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + 257:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 258:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 259:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */ + 260:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */ + 261:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */ + 262:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */ + 263:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */ + 264:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 265:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 266:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 267:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 268:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + 269:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 270:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 271:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, n + 272:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCOSEL_HSI14 /*!< HSI14 oscillator clock + 273:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MC + 274:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO s + 275:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO s + 276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO s + 277:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO s + 278:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_MCOSEL_HSI48) + 279:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /*!< HSI48 selection as MCO + 280:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_MCOSEL_HSI48 */ + 281:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2 + 282:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_PLLNODIV) + ARM GAS /tmp/cc58GRFF.s page 62 + + + 283:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL + 284:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_PLLNODIV */ + 285:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 286:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 287:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 288:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 289:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + 290:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 291:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 292:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */ + 293:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_MCOPRE) + 294:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ + 295:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ + 296:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ + 297:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ + 298:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */ + 299:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */ + 300:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */ + 301:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_MCOPRE */ + 302:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 303:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 304:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 305:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 306:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 307:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + 308:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 309:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 310:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the periphera + 311:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as ex + 312:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 313:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 314:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 315:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */ + 316:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 317:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection + 318:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 319:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 320:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USA + 321:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USA + 322:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USA + 323:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USA + 324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR3_USART2SW) + 325:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USA + 326:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USA + 327:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USA + 328:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USA + 329:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR3_USART2SW */ + 330:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR3_USART3SW) + 331:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USA + 332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USA + 333:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USA + 334:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USA + 335:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR3_USART3SW */ + 336:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 337:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 338:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 339:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + ARM GAS /tmp/cc58GRFF.s page 63 + + + 340:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection + 341:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 342:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 343:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI /*!< HSI oscillator clock used a + 344:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK /*!< System clock selected as I2 + 345:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 346:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 347:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 348:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 349:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(CEC) + 350:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + 351:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 352:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 353:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 + 354:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HD + 355:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 356:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 357:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 358:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 359:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* CEC */ + 360:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 361:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USB) + 362:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + 363:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 364:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 365:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR3_USBSW_HSI48) + 366:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 oscillator clock used + 367:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #else + 368:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_NONE ((uint32_t)0x00000000) /*!< USB Clock disabled */ + 369:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /*RCC_CFGR3_USBSW_HSI48*/ + 370:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL selected as USB clock s + 371:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 372:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 373:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 374:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 375:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* USB */ + 376:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 377:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source + 378:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 379:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 380:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection + 381:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR3_USART2SW) + 382:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection + 383:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR3_USART2SW */ + 384:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR3_USART3SW) + 385:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection + 386:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR3_USART3SW */ + 387:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 388:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 389:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 390:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 391:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source + 392:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 393:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 394:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */ + 395:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 396:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + ARM GAS /tmp/cc58GRFF.s page 64 + + + 397:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 398:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 399:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(CEC) + 400:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + 401:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 402:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 403:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selecti + 404:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 405:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 406:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 407:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* CEC */ + 408:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 409:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USB) + 410:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + 411:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 412:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 413:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE RCC_CFGR3_USBSW /*!< USB Clock source selection + 414:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 415:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 416:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 417:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* USB */ + 418:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 419:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + 420:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 421:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 422:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC + 423:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used a + 424:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used a + 425:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divide + 426:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 427:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 428:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 429:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 430:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor + 431:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 432:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 433:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */ + 434:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */ + 435:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */ + 436:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */ + 437:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */ + 438:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */ + 439:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */ + 440:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */ + 441:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */ + 442:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */ + 443:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */ + 444:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */ + 445:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */ + 446:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */ + 447:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */ + 448:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 449:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 450:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 451:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 452:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE + 453:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + ARM GAS /tmp/cc58GRFF.s page 65 + + + 454:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 455:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No cl + 456:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/P + 457:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + 458:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/P + 459:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_SW_HSI48) + 460:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< HSI48 + 461:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_SW_HSI48 */ + 462:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #else + 463:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI c + 464:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) + 465:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) + 466:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) + 467:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) + 468:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) + 469:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) + 470:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) + 471:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) + 472:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) + 473:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) + 474:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) + 475:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) + 476:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) + 477:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) + 478:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) + 479:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) + 480:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + 481:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 482:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 483:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 484:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 485:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor + 486:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 487:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 488:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divi + 489:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided + 490:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided + 491:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided + 492:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided + 493:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided + 494:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided + 495:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided + 496:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided + 497:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided + 498:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided + 499:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided + 500:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided + 501:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided + 502:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided + 503:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided + 504:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 505:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 506:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 507:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 508:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 509:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 510:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + ARM GAS /tmp/cc58GRFF.s page 66 + + + 511:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 512:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Exported macro ------------------------------------------------------------*/ + 513:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + 514:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 515:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 516:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 517:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + 518:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 519:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 520:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 521:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 522:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Write a value in RCC register + 523:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __REG__ Register to be written + 524:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __VALUE__ Value to be written in the register + 525:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 526:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 527:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + 528:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 529:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 530:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Read a value in RCC register + 531:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __REG__ Register to be read + 532:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Register value + 533:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 534:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) + 535:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 536:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 537:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 538:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 539:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + 540:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 541:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 542:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 543:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + 544:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 545:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency + 546:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator() + 547:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * , @ref LL_RCC_PLL_GetPrediv()); + 548:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/HSI48) + 549:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __PLLMUL__ This parameter can be one of the following values: + 550:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_2 + 551:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3 + 552:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4 + 553:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_5 + 554:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6 + 555:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_7 + 556:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8 + 557:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_9 + 558:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_10 + 559:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_11 + 560:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12 + 561:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_13 + 562:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_14 + 563:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_15 + 564:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16 + 565:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __PLLPREDIV__ This parameter can be one of the following values: + 566:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_1 + 567:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_2 + ARM GAS /tmp/cc58GRFF.s page 67 + + + 568:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_3 + 569:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_4 + 570:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_5 + 571:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_6 + 572:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_7 + 573:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_8 + 574:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_9 + 575:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_10 + 576:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_11 + 577:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_12 + 578:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_13 + 579:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_14 + 580:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_15 + 581:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_16 + 582:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) + 583:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 584:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \ + 585:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RC + 586:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 587:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #else + 588:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 589:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency + 590:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref + 591:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2) + 592:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __PLLMUL__ This parameter can be one of the following values: + 593:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_2 + 594:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3 + 595:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4 + 596:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_5 + 597:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6 + 598:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_7 + 599:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8 + 600:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_9 + 601:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_10 + 602:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_11 + 603:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12 + 604:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_13 + 605:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_14 + 606:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_15 + 607:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16 + 608:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) + 609:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 610:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ + 611:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) + 612:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + 613:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 614:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Helper macro to calculate the HCLK frequency + 615:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler + 616:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) + 617:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) + 618:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __AHBPRESCALER__ This parameter can be one of the following values: + 619:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 + 620:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 + 621:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 + 622:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 + 623:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 + 624:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 + ARM GAS /tmp/cc58GRFF.s page 68 + + + 625:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 + 626:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 + 627:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 + 628:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval HCLK clock frequency (in Hz) + 629:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 630:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTabl + 631:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 632:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 633:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + 634:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler + 635:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) + 636:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __HCLKFREQ__ HCLK frequency + 637:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __APB1PRESCALER__ This parameter can be one of the following values: + 638:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 + 639:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 + 640:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 + 641:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 + 642:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 + 643:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval PCLK1 clock frequency (in Hz) + 644:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 645:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[ + 646:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 647:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 648:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 649:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 650:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 651:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 652:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 653:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 654:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 655:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Exported functions --------------------------------------------------------*/ + 656:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + 657:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 658:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 659:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 660:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSE HSE + 661:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 662:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 663:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 664:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 665:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable the Clock Security System. + 666:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + 667:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 668:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 669:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) + 670:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 671:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_CSSON); + 672:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 673:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 674:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 675:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable the Clock Security System. + 676:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note Cannot be disabled in HSE is ready (only by hardware) + 677:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS + 678:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 679:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 680:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_DisableCSS(void) + 681:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + ARM GAS /tmp/cc58GRFF.s page 69 + + + 682:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_CSSON); + 683:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 684:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 685:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 686:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable HSE external oscillator (HSE Bypass) + 687:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + 688:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 689:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 690:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) + 691:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 692:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEBYP); + 693:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 694:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 695:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 696:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable HSE external oscillator (HSE Bypass) + 697:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + 698:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 699:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 700:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) + 701:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 702:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + 703:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 704:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 705:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 706:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable HSE crystal oscillator (HSE ON) + 707:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Enable + 708:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 709:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 710:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Enable(void) + 711:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 712:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEON); + 713:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 714:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 715:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 716:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable HSE crystal oscillator (HSE ON) + 717:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Disable + 718:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 719:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 720:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Disable(void) + 721:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 722:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEON); + 723:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 724:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 725:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 726:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if HSE oscillator Ready + 727:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + 728:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 729:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 730:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) + 731:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 732:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); + 733:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 734:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 735:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 736:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 737:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 738:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + ARM GAS /tmp/cc58GRFF.s page 70 + + + 739:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI HSI + 740:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 741:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 742:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 743:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 744:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable HSI oscillator + 745:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Enable + 746:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 747:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 748:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Enable(void) + 749:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 750:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSION); + 137 .loc 5 750 0 + 138 0014 154A ldr r2, .L8+4 + 139 0016 1368 ldr r3, [r2] + 140 0018 0121 movs r1, #1 + 141 001a 0B43 orrs r3, r1 + 142 001c 1360 str r3, [r2] + 143 .L6: + 144 .LBE43: + 145 .LBE42: + 146 .LBB44: + 147 .LBB45: + 751:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 752:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 753:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 754:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable HSI oscillator + 755:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Disable + 756:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 757:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 758:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Disable(void) + 759:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 760:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSION); + 761:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 762:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 763:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 764:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if HSI clock is ready + 765:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + 766:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 767:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 768:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) + 769:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 770:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); + 148 .loc 5 770 0 discriminator 1 + 149 001e 134B ldr r3, .L8+4 + 150 0020 1B68 ldr r3, [r3] + 151 .LBE45: + 152 .LBE44: + 123:Src/main.c **** { + 153 .loc 1 123 0 discriminator 1 + 154 0022 9B07 lsls r3, r3, #30 + 155 0024 FBD5 bpl .L6 + 156 .LVL5: + 157 .LBB46: + 158 .LBB47: + 771:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 772:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + ARM GAS /tmp/cc58GRFF.s page 71 + + + 773:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 774:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get HSI Calibration value + 775:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note When HSITRIM is written, HSICAL is updated with the sum of + 776:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * HSITRIM and the factory trim value + 777:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration + 778:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + 779:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 780:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) + 781:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 782:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); + 783:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 784:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 785:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 786:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set HSI Calibration trimming + 787:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note user-programmable trimming value that is added to the HSICAL + 788:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note Default value is 16, which, when added to the HSICAL value, + 789:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * should trim the HSI to 16 MHz +/- 1 % + 790:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming + 791:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Value between Min_Data = 0x00 and Max_Data = 0x1F + 792:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 793:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 794:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) + 795:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 796:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); + 159 .loc 5 796 0 + 160 0026 114B ldr r3, .L8+4 + 161 0028 1A68 ldr r2, [r3] + 162 002a F821 movs r1, #248 + 163 002c 8A43 bics r2, r1 + 164 002e 7839 subs r1, r1, #120 + 165 0030 0A43 orrs r2, r1 + 166 0032 1A60 str r2, [r3] + 167 .LVL6: + 168 .LBE47: + 169 .LBE46: + 170 .LBB48: + 171 .LBB49: + 797:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 798:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 799:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 800:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get HSI Calibration trimming + 801:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming + 802:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + 803:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 804:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) + 805:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 806:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + 807:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 808:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 809:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 810:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 811:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 812:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 813:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 814:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI48 HSI48 + 815:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 816:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + ARM GAS /tmp/cc58GRFF.s page 72 + + + 817:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 818:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 819:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable HSI48 + 820:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Enable + 821:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 822:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 823:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI48_Enable(void) + 824:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 825:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR2, RCC_CR2_HSI48ON); + 826:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 827:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 828:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 829:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable HSI48 + 830:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Disable + 831:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 832:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 833:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI48_Disable(void) + 834:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 835:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON); + 836:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 837:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 838:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 839:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if HSI48 oscillator Ready + 840:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI48RDY LL_RCC_HSI48_IsReady + 841:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 842:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 843:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) + 844:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 845:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CR2, RCC_CR2_HSI48RDY) == (RCC_CR2_HSI48RDY)); + 846:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 847:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 848:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 849:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get HSI48 Calibration value + 850:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI48CAL LL_RCC_HSI48_GetCalibration + 851:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + 852:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 853:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) + 854:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 855:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48CAL) >> RCC_POSITION_HSI48CAL); + 856:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 857:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 858:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 859:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 860:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 861:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 862:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 863:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 864:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI14 HSI14 + 865:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 866:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 867:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 868:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 869:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable HSI14 + 870:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Enable + 871:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 872:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 873:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI14_Enable(void) + ARM GAS /tmp/cc58GRFF.s page 73 + + + 874:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 875:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR2, RCC_CR2_HSI14ON); + 876:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 877:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 878:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 879:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable HSI14 + 880:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Disable + 881:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 882:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 883:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI14_Disable(void) + 884:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 885:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON); + 886:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 887:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 888:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 889:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if HSI14 oscillator Ready + 890:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14RDY LL_RCC_HSI14_IsReady + 891:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 892:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 893:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI14_IsReady(void) + 894:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 895:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CR2, RCC_CR2_HSI14RDY) == (RCC_CR2_HSI14RDY)); + 896:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 897:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 898:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 899:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief ADC interface can turn on the HSI14 oscillator + 900:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_EnableADCControl + 901:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 902:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 903:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI14_EnableADCControl(void) + 904:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 905:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS); + 906:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 907:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 908:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 909:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief ADC interface can not turn on the HSI14 oscillator + 910:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_DisableADCControl + 911:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 912:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 913:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI14_DisableADCControl(void) + 914:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 915:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS); + 916:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 917:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 918:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 919:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set HSI14 Calibration trimming + 920:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note user-programmable trimming value that is added to the HSI14CAL + 921:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note Default value is 16, which, when added to the HSI14CAL value, + 922:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * should trim the HSI14 to 14 MHz +/- 1 % + 923:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_SetCalibTrimming + 924:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Value between Min_Data = 0x00 and Max_Data = 0xFF + 925:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 926:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 927:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI14_SetCalibTrimming(uint32_t Value) + 928:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 929:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, Value << RCC_POSITION_HSI14TRIM); + 930:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + ARM GAS /tmp/cc58GRFF.s page 74 + + + 931:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 932:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 933:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get HSI14 Calibration value + 934:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note When HSI14TRIM is written, HSI14CAL is updated with the sum of + 935:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * HSI14TRIM and the factory trim value + 936:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_GetCalibTrimming + 937:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + 938:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 939:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibTrimming(void) + 940:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 941:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14TRIM) >> RCC_POSITION_HSI14TRIM); + 942:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 943:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 944:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 945:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get HSI14 Calibration trimming + 946:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14CAL LL_RCC_HSI14_GetCalibration + 947:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + 948:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 949:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibration(void) + 950:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 951:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14CAL) >> RCC_POSITION_HSI14CAL); + 952:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 953:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 954:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 955:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 956:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 957:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 958:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSE LSE + 959:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 960:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 961:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 962:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 963:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable Low Speed External (LSE) crystal. + 964:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + 965:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 966:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 967:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Enable(void) + 968:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 969:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); + 970:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 971:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 972:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 973:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable Low Speed External (LSE) crystal. + 974:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + 975:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 976:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 977:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Disable(void) + 978:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 979:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); + 980:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 981:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 982:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 983:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable external clock source (LSE bypass). + 984:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + 985:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 986:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 987:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) + ARM GAS /tmp/cc58GRFF.s page 75 + + + 988:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 989:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + 990:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 991:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 992:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 993:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable external clock source (LSE bypass). + 994:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + 995:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 996:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 997:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) + 998:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 999:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +1000:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1001:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1002:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1003:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set LSE oscillator drive capability +1004:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note The oscillator is in Xtal mode when it is not in bypass mode. +1005:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability +1006:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param LSEDrive This parameter can be one of the following values: +1007:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_LOW +1008:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW +1009:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH +1010:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_HIGH +1011:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1012:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1013:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +1014:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1015:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +1016:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1017:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1018:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1019:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get LSE oscillator drive capability +1020:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability +1021:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1022:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_LOW +1023:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW +1024:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH +1025:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_HIGH +1026:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1027:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +1028:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1029:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +1030:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1031:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1032:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1033:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if LSE oscillator Ready +1034:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady +1035:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1036:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1037:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +1038:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1039:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); +1040:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1041:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1042:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1043:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} +1044:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + ARM GAS /tmp/cc58GRFF.s page 76 + + +1045:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1046:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSI LSI +1047:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ +1048:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1049:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1050:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1051:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable LSI Oscillator +1052:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Enable +1053:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1054:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1055:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Enable(void) +1056:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1057:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_LSION); +1058:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1059:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1060:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1061:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable LSI Oscillator +1062:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Disable +1063:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1064:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1065:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Disable(void) +1066:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1067:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +1068:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1069:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1070:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1071:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if LSI is Ready +1072:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady +1073:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1074:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1075:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +1076:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1077:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +1078:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1079:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1080:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1081:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} +1082:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1083:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1084:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_System System +1085:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ +1086:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1087:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1088:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1089:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure the system clock source +1090:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR SW LL_RCC_SetSysClkSource +1091:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +1092:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI +1093:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE +1094:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL +1095:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI48 (*) +1096:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1097:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices +1098:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1099:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +1101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + ARM GAS /tmp/cc58GRFF.s page 77 + + +1102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +1103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get the system clock source +1107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR SWS LL_RCC_GetSysClkSource +1108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI +1110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE +1111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL +1112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*) +1113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices +1115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +1117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +1119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set AHB prescaler +1123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler +1124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +1125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 +1126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +1127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +1128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +1129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +1130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +1131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +1132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +1133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +1134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +1137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); + 172 .loc 5 1138 0 + 173 0034 5A68 ldr r2, [r3, #4] + 174 0036 7031 adds r1, r1, #112 + 175 0038 8A43 bics r2, r1 + 176 003a 5A60 str r2, [r3, #4] + 177 .LVL7: + 178 .LBE49: + 179 .LBE48: + 180 .LBB50: + 181 .LBB51: +1139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set APB1 prescaler +1143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler +1144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +1145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +1146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +1147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +1148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 + ARM GAS /tmp/cc58GRFF.s page 78 + + +1149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +1150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +1153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); + 182 .loc 5 1154 0 + 183 003c 5A68 ldr r2, [r3, #4] + 184 003e 0C49 ldr r1, .L8+8 + 185 0040 0A40 ands r2, r1 + 186 0042 5A60 str r2, [r3, #4] + 187 .LVL8: + 188 .LBE51: + 189 .LBE50: + 190 .LBB52: + 191 .LBB53: +1102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 192 .loc 5 1102 0 + 193 0044 5A68 ldr r2, [r3, #4] + 194 0046 0321 movs r1, #3 + 195 0048 8A43 bics r2, r1 + 196 004a 5A60 str r2, [r3, #4] + 197 .L7: + 198 .LBE53: + 199 .LBE52: + 200 .LBB54: + 201 .LBB55: +1118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 202 .loc 5 1118 0 discriminator 1 + 203 004c 074B ldr r3, .L8+4 + 204 004e 5B68 ldr r3, [r3, #4] + 205 0050 0C22 movs r2, #12 + 206 .LBE55: + 207 .LBE54: + 133:Src/main.c **** { + 208 .loc 1 133 0 discriminator 1 + 209 0052 1A42 tst r2, r3 + 210 0054 FAD1 bne .L7 + 137:Src/main.c **** LL_SetSystemCoreClock(8000000); + 211 .loc 1 137 0 + 212 0056 074C ldr r4, .L8+12 + 213 0058 2000 movs r0, r4 + 214 005a FFF7FEFF bl LL_Init1msTick + 215 .LVL9: + 138:Src/main.c **** } + 216 .loc 1 138 0 + 217 005e 2000 movs r0, r4 + 218 0060 FFF7FEFF bl LL_SetSystemCoreClock + 219 .LVL10: + 139:Src/main.c **** + 220 .loc 1 139 0 + 221 @ sp needed + 222 0064 10BD pop {r4, pc} + 223 .L9: + 224 0066 C046 .align 2 + 225 .L8: + 226 0068 00200240 .word 1073881088 + ARM GAS /tmp/cc58GRFF.s page 79 + + + 227 006c 00100240 .word 1073876992 + 228 0070 FFF8FFFF .word -1793 + 229 0074 00127A00 .word 8000000 + 230 .cfi_endproc + 231 .LFE418: + 233 .section .text.main,"ax",%progbits + 234 .align 1 + 235 .global main + 236 .syntax unified + 237 .code 16 + 238 .thumb_func + 239 .fpu softvfp + 241 main: + 242 .LFB417: + 65:Src/main.c **** /* USER CODE BEGIN 1 */ + 243 .loc 1 65 0 + 244 .cfi_startproc + 245 @ Volatile: function does not return. + 246 @ args = 0, pretend = 0, frame = 8 + 247 @ frame_needed = 0, uses_anonymous_args = 0 + 248 0000 00B5 push {lr} + 249 .LCFI3: + 250 .cfi_def_cfa_offset 4 + 251 .cfi_offset 14, -4 + 252 0002 83B0 sub sp, sp, #12 + 253 .LCFI4: + 254 .cfi_def_cfa_offset 16 + 255 .LVL11: + 256 .LBB56: + 257 .LBB57: + 234:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 235:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 236:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 237:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 238:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + 239:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + 240:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n + 241:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n + 242:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 243:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + 244:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + 245:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + 246:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + 247:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + 248:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + 249:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock + 250:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 251:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 252:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + 253:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 254:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + 255:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 256:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 257:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 258:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 259:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + 260:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + ARM GAS /tmp/cc58GRFF.s page 80 + + + 261:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 262:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 263:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 264:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 265:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 266:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 267:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 268:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 269:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + 270:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 271:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 272:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 273:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 274:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n + 275:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + 281:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + 282:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n + 283:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + 284:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + 285:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock + 286:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 287:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 288:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + 289:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 290:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + 291:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 292:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 293:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 294:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 295:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + 296:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + 297:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 298:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 299:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 300:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 301:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 302:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 303:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 304:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 305:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 306:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 307:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 308:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 309:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 310:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + 311:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + 312:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + 313:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + 314:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + 315:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + 316:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset + 317:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + ARM GAS /tmp/cc58GRFF.s page 81 + + + 318:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 319:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 320:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 321:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 322:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + 323:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + 324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 325:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 326:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 327:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 328:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 329:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 330:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 331:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 333:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 334:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 335:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 336:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 337:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + 338:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + 339:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + 340:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + 341:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + 342:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + 343:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset + 344:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 345:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 346:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 347:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 348:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 349:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + 350:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + 351:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 352:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 353:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 354:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 355:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 356:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 357:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 358:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 359:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 360:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 361:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 362:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 363:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @} + 364:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 365:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 366:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1 + 367:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 368:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 369:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 370:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 371:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock (available in register 1). + 372:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + 373:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + 374:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + ARM GAS /tmp/cc58GRFF.s page 82 + + + 375:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + 376:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n + 377:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + 378:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + 379:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + 380:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n + 381:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + 382:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + 383:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + 384:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + 385:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + 386:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n + 387:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + 388:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + 389:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + 390:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_EnableClock + 391:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 392:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + 393:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + 394:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 395:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 396:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + 397:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 398:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 399:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + 400:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + 401:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 402:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 403:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 404:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 405:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 406:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + 407:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 408:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 409:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 410:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + 411:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 412:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 413:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 414:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 415:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) + 416:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 417:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __IO uint32_t tmpreg; + 418:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 419:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 420:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + 421:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** (void)tmpreg; + 422:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 423:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 424:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 425:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not (available in register 1). + 426:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + 427:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + 428:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + 429:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + 430:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n + 431:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + ARM GAS /tmp/cc58GRFF.s page 83 + + + 432:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + 433:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + 434:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + 435:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + 436:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + 437:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + 438:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + 439:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + 440:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n + 441:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + 442:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + 443:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + 444:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock + 445:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 446:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + 447:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + 448:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 449:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 450:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + 451:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 452:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 453:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + 454:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + 455:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 456:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 457:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 458:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 459:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 460:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + 461:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 462:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 463:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 464:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + 465:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 466:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 467:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 468:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 469:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) + 470:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 471:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); + 472:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 473:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 474:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 475:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock (available in register 1). + 476:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + 477:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + 478:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + 479:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + 480:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n + 481:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + 482:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + 483:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + 484:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n + 485:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + 486:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + 487:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + 488:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + ARM GAS /tmp/cc58GRFF.s page 84 + + + 489:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + 490:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n + 491:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + 492:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + 493:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + 494:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_DisableClock + 495:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 496:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + 497:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + 498:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 499:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 500:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + 501:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 502:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 503:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + 504:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + 505:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 506:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 507:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 508:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 509:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 510:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + 511:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 512:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 513:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 514:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + 515:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 516:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 517:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 518:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 519:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) + 520:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 521:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); + 522:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 523:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 524:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 525:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Force APB1 peripherals reset (available in register 1). + 526:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + 527:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + 528:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + 529:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + 530:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n + 531:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + 532:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + 533:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + 534:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n + 535:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + 536:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + 537:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + 538:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + 539:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + 540:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n + 541:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + 542:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + 543:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + 544:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ForceReset + 545:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + ARM GAS /tmp/cc58GRFF.s page 85 + + + 546:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 547:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + 548:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + 549:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 550:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 551:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + 552:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 553:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 554:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + 555:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + 556:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 557:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 558:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 559:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 560:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 561:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + 562:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 563:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 564:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 565:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + 566:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 567:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 568:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 569:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 570:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) + 571:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 572:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); + 573:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 574:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 575:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 576:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Release APB1 peripherals reset (available in register 1). + 577:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + 578:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + 579:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + 580:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + 581:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n + 582:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + 583:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + 584:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + 585:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + 586:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + 587:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + 588:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + 589:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + 590:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + 591:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n + 592:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + 593:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + 594:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + 595:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset + 596:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 597:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 598:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + 599:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + 600:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 601:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 602:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + ARM GAS /tmp/cc58GRFF.s page 86 + + + 603:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 604:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 605:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + 606:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + 607:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 608:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 609:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 610:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 611:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 612:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + 613:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 614:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 615:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 616:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + 617:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 618:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 619:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 620:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 621:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) + 622:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 623:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); + 624:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 625:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 626:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 627:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @} + 628:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 629:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 630:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2 + 631:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 632:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 633:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 634:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 635:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock (available in register 2). + 636:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_EnableClock\n + 637:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB2ENR ADC1EN LL_APB1_GRP2_EnableClock\n + 638:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB2ENR USART8EN LL_APB1_GRP2_EnableClock\n + 639:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB2ENR USART7EN LL_APB1_GRP2_EnableClock\n + 640:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB2ENR USART6EN LL_APB1_GRP2_EnableClock\n + 641:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB2ENR TIM1EN LL_APB1_GRP2_EnableClock\n + 642:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB1_GRP2_EnableClock\n + 643:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB2ENR USART1EN LL_APB1_GRP2_EnableClock\n + 644:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB2ENR TIM15EN LL_APB1_GRP2_EnableClock\n + 645:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB2ENR TIM16EN LL_APB1_GRP2_EnableClock\n + 646:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB2ENR TIM17EN LL_APB1_GRP2_EnableClock\n + 647:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB2ENR DBGMCUEN LL_APB1_GRP2_EnableClock + 648:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 649:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + 650:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + 651:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) + 652:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) + 653:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) + 654:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + 655:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + 656:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + 657:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + 658:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + 659:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + ARM GAS /tmp/cc58GRFF.s page 87 + + + 660:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU + 661:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 662:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 663:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 664:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 665:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) + 666:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 667:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __IO uint32_t tmpreg; + 668:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); + 258 .loc 2 668 0 + 259 0004 164B ldr r3, .L12 + 260 0006 9969 ldr r1, [r3, #24] + 261 0008 0122 movs r2, #1 + 262 000a 1143 orrs r1, r2 + 263 000c 9961 str r1, [r3, #24] + 669:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 670:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + 264 .loc 2 670 0 + 265 000e 9969 ldr r1, [r3, #24] + 266 0010 0A40 ands r2, r1 + 267 0012 0192 str r2, [sp, #4] + 671:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** (void)tmpreg; + 268 .loc 2 671 0 + 269 0014 019A ldr r2, [sp, #4] + 270 .LVL12: + 271 .LBE57: + 272 .LBE56: + 273 .LBB58: + 274 .LBB59: + 418:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 275 .loc 2 418 0 + 276 0016 DA69 ldr r2, [r3, #28] + 277 0018 8021 movs r1, #128 + 278 001a 4905 lsls r1, r1, #21 + 279 001c 0A43 orrs r2, r1 + 280 001e DA61 str r2, [r3, #28] + 420:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** (void)tmpreg; + 281 .loc 2 420 0 + 282 0020 DB69 ldr r3, [r3, #28] + 283 0022 0B40 ands r3, r1 + 284 0024 0093 str r3, [sp] + 421:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 285 .loc 2 421 0 + 286 0026 009B ldr r3, [sp] + 287 .LVL13: + 288 .LBE59: + 289 .LBE58: + 290 .LBB60: + 291 .LBB61: + 292 .file 6 "Drivers/CMSIS/Include/core_cm0.h" + 1:Drivers/CMSIS/Include/core_cm0.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/core_cm0.h **** * @file core_cm0.h + 3:Drivers/CMSIS/Include/core_cm0.h **** * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + 4:Drivers/CMSIS/Include/core_cm0.h **** * @version V5.0.5 + 5:Drivers/CMSIS/Include/core_cm0.h **** * @date 28. May 2018 + 6:Drivers/CMSIS/Include/core_cm0.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/core_cm0.h **** /* + ARM GAS /tmp/cc58GRFF.s page 88 + + + 8:Drivers/CMSIS/Include/core_cm0.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/core_cm0.h **** * + 10:Drivers/CMSIS/Include/core_cm0.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/core_cm0.h **** * + 12:Drivers/CMSIS/Include/core_cm0.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/core_cm0.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/core_cm0.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/core_cm0.h **** * + 16:Drivers/CMSIS/Include/core_cm0.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/core_cm0.h **** * + 18:Drivers/CMSIS/Include/core_cm0.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/core_cm0.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/core_cm0.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/core_cm0.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/core_cm0.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/core_cm0.h **** */ + 24:Drivers/CMSIS/Include/core_cm0.h **** + 25:Drivers/CMSIS/Include/core_cm0.h **** #if defined ( __ICCARM__ ) + 26:Drivers/CMSIS/Include/core_cm0.h **** #pragma system_include /* treat file as system include file for MISRA check */ + 27:Drivers/CMSIS/Include/core_cm0.h **** #elif defined (__clang__) + 28:Drivers/CMSIS/Include/core_cm0.h **** #pragma clang system_header /* treat file as system include file */ + 29:Drivers/CMSIS/Include/core_cm0.h **** #endif + 30:Drivers/CMSIS/Include/core_cm0.h **** + 31:Drivers/CMSIS/Include/core_cm0.h **** #ifndef __CORE_CM0_H_GENERIC + 32:Drivers/CMSIS/Include/core_cm0.h **** #define __CORE_CM0_H_GENERIC + 33:Drivers/CMSIS/Include/core_cm0.h **** + 34:Drivers/CMSIS/Include/core_cm0.h **** #include + 35:Drivers/CMSIS/Include/core_cm0.h **** + 36:Drivers/CMSIS/Include/core_cm0.h **** #ifdef __cplusplus + 37:Drivers/CMSIS/Include/core_cm0.h **** extern "C" { + 38:Drivers/CMSIS/Include/core_cm0.h **** #endif + 39:Drivers/CMSIS/Include/core_cm0.h **** + 40:Drivers/CMSIS/Include/core_cm0.h **** /** + 41:Drivers/CMSIS/Include/core_cm0.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + 42:Drivers/CMSIS/Include/core_cm0.h **** CMSIS violates the following MISRA-C:2004 rules: + 43:Drivers/CMSIS/Include/core_cm0.h **** + 44:Drivers/CMSIS/Include/core_cm0.h **** \li Required Rule 8.5, object/function definition in header file.
+ 45:Drivers/CMSIS/Include/core_cm0.h **** Function definitions in header files are used to allow 'inlining'. + 46:Drivers/CMSIS/Include/core_cm0.h **** + 47:Drivers/CMSIS/Include/core_cm0.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ 48:Drivers/CMSIS/Include/core_cm0.h **** Unions are used for effective representation of core registers. + 49:Drivers/CMSIS/Include/core_cm0.h **** + 50:Drivers/CMSIS/Include/core_cm0.h **** \li Advisory Rule 19.7, Function-like macro defined.
+ 51:Drivers/CMSIS/Include/core_cm0.h **** Function-like macros are used to allow more efficient code. + 52:Drivers/CMSIS/Include/core_cm0.h **** */ + 53:Drivers/CMSIS/Include/core_cm0.h **** + 54:Drivers/CMSIS/Include/core_cm0.h **** + 55:Drivers/CMSIS/Include/core_cm0.h **** /******************************************************************************* + 56:Drivers/CMSIS/Include/core_cm0.h **** * CMSIS definitions + 57:Drivers/CMSIS/Include/core_cm0.h **** ******************************************************************************/ + 58:Drivers/CMSIS/Include/core_cm0.h **** /** + 59:Drivers/CMSIS/Include/core_cm0.h **** \ingroup Cortex_M0 + 60:Drivers/CMSIS/Include/core_cm0.h **** @{ + 61:Drivers/CMSIS/Include/core_cm0.h **** */ + 62:Drivers/CMSIS/Include/core_cm0.h **** + 63:Drivers/CMSIS/Include/core_cm0.h **** #include "cmsis_version.h" + 64:Drivers/CMSIS/Include/core_cm0.h **** + ARM GAS /tmp/cc58GRFF.s page 89 + + + 65:Drivers/CMSIS/Include/core_cm0.h **** /* CMSIS CM0 definitions */ + 66:Drivers/CMSIS/Include/core_cm0.h **** #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] C + 67:Drivers/CMSIS/Include/core_cm0.h **** #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] C + 68:Drivers/CMSIS/Include/core_cm0.h **** #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + 69:Drivers/CMSIS/Include/core_cm0.h **** __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL + 70:Drivers/CMSIS/Include/core_cm0.h **** + 71:Drivers/CMSIS/Include/core_cm0.h **** #define __CORTEX_M (0U) /*!< Cortex-M Core */ + 72:Drivers/CMSIS/Include/core_cm0.h **** + 73:Drivers/CMSIS/Include/core_cm0.h **** /** __FPU_USED indicates whether an FPU is used or not. + 74:Drivers/CMSIS/Include/core_cm0.h **** This core does not support an FPU at all + 75:Drivers/CMSIS/Include/core_cm0.h **** */ + 76:Drivers/CMSIS/Include/core_cm0.h **** #define __FPU_USED 0U + 77:Drivers/CMSIS/Include/core_cm0.h **** + 78:Drivers/CMSIS/Include/core_cm0.h **** #if defined ( __CC_ARM ) + 79:Drivers/CMSIS/Include/core_cm0.h **** #if defined __TARGET_FPU_VFP + 80:Drivers/CMSIS/Include/core_cm0.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 81:Drivers/CMSIS/Include/core_cm0.h **** #endif + 82:Drivers/CMSIS/Include/core_cm0.h **** + 83:Drivers/CMSIS/Include/core_cm0.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + 84:Drivers/CMSIS/Include/core_cm0.h **** #if defined __ARM_PCS_VFP + 85:Drivers/CMSIS/Include/core_cm0.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 86:Drivers/CMSIS/Include/core_cm0.h **** #endif + 87:Drivers/CMSIS/Include/core_cm0.h **** + 88:Drivers/CMSIS/Include/core_cm0.h **** #elif defined ( __GNUC__ ) + 89:Drivers/CMSIS/Include/core_cm0.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) + 90:Drivers/CMSIS/Include/core_cm0.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 91:Drivers/CMSIS/Include/core_cm0.h **** #endif + 92:Drivers/CMSIS/Include/core_cm0.h **** + 93:Drivers/CMSIS/Include/core_cm0.h **** #elif defined ( __ICCARM__ ) + 94:Drivers/CMSIS/Include/core_cm0.h **** #if defined __ARMVFP__ + 95:Drivers/CMSIS/Include/core_cm0.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 96:Drivers/CMSIS/Include/core_cm0.h **** #endif + 97:Drivers/CMSIS/Include/core_cm0.h **** + 98:Drivers/CMSIS/Include/core_cm0.h **** #elif defined ( __TI_ARM__ ) + 99:Drivers/CMSIS/Include/core_cm0.h **** #if defined __TI_VFP_SUPPORT__ + 100:Drivers/CMSIS/Include/core_cm0.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 101:Drivers/CMSIS/Include/core_cm0.h **** #endif + 102:Drivers/CMSIS/Include/core_cm0.h **** + 103:Drivers/CMSIS/Include/core_cm0.h **** #elif defined ( __TASKING__ ) + 104:Drivers/CMSIS/Include/core_cm0.h **** #if defined __FPU_VFP__ + 105:Drivers/CMSIS/Include/core_cm0.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 106:Drivers/CMSIS/Include/core_cm0.h **** #endif + 107:Drivers/CMSIS/Include/core_cm0.h **** + 108:Drivers/CMSIS/Include/core_cm0.h **** #elif defined ( __CSMC__ ) + 109:Drivers/CMSIS/Include/core_cm0.h **** #if ( __CSMC__ & 0x400U) + 110:Drivers/CMSIS/Include/core_cm0.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 111:Drivers/CMSIS/Include/core_cm0.h **** #endif + 112:Drivers/CMSIS/Include/core_cm0.h **** + 113:Drivers/CMSIS/Include/core_cm0.h **** #endif + 114:Drivers/CMSIS/Include/core_cm0.h **** + 115:Drivers/CMSIS/Include/core_cm0.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + 116:Drivers/CMSIS/Include/core_cm0.h **** + 117:Drivers/CMSIS/Include/core_cm0.h **** + 118:Drivers/CMSIS/Include/core_cm0.h **** #ifdef __cplusplus + 119:Drivers/CMSIS/Include/core_cm0.h **** } + 120:Drivers/CMSIS/Include/core_cm0.h **** #endif + 121:Drivers/CMSIS/Include/core_cm0.h **** + ARM GAS /tmp/cc58GRFF.s page 90 + + + 122:Drivers/CMSIS/Include/core_cm0.h **** #endif /* __CORE_CM0_H_GENERIC */ + 123:Drivers/CMSIS/Include/core_cm0.h **** + 124:Drivers/CMSIS/Include/core_cm0.h **** #ifndef __CMSIS_GENERIC + 125:Drivers/CMSIS/Include/core_cm0.h **** + 126:Drivers/CMSIS/Include/core_cm0.h **** #ifndef __CORE_CM0_H_DEPENDANT + 127:Drivers/CMSIS/Include/core_cm0.h **** #define __CORE_CM0_H_DEPENDANT + 128:Drivers/CMSIS/Include/core_cm0.h **** + 129:Drivers/CMSIS/Include/core_cm0.h **** #ifdef __cplusplus + 130:Drivers/CMSIS/Include/core_cm0.h **** extern "C" { + 131:Drivers/CMSIS/Include/core_cm0.h **** #endif + 132:Drivers/CMSIS/Include/core_cm0.h **** + 133:Drivers/CMSIS/Include/core_cm0.h **** /* check device defines and use defaults */ + 134:Drivers/CMSIS/Include/core_cm0.h **** #if defined __CHECK_DEVICE_DEFINES + 135:Drivers/CMSIS/Include/core_cm0.h **** #ifndef __CM0_REV + 136:Drivers/CMSIS/Include/core_cm0.h **** #define __CM0_REV 0x0000U + 137:Drivers/CMSIS/Include/core_cm0.h **** #warning "__CM0_REV not defined in device header file; using default!" + 138:Drivers/CMSIS/Include/core_cm0.h **** #endif + 139:Drivers/CMSIS/Include/core_cm0.h **** + 140:Drivers/CMSIS/Include/core_cm0.h **** #ifndef __NVIC_PRIO_BITS + 141:Drivers/CMSIS/Include/core_cm0.h **** #define __NVIC_PRIO_BITS 2U + 142:Drivers/CMSIS/Include/core_cm0.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + 143:Drivers/CMSIS/Include/core_cm0.h **** #endif + 144:Drivers/CMSIS/Include/core_cm0.h **** + 145:Drivers/CMSIS/Include/core_cm0.h **** #ifndef __Vendor_SysTickConfig + 146:Drivers/CMSIS/Include/core_cm0.h **** #define __Vendor_SysTickConfig 0U + 147:Drivers/CMSIS/Include/core_cm0.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + 148:Drivers/CMSIS/Include/core_cm0.h **** #endif + 149:Drivers/CMSIS/Include/core_cm0.h **** #endif + 150:Drivers/CMSIS/Include/core_cm0.h **** + 151:Drivers/CMSIS/Include/core_cm0.h **** /* IO definitions (access restrictions to peripheral registers) */ + 152:Drivers/CMSIS/Include/core_cm0.h **** /** + 153:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines + 154:Drivers/CMSIS/Include/core_cm0.h **** + 155:Drivers/CMSIS/Include/core_cm0.h **** IO Type Qualifiers are used + 156:Drivers/CMSIS/Include/core_cm0.h **** \li to specify the access to peripheral variables. + 157:Drivers/CMSIS/Include/core_cm0.h **** \li for automatic generation of peripheral register debug information. + 158:Drivers/CMSIS/Include/core_cm0.h **** */ + 159:Drivers/CMSIS/Include/core_cm0.h **** #ifdef __cplusplus + 160:Drivers/CMSIS/Include/core_cm0.h **** #define __I volatile /*!< Defines 'read only' permissions */ + 161:Drivers/CMSIS/Include/core_cm0.h **** #else + 162:Drivers/CMSIS/Include/core_cm0.h **** #define __I volatile const /*!< Defines 'read only' permissions */ + 163:Drivers/CMSIS/Include/core_cm0.h **** #endif + 164:Drivers/CMSIS/Include/core_cm0.h **** #define __O volatile /*!< Defines 'write only' permissions */ + 165:Drivers/CMSIS/Include/core_cm0.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ + 166:Drivers/CMSIS/Include/core_cm0.h **** + 167:Drivers/CMSIS/Include/core_cm0.h **** /* following defines should be used for structure members */ + 168:Drivers/CMSIS/Include/core_cm0.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ + 169:Drivers/CMSIS/Include/core_cm0.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ + 170:Drivers/CMSIS/Include/core_cm0.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ + 171:Drivers/CMSIS/Include/core_cm0.h **** + 172:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of group Cortex_M0 */ + 173:Drivers/CMSIS/Include/core_cm0.h **** + 174:Drivers/CMSIS/Include/core_cm0.h **** + 175:Drivers/CMSIS/Include/core_cm0.h **** + 176:Drivers/CMSIS/Include/core_cm0.h **** /******************************************************************************* + 177:Drivers/CMSIS/Include/core_cm0.h **** * Register Abstraction + 178:Drivers/CMSIS/Include/core_cm0.h **** Core Register contain: + ARM GAS /tmp/cc58GRFF.s page 91 + + + 179:Drivers/CMSIS/Include/core_cm0.h **** - Core Register + 180:Drivers/CMSIS/Include/core_cm0.h **** - Core NVIC Register + 181:Drivers/CMSIS/Include/core_cm0.h **** - Core SCB Register + 182:Drivers/CMSIS/Include/core_cm0.h **** - Core SysTick Register + 183:Drivers/CMSIS/Include/core_cm0.h **** ******************************************************************************/ + 184:Drivers/CMSIS/Include/core_cm0.h **** /** + 185:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_core_register Defines and Type Definitions + 186:Drivers/CMSIS/Include/core_cm0.h **** \brief Type definitions and defines for Cortex-M processor based devices. + 187:Drivers/CMSIS/Include/core_cm0.h **** */ + 188:Drivers/CMSIS/Include/core_cm0.h **** + 189:Drivers/CMSIS/Include/core_cm0.h **** /** + 190:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_core_register + 191:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_CORE Status and Control Registers + 192:Drivers/CMSIS/Include/core_cm0.h **** \brief Core Register type definitions. + 193:Drivers/CMSIS/Include/core_cm0.h **** @{ + 194:Drivers/CMSIS/Include/core_cm0.h **** */ + 195:Drivers/CMSIS/Include/core_cm0.h **** + 196:Drivers/CMSIS/Include/core_cm0.h **** /** + 197:Drivers/CMSIS/Include/core_cm0.h **** \brief Union type to access the Application Program Status Register (APSR). + 198:Drivers/CMSIS/Include/core_cm0.h **** */ + 199:Drivers/CMSIS/Include/core_cm0.h **** typedef union + 200:Drivers/CMSIS/Include/core_cm0.h **** { + 201:Drivers/CMSIS/Include/core_cm0.h **** struct + 202:Drivers/CMSIS/Include/core_cm0.h **** { + 203:Drivers/CMSIS/Include/core_cm0.h **** uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + 204:Drivers/CMSIS/Include/core_cm0.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 205:Drivers/CMSIS/Include/core_cm0.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 206:Drivers/CMSIS/Include/core_cm0.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 207:Drivers/CMSIS/Include/core_cm0.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 208:Drivers/CMSIS/Include/core_cm0.h **** } b; /*!< Structure used for bit access */ + 209:Drivers/CMSIS/Include/core_cm0.h **** uint32_t w; /*!< Type used for word access */ + 210:Drivers/CMSIS/Include/core_cm0.h **** } APSR_Type; + 211:Drivers/CMSIS/Include/core_cm0.h **** + 212:Drivers/CMSIS/Include/core_cm0.h **** /* APSR Register Definitions */ + 213:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_N_Pos 31U /*!< APSR + 214:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR + 215:Drivers/CMSIS/Include/core_cm0.h **** + 216:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_Z_Pos 30U /*!< APSR + 217:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR + 218:Drivers/CMSIS/Include/core_cm0.h **** + 219:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_C_Pos 29U /*!< APSR + 220:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR + 221:Drivers/CMSIS/Include/core_cm0.h **** + 222:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_V_Pos 28U /*!< APSR + 223:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR + 224:Drivers/CMSIS/Include/core_cm0.h **** + 225:Drivers/CMSIS/Include/core_cm0.h **** + 226:Drivers/CMSIS/Include/core_cm0.h **** /** + 227:Drivers/CMSIS/Include/core_cm0.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). + 228:Drivers/CMSIS/Include/core_cm0.h **** */ + 229:Drivers/CMSIS/Include/core_cm0.h **** typedef union + 230:Drivers/CMSIS/Include/core_cm0.h **** { + 231:Drivers/CMSIS/Include/core_cm0.h **** struct + 232:Drivers/CMSIS/Include/core_cm0.h **** { + 233:Drivers/CMSIS/Include/core_cm0.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 234:Drivers/CMSIS/Include/core_cm0.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + 235:Drivers/CMSIS/Include/core_cm0.h **** } b; /*!< Structure used for bit access */ + ARM GAS /tmp/cc58GRFF.s page 92 + + + 236:Drivers/CMSIS/Include/core_cm0.h **** uint32_t w; /*!< Type used for word access */ + 237:Drivers/CMSIS/Include/core_cm0.h **** } IPSR_Type; + 238:Drivers/CMSIS/Include/core_cm0.h **** + 239:Drivers/CMSIS/Include/core_cm0.h **** /* IPSR Register Definitions */ + 240:Drivers/CMSIS/Include/core_cm0.h **** #define IPSR_ISR_Pos 0U /*!< IPSR + 241:Drivers/CMSIS/Include/core_cm0.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR + 242:Drivers/CMSIS/Include/core_cm0.h **** + 243:Drivers/CMSIS/Include/core_cm0.h **** + 244:Drivers/CMSIS/Include/core_cm0.h **** /** + 245:Drivers/CMSIS/Include/core_cm0.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + 246:Drivers/CMSIS/Include/core_cm0.h **** */ + 247:Drivers/CMSIS/Include/core_cm0.h **** typedef union + 248:Drivers/CMSIS/Include/core_cm0.h **** { + 249:Drivers/CMSIS/Include/core_cm0.h **** struct + 250:Drivers/CMSIS/Include/core_cm0.h **** { + 251:Drivers/CMSIS/Include/core_cm0.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 252:Drivers/CMSIS/Include/core_cm0.h **** uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + 253:Drivers/CMSIS/Include/core_cm0.h **** uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + 254:Drivers/CMSIS/Include/core_cm0.h **** uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + 255:Drivers/CMSIS/Include/core_cm0.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 256:Drivers/CMSIS/Include/core_cm0.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 257:Drivers/CMSIS/Include/core_cm0.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 258:Drivers/CMSIS/Include/core_cm0.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 259:Drivers/CMSIS/Include/core_cm0.h **** } b; /*!< Structure used for bit access */ + 260:Drivers/CMSIS/Include/core_cm0.h **** uint32_t w; /*!< Type used for word access */ + 261:Drivers/CMSIS/Include/core_cm0.h **** } xPSR_Type; + 262:Drivers/CMSIS/Include/core_cm0.h **** + 263:Drivers/CMSIS/Include/core_cm0.h **** /* xPSR Register Definitions */ + 264:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_N_Pos 31U /*!< xPSR + 265:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR + 266:Drivers/CMSIS/Include/core_cm0.h **** + 267:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_Z_Pos 30U /*!< xPSR + 268:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR + 269:Drivers/CMSIS/Include/core_cm0.h **** + 270:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_C_Pos 29U /*!< xPSR + 271:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR + 272:Drivers/CMSIS/Include/core_cm0.h **** + 273:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_V_Pos 28U /*!< xPSR + 274:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR + 275:Drivers/CMSIS/Include/core_cm0.h **** + 276:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_T_Pos 24U /*!< xPSR + 277:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR + 278:Drivers/CMSIS/Include/core_cm0.h **** + 279:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_ISR_Pos 0U /*!< xPSR + 280:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR + 281:Drivers/CMSIS/Include/core_cm0.h **** + 282:Drivers/CMSIS/Include/core_cm0.h **** + 283:Drivers/CMSIS/Include/core_cm0.h **** /** + 284:Drivers/CMSIS/Include/core_cm0.h **** \brief Union type to access the Control Registers (CONTROL). + 285:Drivers/CMSIS/Include/core_cm0.h **** */ + 286:Drivers/CMSIS/Include/core_cm0.h **** typedef union + 287:Drivers/CMSIS/Include/core_cm0.h **** { + 288:Drivers/CMSIS/Include/core_cm0.h **** struct + 289:Drivers/CMSIS/Include/core_cm0.h **** { + 290:Drivers/CMSIS/Include/core_cm0.h **** uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + 291:Drivers/CMSIS/Include/core_cm0.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + 292:Drivers/CMSIS/Include/core_cm0.h **** uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + ARM GAS /tmp/cc58GRFF.s page 93 + + + 293:Drivers/CMSIS/Include/core_cm0.h **** } b; /*!< Structure used for bit access */ + 294:Drivers/CMSIS/Include/core_cm0.h **** uint32_t w; /*!< Type used for word access */ + 295:Drivers/CMSIS/Include/core_cm0.h **** } CONTROL_Type; + 296:Drivers/CMSIS/Include/core_cm0.h **** + 297:Drivers/CMSIS/Include/core_cm0.h **** /* CONTROL Register Definitions */ + 298:Drivers/CMSIS/Include/core_cm0.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT + 299:Drivers/CMSIS/Include/core_cm0.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT + 300:Drivers/CMSIS/Include/core_cm0.h **** + 301:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of group CMSIS_CORE */ + 302:Drivers/CMSIS/Include/core_cm0.h **** + 303:Drivers/CMSIS/Include/core_cm0.h **** + 304:Drivers/CMSIS/Include/core_cm0.h **** /** + 305:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_core_register + 306:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + 307:Drivers/CMSIS/Include/core_cm0.h **** \brief Type definitions for the NVIC Registers + 308:Drivers/CMSIS/Include/core_cm0.h **** @{ + 309:Drivers/CMSIS/Include/core_cm0.h **** */ + 310:Drivers/CMSIS/Include/core_cm0.h **** + 311:Drivers/CMSIS/Include/core_cm0.h **** /** + 312:Drivers/CMSIS/Include/core_cm0.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + 313:Drivers/CMSIS/Include/core_cm0.h **** */ + 314:Drivers/CMSIS/Include/core_cm0.h **** typedef struct + 315:Drivers/CMSIS/Include/core_cm0.h **** { + 316:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + 317:Drivers/CMSIS/Include/core_cm0.h **** uint32_t RESERVED0[31U]; + 318:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register + 319:Drivers/CMSIS/Include/core_cm0.h **** uint32_t RSERVED1[31U]; + 320:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * + 321:Drivers/CMSIS/Include/core_cm0.h **** uint32_t RESERVED2[31U]; + 322:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register + 323:Drivers/CMSIS/Include/core_cm0.h **** uint32_t RESERVED3[31U]; + 324:Drivers/CMSIS/Include/core_cm0.h **** uint32_t RESERVED4[64U]; + 325:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ + 326:Drivers/CMSIS/Include/core_cm0.h **** } NVIC_Type; + 327:Drivers/CMSIS/Include/core_cm0.h **** + 328:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of group CMSIS_NVIC */ + 329:Drivers/CMSIS/Include/core_cm0.h **** + 330:Drivers/CMSIS/Include/core_cm0.h **** + 331:Drivers/CMSIS/Include/core_cm0.h **** /** + 332:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_core_register + 333:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_SCB System Control Block (SCB) + 334:Drivers/CMSIS/Include/core_cm0.h **** \brief Type definitions for the System Control Block Registers + 335:Drivers/CMSIS/Include/core_cm0.h **** @{ + 336:Drivers/CMSIS/Include/core_cm0.h **** */ + 337:Drivers/CMSIS/Include/core_cm0.h **** + 338:Drivers/CMSIS/Include/core_cm0.h **** /** + 339:Drivers/CMSIS/Include/core_cm0.h **** \brief Structure type to access the System Control Block (SCB). + 340:Drivers/CMSIS/Include/core_cm0.h **** */ + 341:Drivers/CMSIS/Include/core_cm0.h **** typedef struct + 342:Drivers/CMSIS/Include/core_cm0.h **** { + 343:Drivers/CMSIS/Include/core_cm0.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + 344:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi + 345:Drivers/CMSIS/Include/core_cm0.h **** uint32_t RESERVED0; + 346:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset + 347:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + 348:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * + 349:Drivers/CMSIS/Include/core_cm0.h **** uint32_t RESERVED1; + ARM GAS /tmp/cc58GRFF.s page 94 + + + 350:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registe + 351:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State + 352:Drivers/CMSIS/Include/core_cm0.h **** } SCB_Type; + 353:Drivers/CMSIS/Include/core_cm0.h **** + 354:Drivers/CMSIS/Include/core_cm0.h **** /* SCB CPUID Register Definitions */ + 355:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB + 356:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB + 357:Drivers/CMSIS/Include/core_cm0.h **** + 358:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB + 359:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB + 360:Drivers/CMSIS/Include/core_cm0.h **** + 361:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB + 362:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB + 363:Drivers/CMSIS/Include/core_cm0.h **** + 364:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB + 365:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB + 366:Drivers/CMSIS/Include/core_cm0.h **** + 367:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB + 368:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB + 369:Drivers/CMSIS/Include/core_cm0.h **** + 370:Drivers/CMSIS/Include/core_cm0.h **** /* SCB Interrupt Control State Register Definitions */ + 371:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB + 372:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB + 373:Drivers/CMSIS/Include/core_cm0.h **** + 374:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB + 375:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB + 376:Drivers/CMSIS/Include/core_cm0.h **** + 377:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB + 378:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB + 379:Drivers/CMSIS/Include/core_cm0.h **** + 380:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB + 381:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB + 382:Drivers/CMSIS/Include/core_cm0.h **** + 383:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB + 384:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB + 385:Drivers/CMSIS/Include/core_cm0.h **** + 386:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB + 387:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB + 388:Drivers/CMSIS/Include/core_cm0.h **** + 389:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB + 390:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB + 391:Drivers/CMSIS/Include/core_cm0.h **** + 392:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB + 393:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB + 394:Drivers/CMSIS/Include/core_cm0.h **** + 395:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB + 396:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB + 397:Drivers/CMSIS/Include/core_cm0.h **** + 398:Drivers/CMSIS/Include/core_cm0.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ + 399:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB + 400:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB + 401:Drivers/CMSIS/Include/core_cm0.h **** + 402:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB + 403:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB + 404:Drivers/CMSIS/Include/core_cm0.h **** + 405:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB + 406:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB + ARM GAS /tmp/cc58GRFF.s page 95 + + + 407:Drivers/CMSIS/Include/core_cm0.h **** + 408:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB + 409:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB + 410:Drivers/CMSIS/Include/core_cm0.h **** + 411:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB + 412:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB + 413:Drivers/CMSIS/Include/core_cm0.h **** + 414:Drivers/CMSIS/Include/core_cm0.h **** /* SCB System Control Register Definitions */ + 415:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB + 416:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB + 417:Drivers/CMSIS/Include/core_cm0.h **** + 418:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB + 419:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB + 420:Drivers/CMSIS/Include/core_cm0.h **** + 421:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB + 422:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB + 423:Drivers/CMSIS/Include/core_cm0.h **** + 424:Drivers/CMSIS/Include/core_cm0.h **** /* SCB Configuration Control Register Definitions */ + 425:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB + 426:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB + 427:Drivers/CMSIS/Include/core_cm0.h **** + 428:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB + 429:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB + 430:Drivers/CMSIS/Include/core_cm0.h **** + 431:Drivers/CMSIS/Include/core_cm0.h **** /* SCB System Handler Control and State Register Definitions */ + 432:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB + 433:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB + 434:Drivers/CMSIS/Include/core_cm0.h **** + 435:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of group CMSIS_SCB */ + 436:Drivers/CMSIS/Include/core_cm0.h **** + 437:Drivers/CMSIS/Include/core_cm0.h **** + 438:Drivers/CMSIS/Include/core_cm0.h **** /** + 439:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_core_register + 440:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) + 441:Drivers/CMSIS/Include/core_cm0.h **** \brief Type definitions for the System Timer Registers. + 442:Drivers/CMSIS/Include/core_cm0.h **** @{ + 443:Drivers/CMSIS/Include/core_cm0.h **** */ + 444:Drivers/CMSIS/Include/core_cm0.h **** + 445:Drivers/CMSIS/Include/core_cm0.h **** /** + 446:Drivers/CMSIS/Include/core_cm0.h **** \brief Structure type to access the System Timer (SysTick). + 447:Drivers/CMSIS/Include/core_cm0.h **** */ + 448:Drivers/CMSIS/Include/core_cm0.h **** typedef struct + 449:Drivers/CMSIS/Include/core_cm0.h **** { + 450:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis + 451:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + 452:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * + 453:Drivers/CMSIS/Include/core_cm0.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + 454:Drivers/CMSIS/Include/core_cm0.h **** } SysTick_Type; + 455:Drivers/CMSIS/Include/core_cm0.h **** + 456:Drivers/CMSIS/Include/core_cm0.h **** /* SysTick Control / Status Register Definitions */ + 457:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT + 458:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT + 459:Drivers/CMSIS/Include/core_cm0.h **** + 460:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT + 461:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT + 462:Drivers/CMSIS/Include/core_cm0.h **** + 463:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT + ARM GAS /tmp/cc58GRFF.s page 96 + + + 464:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT + 465:Drivers/CMSIS/Include/core_cm0.h **** + 466:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT + 467:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT + 468:Drivers/CMSIS/Include/core_cm0.h **** + 469:Drivers/CMSIS/Include/core_cm0.h **** /* SysTick Reload Register Definitions */ + 470:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT + 471:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT + 472:Drivers/CMSIS/Include/core_cm0.h **** + 473:Drivers/CMSIS/Include/core_cm0.h **** /* SysTick Current Register Definitions */ + 474:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT + 475:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT + 476:Drivers/CMSIS/Include/core_cm0.h **** + 477:Drivers/CMSIS/Include/core_cm0.h **** /* SysTick Calibration Register Definitions */ + 478:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT + 479:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT + 480:Drivers/CMSIS/Include/core_cm0.h **** + 481:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT + 482:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT + 483:Drivers/CMSIS/Include/core_cm0.h **** + 484:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT + 485:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT + 486:Drivers/CMSIS/Include/core_cm0.h **** + 487:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of group CMSIS_SysTick */ + 488:Drivers/CMSIS/Include/core_cm0.h **** + 489:Drivers/CMSIS/Include/core_cm0.h **** + 490:Drivers/CMSIS/Include/core_cm0.h **** /** + 491:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_core_register + 492:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + 493:Drivers/CMSIS/Include/core_cm0.h **** \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible ove + 494:Drivers/CMSIS/Include/core_cm0.h **** Therefore they are not covered by the Cortex-M0 header file. + 495:Drivers/CMSIS/Include/core_cm0.h **** @{ + 496:Drivers/CMSIS/Include/core_cm0.h **** */ + 497:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of group CMSIS_CoreDebug */ + 498:Drivers/CMSIS/Include/core_cm0.h **** + 499:Drivers/CMSIS/Include/core_cm0.h **** + 500:Drivers/CMSIS/Include/core_cm0.h **** /** + 501:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_core_register + 502:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_core_bitfield Core register bit field macros + 503:Drivers/CMSIS/Include/core_cm0.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + 504:Drivers/CMSIS/Include/core_cm0.h **** @{ + 505:Drivers/CMSIS/Include/core_cm0.h **** */ + 506:Drivers/CMSIS/Include/core_cm0.h **** + 507:Drivers/CMSIS/Include/core_cm0.h **** /** + 508:Drivers/CMSIS/Include/core_cm0.h **** \brief Mask and shift a bit field value for use in a register bit range. + 509:Drivers/CMSIS/Include/core_cm0.h **** \param[in] field Name of the register bit field. + 510:Drivers/CMSIS/Include/core_cm0.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + 511:Drivers/CMSIS/Include/core_cm0.h **** \return Masked and shifted value. + 512:Drivers/CMSIS/Include/core_cm0.h **** */ + 513:Drivers/CMSIS/Include/core_cm0.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + 514:Drivers/CMSIS/Include/core_cm0.h **** + 515:Drivers/CMSIS/Include/core_cm0.h **** /** + 516:Drivers/CMSIS/Include/core_cm0.h **** \brief Mask and shift a register value to extract a bit filed value. + 517:Drivers/CMSIS/Include/core_cm0.h **** \param[in] field Name of the register bit field. + 518:Drivers/CMSIS/Include/core_cm0.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + 519:Drivers/CMSIS/Include/core_cm0.h **** \return Masked and shifted bit field value. + 520:Drivers/CMSIS/Include/core_cm0.h **** */ + ARM GAS /tmp/cc58GRFF.s page 97 + + + 521:Drivers/CMSIS/Include/core_cm0.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + 522:Drivers/CMSIS/Include/core_cm0.h **** + 523:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of group CMSIS_core_bitfield */ + 524:Drivers/CMSIS/Include/core_cm0.h **** + 525:Drivers/CMSIS/Include/core_cm0.h **** + 526:Drivers/CMSIS/Include/core_cm0.h **** /** + 527:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_core_register + 528:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_core_base Core Definitions + 529:Drivers/CMSIS/Include/core_cm0.h **** \brief Definitions for base addresses, unions, and structures. + 530:Drivers/CMSIS/Include/core_cm0.h **** @{ + 531:Drivers/CMSIS/Include/core_cm0.h **** */ + 532:Drivers/CMSIS/Include/core_cm0.h **** + 533:Drivers/CMSIS/Include/core_cm0.h **** /* Memory mapping of Core Hardware */ + 534:Drivers/CMSIS/Include/core_cm0.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas + 535:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + 536:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + 537:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas + 538:Drivers/CMSIS/Include/core_cm0.h **** + 539:Drivers/CMSIS/Include/core_cm0.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct + 540:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st + 541:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc + 542:Drivers/CMSIS/Include/core_cm0.h **** + 543:Drivers/CMSIS/Include/core_cm0.h **** + 544:Drivers/CMSIS/Include/core_cm0.h **** /*@} */ + 545:Drivers/CMSIS/Include/core_cm0.h **** + 546:Drivers/CMSIS/Include/core_cm0.h **** + 547:Drivers/CMSIS/Include/core_cm0.h **** + 548:Drivers/CMSIS/Include/core_cm0.h **** /******************************************************************************* + 549:Drivers/CMSIS/Include/core_cm0.h **** * Hardware Abstraction Layer + 550:Drivers/CMSIS/Include/core_cm0.h **** Core Function Interface contains: + 551:Drivers/CMSIS/Include/core_cm0.h **** - Core NVIC Functions + 552:Drivers/CMSIS/Include/core_cm0.h **** - Core SysTick Functions + 553:Drivers/CMSIS/Include/core_cm0.h **** - Core Register Access Functions + 554:Drivers/CMSIS/Include/core_cm0.h **** ******************************************************************************/ + 555:Drivers/CMSIS/Include/core_cm0.h **** /** + 556:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference + 557:Drivers/CMSIS/Include/core_cm0.h **** */ + 558:Drivers/CMSIS/Include/core_cm0.h **** + 559:Drivers/CMSIS/Include/core_cm0.h **** + 560:Drivers/CMSIS/Include/core_cm0.h **** + 561:Drivers/CMSIS/Include/core_cm0.h **** /* ########################## NVIC functions #################################### */ + 562:Drivers/CMSIS/Include/core_cm0.h **** /** + 563:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_Core_FunctionInterface + 564:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions + 565:Drivers/CMSIS/Include/core_cm0.h **** \brief Functions that manage interrupts and exceptions via the NVIC. + 566:Drivers/CMSIS/Include/core_cm0.h **** @{ + 567:Drivers/CMSIS/Include/core_cm0.h **** */ + 568:Drivers/CMSIS/Include/core_cm0.h **** + 569:Drivers/CMSIS/Include/core_cm0.h **** #ifdef CMSIS_NVIC_VIRTUAL + 570:Drivers/CMSIS/Include/core_cm0.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + 571:Drivers/CMSIS/Include/core_cm0.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + 572:Drivers/CMSIS/Include/core_cm0.h **** #endif + 573:Drivers/CMSIS/Include/core_cm0.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE + 574:Drivers/CMSIS/Include/core_cm0.h **** #else + 575:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + 576:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + 577:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ + ARM GAS /tmp/cc58GRFF.s page 98 + + + 578:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + 579:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ + 580:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + 581:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + 582:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + 583:Drivers/CMSIS/Include/core_cm0.h **** /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + 584:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_SetPriority __NVIC_SetPriority + 585:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_GetPriority __NVIC_GetPriority + 586:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_SystemReset __NVIC_SystemReset + 587:Drivers/CMSIS/Include/core_cm0.h **** #endif /* CMSIS_NVIC_VIRTUAL */ + 588:Drivers/CMSIS/Include/core_cm0.h **** + 589:Drivers/CMSIS/Include/core_cm0.h **** #ifdef CMSIS_VECTAB_VIRTUAL + 590:Drivers/CMSIS/Include/core_cm0.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + 591:Drivers/CMSIS/Include/core_cm0.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + 592:Drivers/CMSIS/Include/core_cm0.h **** #endif + 593:Drivers/CMSIS/Include/core_cm0.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE + 594:Drivers/CMSIS/Include/core_cm0.h **** #else + 595:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_SetVector __NVIC_SetVector + 596:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_GetVector __NVIC_GetVector + 597:Drivers/CMSIS/Include/core_cm0.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */ + 598:Drivers/CMSIS/Include/core_cm0.h **** + 599:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_USER_IRQ_OFFSET 16 + 600:Drivers/CMSIS/Include/core_cm0.h **** + 601:Drivers/CMSIS/Include/core_cm0.h **** + 602:Drivers/CMSIS/Include/core_cm0.h **** /* The following EXC_RETURN values are saved the LR on exception entry */ + 603:Drivers/CMSIS/Include/core_cm0.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret + 604:Drivers/CMSIS/Include/core_cm0.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu + 605:Drivers/CMSIS/Include/core_cm0.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu + 606:Drivers/CMSIS/Include/core_cm0.h **** + 607:Drivers/CMSIS/Include/core_cm0.h **** + 608:Drivers/CMSIS/Include/core_cm0.h **** /* Interrupt Priorities are WORD accessible only under Armv6-M */ + 609:Drivers/CMSIS/Include/core_cm0.h **** /* The following MACROS handle generation of the register offset and byte masks */ + 610:Drivers/CMSIS/Include/core_cm0.h **** #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) + 611:Drivers/CMSIS/Include/core_cm0.h **** #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) + 612:Drivers/CMSIS/Include/core_cm0.h **** #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + 613:Drivers/CMSIS/Include/core_cm0.h **** + 614:Drivers/CMSIS/Include/core_cm0.h **** #define __NVIC_SetPriorityGrouping(X) (void)(X) + 615:Drivers/CMSIS/Include/core_cm0.h **** #define __NVIC_GetPriorityGrouping() (0U) + 616:Drivers/CMSIS/Include/core_cm0.h **** + 617:Drivers/CMSIS/Include/core_cm0.h **** /** + 618:Drivers/CMSIS/Include/core_cm0.h **** \brief Enable Interrupt + 619:Drivers/CMSIS/Include/core_cm0.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. + 620:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Device specific interrupt number. + 621:Drivers/CMSIS/Include/core_cm0.h **** \note IRQn must not be negative. + 622:Drivers/CMSIS/Include/core_cm0.h **** */ + 623:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) + 624:Drivers/CMSIS/Include/core_cm0.h **** { + 625:Drivers/CMSIS/Include/core_cm0.h **** if ((int32_t)(IRQn) >= 0) + 626:Drivers/CMSIS/Include/core_cm0.h **** { + 627:Drivers/CMSIS/Include/core_cm0.h **** NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 628:Drivers/CMSIS/Include/core_cm0.h **** } + 629:Drivers/CMSIS/Include/core_cm0.h **** } + 630:Drivers/CMSIS/Include/core_cm0.h **** + 631:Drivers/CMSIS/Include/core_cm0.h **** + 632:Drivers/CMSIS/Include/core_cm0.h **** /** + 633:Drivers/CMSIS/Include/core_cm0.h **** \brief Get Interrupt Enable status + 634:Drivers/CMSIS/Include/core_cm0.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + ARM GAS /tmp/cc58GRFF.s page 99 + + + 635:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Device specific interrupt number. + 636:Drivers/CMSIS/Include/core_cm0.h **** \return 0 Interrupt is not enabled. + 637:Drivers/CMSIS/Include/core_cm0.h **** \return 1 Interrupt is enabled. + 638:Drivers/CMSIS/Include/core_cm0.h **** \note IRQn must not be negative. + 639:Drivers/CMSIS/Include/core_cm0.h **** */ + 640:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) + 641:Drivers/CMSIS/Include/core_cm0.h **** { + 642:Drivers/CMSIS/Include/core_cm0.h **** if ((int32_t)(IRQn) >= 0) + 643:Drivers/CMSIS/Include/core_cm0.h **** { + 644:Drivers/CMSIS/Include/core_cm0.h **** return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL) + 645:Drivers/CMSIS/Include/core_cm0.h **** } + 646:Drivers/CMSIS/Include/core_cm0.h **** else + 647:Drivers/CMSIS/Include/core_cm0.h **** { + 648:Drivers/CMSIS/Include/core_cm0.h **** return(0U); + 649:Drivers/CMSIS/Include/core_cm0.h **** } + 650:Drivers/CMSIS/Include/core_cm0.h **** } + 651:Drivers/CMSIS/Include/core_cm0.h **** + 652:Drivers/CMSIS/Include/core_cm0.h **** + 653:Drivers/CMSIS/Include/core_cm0.h **** /** + 654:Drivers/CMSIS/Include/core_cm0.h **** \brief Disable Interrupt + 655:Drivers/CMSIS/Include/core_cm0.h **** \details Disables a device specific interrupt in the NVIC interrupt controller. + 656:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Device specific interrupt number. + 657:Drivers/CMSIS/Include/core_cm0.h **** \note IRQn must not be negative. + 658:Drivers/CMSIS/Include/core_cm0.h **** */ + 659:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) + 660:Drivers/CMSIS/Include/core_cm0.h **** { + 661:Drivers/CMSIS/Include/core_cm0.h **** if ((int32_t)(IRQn) >= 0) + 662:Drivers/CMSIS/Include/core_cm0.h **** { + 663:Drivers/CMSIS/Include/core_cm0.h **** NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 664:Drivers/CMSIS/Include/core_cm0.h **** __DSB(); + 665:Drivers/CMSIS/Include/core_cm0.h **** __ISB(); + 666:Drivers/CMSIS/Include/core_cm0.h **** } + 667:Drivers/CMSIS/Include/core_cm0.h **** } + 668:Drivers/CMSIS/Include/core_cm0.h **** + 669:Drivers/CMSIS/Include/core_cm0.h **** + 670:Drivers/CMSIS/Include/core_cm0.h **** /** + 671:Drivers/CMSIS/Include/core_cm0.h **** \brief Get Pending Interrupt + 672:Drivers/CMSIS/Include/core_cm0.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe + 673:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Device specific interrupt number. + 674:Drivers/CMSIS/Include/core_cm0.h **** \return 0 Interrupt status is not pending. + 675:Drivers/CMSIS/Include/core_cm0.h **** \return 1 Interrupt status is pending. + 676:Drivers/CMSIS/Include/core_cm0.h **** \note IRQn must not be negative. + 677:Drivers/CMSIS/Include/core_cm0.h **** */ + 678:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) + 679:Drivers/CMSIS/Include/core_cm0.h **** { + 680:Drivers/CMSIS/Include/core_cm0.h **** if ((int32_t)(IRQn) >= 0) + 681:Drivers/CMSIS/Include/core_cm0.h **** { + 682:Drivers/CMSIS/Include/core_cm0.h **** return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL) + 683:Drivers/CMSIS/Include/core_cm0.h **** } + 684:Drivers/CMSIS/Include/core_cm0.h **** else + 685:Drivers/CMSIS/Include/core_cm0.h **** { + 686:Drivers/CMSIS/Include/core_cm0.h **** return(0U); + 687:Drivers/CMSIS/Include/core_cm0.h **** } + 688:Drivers/CMSIS/Include/core_cm0.h **** } + 689:Drivers/CMSIS/Include/core_cm0.h **** + 690:Drivers/CMSIS/Include/core_cm0.h **** + 691:Drivers/CMSIS/Include/core_cm0.h **** /** + ARM GAS /tmp/cc58GRFF.s page 100 + + + 692:Drivers/CMSIS/Include/core_cm0.h **** \brief Set Pending Interrupt + 693:Drivers/CMSIS/Include/core_cm0.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + 694:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Device specific interrupt number. + 695:Drivers/CMSIS/Include/core_cm0.h **** \note IRQn must not be negative. + 696:Drivers/CMSIS/Include/core_cm0.h **** */ + 697:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) + 698:Drivers/CMSIS/Include/core_cm0.h **** { + 699:Drivers/CMSIS/Include/core_cm0.h **** if ((int32_t)(IRQn) >= 0) + 700:Drivers/CMSIS/Include/core_cm0.h **** { + 701:Drivers/CMSIS/Include/core_cm0.h **** NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 702:Drivers/CMSIS/Include/core_cm0.h **** } + 703:Drivers/CMSIS/Include/core_cm0.h **** } + 704:Drivers/CMSIS/Include/core_cm0.h **** + 705:Drivers/CMSIS/Include/core_cm0.h **** + 706:Drivers/CMSIS/Include/core_cm0.h **** /** + 707:Drivers/CMSIS/Include/core_cm0.h **** \brief Clear Pending Interrupt + 708:Drivers/CMSIS/Include/core_cm0.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + 709:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Device specific interrupt number. + 710:Drivers/CMSIS/Include/core_cm0.h **** \note IRQn must not be negative. + 711:Drivers/CMSIS/Include/core_cm0.h **** */ + 712:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) + 713:Drivers/CMSIS/Include/core_cm0.h **** { + 714:Drivers/CMSIS/Include/core_cm0.h **** if ((int32_t)(IRQn) >= 0) + 715:Drivers/CMSIS/Include/core_cm0.h **** { + 716:Drivers/CMSIS/Include/core_cm0.h **** NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 717:Drivers/CMSIS/Include/core_cm0.h **** } + 718:Drivers/CMSIS/Include/core_cm0.h **** } + 719:Drivers/CMSIS/Include/core_cm0.h **** + 720:Drivers/CMSIS/Include/core_cm0.h **** + 721:Drivers/CMSIS/Include/core_cm0.h **** /** + 722:Drivers/CMSIS/Include/core_cm0.h **** \brief Set Interrupt Priority + 723:Drivers/CMSIS/Include/core_cm0.h **** \details Sets the priority of a device specific interrupt or a processor exception. + 724:Drivers/CMSIS/Include/core_cm0.h **** The interrupt number can be positive to specify a device specific interrupt, + 725:Drivers/CMSIS/Include/core_cm0.h **** or negative to specify a processor exception. + 726:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Interrupt number. + 727:Drivers/CMSIS/Include/core_cm0.h **** \param [in] priority Priority to set. + 728:Drivers/CMSIS/Include/core_cm0.h **** \note The priority cannot be set for every processor exception. + 729:Drivers/CMSIS/Include/core_cm0.h **** */ + 730:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) + 731:Drivers/CMSIS/Include/core_cm0.h **** { + 732:Drivers/CMSIS/Include/core_cm0.h **** if ((int32_t)(IRQn) >= 0) + 733:Drivers/CMSIS/Include/core_cm0.h **** { + 734:Drivers/CMSIS/Include/core_cm0.h **** NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn)) + 735:Drivers/CMSIS/Include/core_cm0.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 736:Drivers/CMSIS/Include/core_cm0.h **** } + 737:Drivers/CMSIS/Include/core_cm0.h **** else + 738:Drivers/CMSIS/Include/core_cm0.h **** { + 739:Drivers/CMSIS/Include/core_cm0.h **** SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn)) + 293 .loc 6 739 0 + 294 0028 0E49 ldr r1, .L12+4 + 295 002a 0B6A ldr r3, [r1, #32] + 296 002c 1B02 lsls r3, r3, #8 + 297 002e 1B0A lsrs r3, r3, #8 + 298 0030 C022 movs r2, #192 + 299 0032 1206 lsls r2, r2, #24 + 300 0034 1343 orrs r3, r2 + 301 0036 0B62 str r3, [r1, #32] + ARM GAS /tmp/cc58GRFF.s page 101 + + + 302 .LVL14: + 303 .LBE61: + 304 .LBE60: + 86:Src/main.c **** + 305 .loc 1 86 0 + 306 0038 FFF7FEFF bl SystemClock_Config + 307 .LVL15: + 93:Src/main.c **** /* USER CODE BEGIN 2 */ + 308 .loc 1 93 0 + 309 003c FFF7FEFF bl MX_GPIO_Init + 310 .LVL16: + 311 .L11: + 312 .LBB62: + 313 .LBB63: + 871:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 872:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 873:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 874:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Toggle data value for several pin of dedicated port. + 875:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll ODR ODy LL_GPIO_TogglePin + 876:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 877:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values: + 878:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 879:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 880:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 881:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 882:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 883:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 884:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 885:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 886:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 887:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 888:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 889:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 890:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 891:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 892:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 893:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 894:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL + 895:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 896:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 897:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) + 898:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 899:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** uint32_t odr = READ_REG(GPIOx->ODR); + 314 .loc 3 899 0 discriminator 1 + 315 0040 0949 ldr r1, .L12+8 + 316 0042 4869 ldr r0, [r1, #20] + 317 .LVL17: + 900:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); + 318 .loc 3 900 0 discriminator 1 + 319 0044 0304 lsls r3, r0, #16 + 320 0046 8022 movs r2, #128 + 321 0048 1203 lsls r2, r2, #12 + 322 004a 1340 ands r3, r2 + 323 004c 0822 movs r2, #8 + 324 004e 8243 bics r2, r0 + 325 0050 1343 orrs r3, r2 + 326 0052 8B61 str r3, [r1, #24] + ARM GAS /tmp/cc58GRFF.s page 102 + + + 327 .LVL18: + 328 .LBE63: + 329 .LBE62: + 104:Src/main.c **** /* USER CODE BEGIN 3 */ + 330 .loc 1 104 0 discriminator 1 + 331 0054 FA20 movs r0, #250 + 332 0056 4000 lsls r0, r0, #1 + 333 0058 FFF7FEFF bl LL_mDelay + 334 .LVL19: + 335 005c F0E7 b .L11 + 336 .L13: + 337 005e C046 .align 2 + 338 .L12: + 339 0060 00100240 .word 1073876992 + 340 0064 00ED00E0 .word -536810240 + 341 0068 00040048 .word 1207960576 + 342 .cfi_endproc + 343 .LFE417: + 345 .section .text.Error_Handler,"ax",%progbits + 346 .align 1 + 347 .global Error_Handler + 348 .syntax unified + 349 .code 16 + 350 .thumb_func + 351 .fpu softvfp + 353 Error_Handler: + 354 .LFB420: + 165:Src/main.c **** + 166:Src/main.c **** /* USER CODE BEGIN 4 */ + 167:Src/main.c **** + 168:Src/main.c **** /* USER CODE END 4 */ + 169:Src/main.c **** + 170:Src/main.c **** /** + 171:Src/main.c **** * @brief This function is executed in case of error occurrence. + 172:Src/main.c **** * @retval None + 173:Src/main.c **** */ + 174:Src/main.c **** void Error_Handler(void) + 175:Src/main.c **** { + 355 .loc 1 175 0 + 356 .cfi_startproc + 357 @ Volatile: function does not return. + 358 @ args = 0, pretend = 0, frame = 0 + 359 @ frame_needed = 0, uses_anonymous_args = 0 + 360 @ link register save eliminated. + 361 .LBB64: + 362 .LBB65: + 363 .file 7 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + ARM GAS /tmp/cc58GRFF.s page 103 + + + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + ARM GAS /tmp/cc58GRFF.s page 104 + + + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/cc58GRFF.s page 105 + + + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 364 .loc 7 142 0 + 365 .syntax divided + 366 @ 142 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 367 0000 72B6 cpsid i + 368 @ 0 "" 2 + 369 .thumb + 370 .syntax unified + 371 .L15: + 372 0002 FEE7 b .L15 + 373 .LBE65: + 374 .LBE64: + 375 .cfi_endproc + 376 .LFE420: + 378 .text + 379 .Letext0: + 380 .file 8 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h" + 381 .file 9 "/usr/include/newlib/machine/_default_types.h" + 382 .file 10 "/usr/include/newlib/sys/_stdint.h" + 383 .file 11 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h" + 384 .file 12 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h" + 385 .file 13 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h" + 386 .file 14 "" + ARM GAS /tmp/cc58GRFF.s page 106 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 main.c + /tmp/cc58GRFF.s:16 .text.MX_GPIO_Init:0000000000000000 $t + /tmp/cc58GRFF.s:22 .text.MX_GPIO_Init:0000000000000000 MX_GPIO_Init + /tmp/cc58GRFF.s:87 .text.MX_GPIO_Init:0000000000000038 $d + /tmp/cc58GRFF.s:93 .text.SystemClock_Config:0000000000000000 $t + /tmp/cc58GRFF.s:100 .text.SystemClock_Config:0000000000000000 SystemClock_Config + /tmp/cc58GRFF.s:226 .text.SystemClock_Config:0000000000000068 $d + /tmp/cc58GRFF.s:234 .text.main:0000000000000000 $t + /tmp/cc58GRFF.s:241 .text.main:0000000000000000 main + /tmp/cc58GRFF.s:339 .text.main:0000000000000060 $d + /tmp/cc58GRFF.s:346 .text.Error_Handler:0000000000000000 $t + /tmp/cc58GRFF.s:353 .text.Error_Handler:0000000000000000 Error_Handler + +UNDEFINED SYMBOLS +memset +LL_GPIO_Init +LL_Init1msTick +LL_SetSystemCoreClock +LL_mDelay diff --git a/bsl/makeLowLayer/build/stm32f0xx_it.lst b/bsl/makeLowLayer/build/stm32f0xx_it.lst new file mode 100644 index 0000000..5977cfb --- /dev/null +++ b/bsl/makeLowLayer/build/stm32f0xx_it.lst @@ -0,0 +1,283 @@ +ARM GAS /tmp/ccH6aSaL.s page 1 + + + 1 .cpu cortex-m0 + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32f0xx_it.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.NMI_Handler,"ax",%progbits + 16 .align 1 + 17 .global NMI_Handler + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 NMI_Handler: + 24 .LFB417: + 25 .file 1 "Src/stm32f0xx_it.c" + 1:Src/stm32f0xx_it.c **** /* USER CODE BEGIN Header */ + 2:Src/stm32f0xx_it.c **** /** + 3:Src/stm32f0xx_it.c **** ****************************************************************************** + 4:Src/stm32f0xx_it.c **** * @file stm32f0xx_it.c + 5:Src/stm32f0xx_it.c **** * @brief Interrupt Service Routines. + 6:Src/stm32f0xx_it.c **** ****************************************************************************** + 7:Src/stm32f0xx_it.c **** * @attention + 8:Src/stm32f0xx_it.c **** * + 9:Src/stm32f0xx_it.c **** *

© Copyright (c) 2021 STMicroelectronics. + 10:Src/stm32f0xx_it.c **** * All rights reserved.

+ 11:Src/stm32f0xx_it.c **** * + 12:Src/stm32f0xx_it.c **** * This software component is licensed by ST under BSD 3-Clause license, + 13:Src/stm32f0xx_it.c **** * the "License"; You may not use this file except in compliance with the + 14:Src/stm32f0xx_it.c **** * License. You may obtain a copy of the License at: + 15:Src/stm32f0xx_it.c **** * opensource.org/licenses/BSD-3-Clause + 16:Src/stm32f0xx_it.c **** * + 17:Src/stm32f0xx_it.c **** ****************************************************************************** + 18:Src/stm32f0xx_it.c **** */ + 19:Src/stm32f0xx_it.c **** /* USER CODE END Header */ + 20:Src/stm32f0xx_it.c **** + 21:Src/stm32f0xx_it.c **** /* Includes ------------------------------------------------------------------*/ + 22:Src/stm32f0xx_it.c **** #include "main.h" + 23:Src/stm32f0xx_it.c **** #include "stm32f0xx_it.h" + 24:Src/stm32f0xx_it.c **** /* Private includes ----------------------------------------------------------*/ + 25:Src/stm32f0xx_it.c **** /* USER CODE BEGIN Includes */ + 26:Src/stm32f0xx_it.c **** /* USER CODE END Includes */ + 27:Src/stm32f0xx_it.c **** + 28:Src/stm32f0xx_it.c **** /* Private typedef -----------------------------------------------------------*/ + 29:Src/stm32f0xx_it.c **** /* USER CODE BEGIN TD */ + 30:Src/stm32f0xx_it.c **** + 31:Src/stm32f0xx_it.c **** /* USER CODE END TD */ + 32:Src/stm32f0xx_it.c **** + 33:Src/stm32f0xx_it.c **** /* Private define ------------------------------------------------------------*/ + ARM GAS /tmp/ccH6aSaL.s page 2 + + + 34:Src/stm32f0xx_it.c **** /* USER CODE BEGIN PD */ + 35:Src/stm32f0xx_it.c **** + 36:Src/stm32f0xx_it.c **** /* USER CODE END PD */ + 37:Src/stm32f0xx_it.c **** + 38:Src/stm32f0xx_it.c **** /* Private macro -------------------------------------------------------------*/ + 39:Src/stm32f0xx_it.c **** /* USER CODE BEGIN PM */ + 40:Src/stm32f0xx_it.c **** + 41:Src/stm32f0xx_it.c **** /* USER CODE END PM */ + 42:Src/stm32f0xx_it.c **** + 43:Src/stm32f0xx_it.c **** /* Private variables ---------------------------------------------------------*/ + 44:Src/stm32f0xx_it.c **** /* USER CODE BEGIN PV */ + 45:Src/stm32f0xx_it.c **** + 46:Src/stm32f0xx_it.c **** /* USER CODE END PV */ + 47:Src/stm32f0xx_it.c **** + 48:Src/stm32f0xx_it.c **** /* Private function prototypes -----------------------------------------------*/ + 49:Src/stm32f0xx_it.c **** /* USER CODE BEGIN PFP */ + 50:Src/stm32f0xx_it.c **** + 51:Src/stm32f0xx_it.c **** /* USER CODE END PFP */ + 52:Src/stm32f0xx_it.c **** + 53:Src/stm32f0xx_it.c **** /* Private user code ---------------------------------------------------------*/ + 54:Src/stm32f0xx_it.c **** /* USER CODE BEGIN 0 */ + 55:Src/stm32f0xx_it.c **** + 56:Src/stm32f0xx_it.c **** /* USER CODE END 0 */ + 57:Src/stm32f0xx_it.c **** + 58:Src/stm32f0xx_it.c **** /* External variables --------------------------------------------------------*/ + 59:Src/stm32f0xx_it.c **** + 60:Src/stm32f0xx_it.c **** /* USER CODE BEGIN EV */ + 61:Src/stm32f0xx_it.c **** + 62:Src/stm32f0xx_it.c **** /* USER CODE END EV */ + 63:Src/stm32f0xx_it.c **** + 64:Src/stm32f0xx_it.c **** /******************************************************************************/ + 65:Src/stm32f0xx_it.c **** /* Cortex-M0 Processor Interruption and Exception Handlers */ + 66:Src/stm32f0xx_it.c **** /******************************************************************************/ + 67:Src/stm32f0xx_it.c **** /** + 68:Src/stm32f0xx_it.c **** * @brief This function handles Non maskable interrupt. + 69:Src/stm32f0xx_it.c **** */ + 70:Src/stm32f0xx_it.c **** void NMI_Handler(void) + 71:Src/stm32f0xx_it.c **** { + 26 .loc 1 71 0 + 27 .cfi_startproc + 28 @ Volatile: function does not return. + 29 @ args = 0, pretend = 0, frame = 0 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 @ link register save eliminated. + 32 .L2: + 33 0000 FEE7 b .L2 + 34 .cfi_endproc + 35 .LFE417: + 37 .section .text.HardFault_Handler,"ax",%progbits + 38 .align 1 + 39 .global HardFault_Handler + 40 .syntax unified + 41 .code 16 + 42 .thumb_func + 43 .fpu softvfp + 45 HardFault_Handler: + 46 .LFB418: + ARM GAS /tmp/ccH6aSaL.s page 3 + + + 72:Src/stm32f0xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + 73:Src/stm32f0xx_it.c **** + 74:Src/stm32f0xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */ + 75:Src/stm32f0xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + 76:Src/stm32f0xx_it.c **** while (1) + 77:Src/stm32f0xx_it.c **** { + 78:Src/stm32f0xx_it.c **** } + 79:Src/stm32f0xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */ + 80:Src/stm32f0xx_it.c **** } + 81:Src/stm32f0xx_it.c **** + 82:Src/stm32f0xx_it.c **** /** + 83:Src/stm32f0xx_it.c **** * @brief This function handles Hard fault interrupt. + 84:Src/stm32f0xx_it.c **** */ + 85:Src/stm32f0xx_it.c **** void HardFault_Handler(void) + 86:Src/stm32f0xx_it.c **** { + 47 .loc 1 86 0 + 48 .cfi_startproc + 49 @ Volatile: function does not return. + 50 @ args = 0, pretend = 0, frame = 0 + 51 @ frame_needed = 0, uses_anonymous_args = 0 + 52 @ link register save eliminated. + 53 .L4: + 54 0000 FEE7 b .L4 + 55 .cfi_endproc + 56 .LFE418: + 58 .section .text.SVC_Handler,"ax",%progbits + 59 .align 1 + 60 .global SVC_Handler + 61 .syntax unified + 62 .code 16 + 63 .thumb_func + 64 .fpu softvfp + 66 SVC_Handler: + 67 .LFB419: + 87:Src/stm32f0xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */ + 88:Src/stm32f0xx_it.c **** + 89:Src/stm32f0xx_it.c **** /* USER CODE END HardFault_IRQn 0 */ + 90:Src/stm32f0xx_it.c **** while (1) + 91:Src/stm32f0xx_it.c **** { + 92:Src/stm32f0xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + 93:Src/stm32f0xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */ + 94:Src/stm32f0xx_it.c **** } + 95:Src/stm32f0xx_it.c **** } + 96:Src/stm32f0xx_it.c **** + 97:Src/stm32f0xx_it.c **** /** + 98:Src/stm32f0xx_it.c **** * @brief This function handles System service call via SWI instruction. + 99:Src/stm32f0xx_it.c **** */ + 100:Src/stm32f0xx_it.c **** void SVC_Handler(void) + 101:Src/stm32f0xx_it.c **** { + 68 .loc 1 101 0 + 69 .cfi_startproc + 70 @ args = 0, pretend = 0, frame = 0 + 71 @ frame_needed = 0, uses_anonymous_args = 0 + 72 @ link register save eliminated. + 102:Src/stm32f0xx_it.c **** /* USER CODE BEGIN SVC_IRQn 0 */ + 103:Src/stm32f0xx_it.c **** + 104:Src/stm32f0xx_it.c **** /* USER CODE END SVC_IRQn 0 */ + ARM GAS /tmp/ccH6aSaL.s page 4 + + + 105:Src/stm32f0xx_it.c **** /* USER CODE BEGIN SVC_IRQn 1 */ + 106:Src/stm32f0xx_it.c **** + 107:Src/stm32f0xx_it.c **** /* USER CODE END SVC_IRQn 1 */ + 108:Src/stm32f0xx_it.c **** } + 73 .loc 1 108 0 + 74 @ sp needed + 75 0000 7047 bx lr + 76 .cfi_endproc + 77 .LFE419: + 79 .section .text.PendSV_Handler,"ax",%progbits + 80 .align 1 + 81 .global PendSV_Handler + 82 .syntax unified + 83 .code 16 + 84 .thumb_func + 85 .fpu softvfp + 87 PendSV_Handler: + 88 .LFB420: + 109:Src/stm32f0xx_it.c **** + 110:Src/stm32f0xx_it.c **** /** + 111:Src/stm32f0xx_it.c **** * @brief This function handles Pendable request for system service. + 112:Src/stm32f0xx_it.c **** */ + 113:Src/stm32f0xx_it.c **** void PendSV_Handler(void) + 114:Src/stm32f0xx_it.c **** { + 89 .loc 1 114 0 + 90 .cfi_startproc + 91 @ args = 0, pretend = 0, frame = 0 + 92 @ frame_needed = 0, uses_anonymous_args = 0 + 93 @ link register save eliminated. + 115:Src/stm32f0xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */ + 116:Src/stm32f0xx_it.c **** + 117:Src/stm32f0xx_it.c **** /* USER CODE END PendSV_IRQn 0 */ + 118:Src/stm32f0xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */ + 119:Src/stm32f0xx_it.c **** + 120:Src/stm32f0xx_it.c **** /* USER CODE END PendSV_IRQn 1 */ + 121:Src/stm32f0xx_it.c **** } + 94 .loc 1 121 0 + 95 @ sp needed + 96 0000 7047 bx lr + 97 .cfi_endproc + 98 .LFE420: + 100 .section .text.SysTick_Handler,"ax",%progbits + 101 .align 1 + 102 .global SysTick_Handler + 103 .syntax unified + 104 .code 16 + 105 .thumb_func + 106 .fpu softvfp + 108 SysTick_Handler: + 109 .LFB421: + 122:Src/stm32f0xx_it.c **** + 123:Src/stm32f0xx_it.c **** /** + 124:Src/stm32f0xx_it.c **** * @brief This function handles System tick timer. + 125:Src/stm32f0xx_it.c **** */ + 126:Src/stm32f0xx_it.c **** void SysTick_Handler(void) + 127:Src/stm32f0xx_it.c **** { + 110 .loc 1 127 0 + ARM GAS /tmp/ccH6aSaL.s page 5 + + + 111 .cfi_startproc + 112 @ args = 0, pretend = 0, frame = 0 + 113 @ frame_needed = 0, uses_anonymous_args = 0 + 114 @ link register save eliminated. + 128:Src/stm32f0xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */ + 129:Src/stm32f0xx_it.c **** + 130:Src/stm32f0xx_it.c **** /* USER CODE END SysTick_IRQn 0 */ + 131:Src/stm32f0xx_it.c **** + 132:Src/stm32f0xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */ + 133:Src/stm32f0xx_it.c **** + 134:Src/stm32f0xx_it.c **** /* USER CODE END SysTick_IRQn 1 */ + 135:Src/stm32f0xx_it.c **** } + 115 .loc 1 135 0 + 116 @ sp needed + 117 0000 7047 bx lr + 118 .cfi_endproc + 119 .LFE421: + 121 .text + 122 .Letext0: + 123 .file 2 "/usr/include/newlib/machine/_default_types.h" + 124 .file 3 "/usr/include/newlib/sys/_stdint.h" + 125 .file 4 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h" + 126 .file 5 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h" + ARM GAS /tmp/ccH6aSaL.s page 6 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f0xx_it.c + /tmp/ccH6aSaL.s:16 .text.NMI_Handler:0000000000000000 $t + /tmp/ccH6aSaL.s:23 .text.NMI_Handler:0000000000000000 NMI_Handler + /tmp/ccH6aSaL.s:38 .text.HardFault_Handler:0000000000000000 $t + /tmp/ccH6aSaL.s:45 .text.HardFault_Handler:0000000000000000 HardFault_Handler + /tmp/ccH6aSaL.s:59 .text.SVC_Handler:0000000000000000 $t + /tmp/ccH6aSaL.s:66 .text.SVC_Handler:0000000000000000 SVC_Handler + /tmp/ccH6aSaL.s:80 .text.PendSV_Handler:0000000000000000 $t + /tmp/ccH6aSaL.s:87 .text.PendSV_Handler:0000000000000000 PendSV_Handler + /tmp/ccH6aSaL.s:101 .text.SysTick_Handler:0000000000000000 $t + /tmp/ccH6aSaL.s:108 .text.SysTick_Handler:0000000000000000 SysTick_Handler + +NO UNDEFINED SYMBOLS diff --git a/bsl/makeLowLayer/build/stm32f0xx_ll_exti.lst b/bsl/makeLowLayer/build/stm32f0xx_ll_exti.lst new file mode 100644 index 0000000..dd9e0a8 --- /dev/null +++ b/bsl/makeLowLayer/build/stm32f0xx_ll_exti.lst @@ -0,0 +1,1417 @@ +ARM GAS /tmp/cc58HedN.s page 1 + + + 1 .cpu cortex-m0 + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32f0xx_ll_exti.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_EXTI_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_EXTI_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_EXTI_DeInit: + 24 .LFB56: + 25 .file 1 "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c" + 1:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @file stm32f0xx_ll_exti.c + 4:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @brief EXTI LL module driver. + 6:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** ****************************************************************************** + 7:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @attention + 8:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * + 9:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** *

© Copyright (c) 2016 STMicroelectronics. + 10:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * All rights reserved.

+ 11:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * + 12:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * This software component is licensed by ST under BSD 3-Clause license, + 13:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * the "License"; You may not use this file except in compliance with the + 14:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * License. You may obtain a copy of the License at: + 15:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * opensource.org/licenses/BSD-3-Clause + 16:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * + 17:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** ****************************************************************************** + 18:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** */ + 19:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 20:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** #if defined(USE_FULL_LL_DRIVER) + 21:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 22:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Includes ------------------------------------------------------------------*/ + 23:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** #include "stm32f0xx_ll_exti.h" + 24:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** #ifdef USE_FULL_ASSERT + 25:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** #include "stm32_assert.h" + 26:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** #else + 27:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** #define assert_param(expr) ((void)0U) + 28:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** #endif + 29:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 30:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /** @addtogroup STM32F0xx_LL_Driver + 31:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @{ + 32:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** */ + 33:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + ARM GAS /tmp/cc58HedN.s page 2 + + + 34:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** #if defined (EXTI) + 35:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 36:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /** @defgroup EXTI_LL EXTI + 37:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @{ + 38:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** */ + 39:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 40:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Private types -------------------------------------------------------------*/ + 41:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Private variables ---------------------------------------------------------*/ + 42:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Private constants ---------------------------------------------------------*/ + 43:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Private macros ------------------------------------------------------------*/ + 44:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /** @addtogroup EXTI_LL_Private_Macros + 45:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @{ + 46:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** */ + 47:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 48:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** #define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x0 + 49:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 50:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** #define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ + 51:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ + 52:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) + 53:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 54:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 55:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** #define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ + 56:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ + 57:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ + 58:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLIN + 59:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 60:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /** + 61:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @} + 62:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** */ + 63:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 64:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Private function prototypes -----------------------------------------------*/ + 65:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 66:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Exported functions --------------------------------------------------------*/ + 67:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /** @addtogroup EXTI_LL_Exported_Functions + 68:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @{ + 69:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** */ + 70:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 71:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /** @addtogroup EXTI_LL_EF_Init + 72:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @{ + 73:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** */ + 74:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 75:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /** + 76:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @brief De-initialize the EXTI registers to their default reset values. + 77:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @retval An ErrorStatus enumeration value: + 78:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * - SUCCESS: EXTI registers are de-initialized + 79:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * - ERROR: not applicable + 80:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** */ + 81:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** uint32_t LL_EXTI_DeInit(void) + 82:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** { + 26 .loc 1 82 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 83:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Interrupt mask register set to default reset values */ + 84:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** #if defined(STM32F030x6) || defined(STM32F031x6) ||defined(STM32F038xx) + 85:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_WriteReg(IMR, 0x0FF40000U); + ARM GAS /tmp/cc58HedN.s page 3 + + + 86:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** #elif defined(STM32F070x6) || defined(STM32F042x6) || defined(STM32F048xx) + 87:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_WriteReg(IMR, 0x7FF40000U); + 31 .loc 1 87 0 + 32 0000 054B ldr r3, .L2 + 33 0002 064A ldr r2, .L2+4 + 34 0004 1A60 str r2, [r3] + 88:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** #elif defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) + 89:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_WriteReg(IMR, 0x0F940000U); + 90:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** #else + 91:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_WriteReg(IMR, 0x7F840000U); + 92:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** #endif + 93:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Event mask register set to default reset values */ + 94:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_WriteReg(EMR, 0x00000000U); + 35 .loc 1 94 0 + 36 0006 0022 movs r2, #0 + 37 0008 5A60 str r2, [r3, #4] + 95:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Rising Trigger selection register set to default reset values */ + 96:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_WriteReg(RTSR, 0x00000000U); + 38 .loc 1 96 0 + 39 000a 9A60 str r2, [r3, #8] + 97:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Falling Trigger selection register set to default reset values */ + 98:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_WriteReg(FTSR, 0x00000000U); + 40 .loc 1 98 0 + 41 000c DA60 str r2, [r3, #12] + 99:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Software interrupt event register set to default reset values */ + 100:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_WriteReg(SWIER, 0x00000000U); + 42 .loc 1 100 0 + 43 000e 1A61 str r2, [r3, #16] + 101:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Pending register clear */ + 102:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_WriteReg(PR, 0x007BFFFFU); + 44 .loc 1 102 0 + 45 0010 034A ldr r2, .L2+8 + 46 0012 5A61 str r2, [r3, #20] + 103:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 104:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** return SUCCESS; + 105:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** } + 47 .loc 1 105 0 + 48 0014 0020 movs r0, #0 + 49 @ sp needed + 50 0016 7047 bx lr + 51 .L3: + 52 .align 2 + 53 .L2: + 54 0018 00040140 .word 1073808384 + 55 001c 0000F47F .word 2146697216 + 56 0020 FFFF7B00 .word 8126463 + 57 .cfi_endproc + 58 .LFE56: + 60 .section .text.LL_EXTI_Init,"ax",%progbits + 61 .align 1 + 62 .global LL_EXTI_Init + 63 .syntax unified + 64 .code 16 + 65 .thumb_func + 66 .fpu softvfp + 68 LL_EXTI_Init: + 69 .LFB57: + ARM GAS /tmp/cc58HedN.s page 4 + + + 106:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 107:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /** + 108:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. + 109:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. + 110:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @retval An ErrorStatus enumeration value: + 111:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * - SUCCESS: EXTI registers are initialized + 112:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * - ERROR: not applicable + 113:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** */ + 114:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) + 115:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** { + 70 .loc 1 115 0 + 71 .cfi_startproc + 72 @ args = 0, pretend = 0, frame = 0 + 73 @ frame_needed = 0, uses_anonymous_args = 0 + 74 .LVL0: + 75 0000 10B5 push {r4, lr} + 76 .LCFI0: + 77 .cfi_def_cfa_offset 8 + 78 .cfi_offset 4, -8 + 79 .cfi_offset 14, -4 + 80 .LVL1: + 116:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** ErrorStatus status = SUCCESS; + 117:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Check the parameters */ + 118:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); + 119:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); + 120:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); + 121:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 122:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* ENABLE LineCommand */ + 123:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** if (EXTI_InitStruct->LineCommand != DISABLE) + 81 .loc 1 123 0 + 82 0002 0379 ldrb r3, [r0, #4] + 83 0004 002B cmp r3, #0 + 84 0006 51D0 beq .L5 + 124:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** { + 125:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); + 126:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 127:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Configure EXTI Lines in range from 0 to 31 */ + 128:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) + 85 .loc 1 128 0 + 86 0008 0368 ldr r3, [r0] + 87 000a 002B cmp r3, #0 + 88 000c 5AD0 beq .L14 + 129:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** { + 130:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** switch (EXTI_InitStruct->Mode) + 89 .loc 1 130 0 + 90 000e 4279 ldrb r2, [r0, #5] + 91 0010 012A cmp r2, #1 + 92 0012 19D0 beq .L8 + 93 0014 002A cmp r2, #0 + 94 0016 03D0 beq .L9 + 95 0018 022A cmp r2, #2 + 96 001a 1FD0 beq .L10 + 131:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** { + 132:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** case LL_EXTI_MODE_IT: + 133:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* First Disable Event on provided Lines */ + 134:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + 135:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Then Enable IT on provided Lines */ + ARM GAS /tmp/cc58HedN.s page 5 + + + 136:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + 137:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** break; + 138:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** case LL_EXTI_MODE_EVENT: + 139:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* First Disable IT on provided Lines */ + 140:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + 141:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Then Enable Event on provided Lines */ + 142:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + 143:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** break; + 144:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** case LL_EXTI_MODE_IT_EVENT: + 145:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Directly Enable IT & Event on provided Lines */ + 146:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + 147:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + 148:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** break; + 149:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** default: + 150:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** status = ERROR; + 97 .loc 1 150 0 + 98 001c 0123 movs r3, #1 + 99 001e 08E0 b .L7 + 100 .L9: + 101 .LVL2: + 102 .LBB30: + 103 .LBB31: + 104 .file 2 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h" + 1:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @file stm32f0xx_ll_exti.h + 4:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @brief Header file of EXTI LL module. + 6:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** ****************************************************************************** + 7:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @attention + 8:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * + 9:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** *

© Copyright (c) 2016 STMicroelectronics. + 10:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * All rights reserved.

+ 11:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * + 12:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * This software component is licensed by ST under BSD 3-Clause license, + 13:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * the "License"; You may not use this file except in compliance with the + 14:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * License. You may obtain a copy of the License at: + 15:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * opensource.org/licenses/BSD-3-Clause + 16:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * + 17:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** ****************************************************************************** + 18:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 19:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 20:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 21:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #ifndef __STM32F0xx_LL_EXTI_H + 22:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define __STM32F0xx_LL_EXTI_H + 23:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 24:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #ifdef __cplusplus + 25:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** extern "C" { + 26:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif + 27:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 28:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /* Includes ------------------------------------------------------------------*/ + 29:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #include "stm32f0xx.h" + 30:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 31:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** @addtogroup STM32F0xx_LL_Driver + 32:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @{ + 33:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 34:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + ARM GAS /tmp/cc58HedN.s page 6 + + + 35:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined (EXTI) + 36:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 37:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** @defgroup EXTI_LL EXTI + 38:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @{ + 39:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 40:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 41:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /* Private types -------------------------------------------------------------*/ + 42:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /* Private variables ---------------------------------------------------------*/ + 43:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /* Private constants ---------------------------------------------------------*/ + 44:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /* Private Macros ------------------------------------------------------------*/ + 45:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(USE_FULL_LL_DRIVER) + 46:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + 47:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @{ + 48:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 49:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 50:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @} + 51:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 52:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif /*USE_FULL_LL_DRIVER*/ + 53:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /* Exported types ------------------------------------------------------------*/ + 54:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(USE_FULL_LL_DRIVER) + 55:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + 56:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @{ + 57:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 58:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** typedef struct + 59:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** { + 60:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 61:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines i + 62:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** This parameter can be any combination of @ref EXTI_LL_EC_LINE + 63:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 64:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + 65:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** This parameter can be set either to ENABLE or DISABLE */ + 66:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 67:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + 68:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + 69:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 70:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + 71:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ + 72:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } LL_EXTI_InitTypeDef; + 73:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 74:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 75:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @} + 76:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 77:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif /*USE_FULL_LL_DRIVER*/ + 78:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 79:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /* Exported constants --------------------------------------------------------*/ + 80:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + 81:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @{ + 82:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 83:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 84:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** @defgroup EXTI_LL_EC_LINE LINE + 85:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @{ + 86:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 87:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ + 88:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ + 89:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ + 90:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ + 91:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ + ARM GAS /tmp/cc58HedN.s page 7 + + + 92:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ + 93:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ + 94:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ + 95:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ + 96:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ + 97:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ + 98:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ + 99:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ + 100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ + 101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ + 102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ + 103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(EXTI_IMR_IM16) + 104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ + 105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif + 106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ + 107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(EXTI_IMR_IM18) + 108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ + 109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif + 110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ + 111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(EXTI_IMR_IM20) + 112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ + 113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif + 114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(EXTI_IMR_IM21) + 115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ + 116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif + 117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(EXTI_IMR_IM22) + 118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ + 119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif + 120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ + 121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(EXTI_IMR_IM24) + 122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ + 123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif + 124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(EXTI_IMR_IM25) + 125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ + 126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif + 127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(EXTI_IMR_IM26) + 128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ + 129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif + 130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(EXTI_IMR_IM27) + 131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ + 132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif + 133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(EXTI_IMR_IM28) + 134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ + 135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif + 136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(EXTI_IMR_IM29) + 137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ + 138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif + 139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(EXTI_IMR_IM30) + 140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ + 141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif + 142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(EXTI_IMR_IM31) + 143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ + 144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif + 145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ + 146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + ARM GAS /tmp/cc58HedN.s page 8 + + + 149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(USE_FULL_LL_DRIVER) + 151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ + 152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif /*USE_FULL_LL_DRIVER*/ + 153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 155:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @} + 156:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 157:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #if defined(USE_FULL_LL_DRIVER) + 158:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 159:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** @defgroup EXTI_LL_EC_MODE Mode + 160:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @{ + 161:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 162:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ + 163:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ + 164:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ + 165:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 166:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @} + 167:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 168:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 169:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + 170:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @{ + 171:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 172:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ + 173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ + 174:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ + 175:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + 176:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 177:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 178:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @} + 179:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 180:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 181:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 182:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #endif /*USE_FULL_LL_DRIVER*/ + 183:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 184:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 185:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 186:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @} + 187:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 189:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /* Exported macro ------------------------------------------------------------*/ + 190:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + 191:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @{ + 192:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 193:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 194:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + 195:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @{ + 196:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 197:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 198:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 199:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @brief Write a value in EXTI register + 200:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @param __REG__ Register to be written + 201:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @param __VALUE__ Value to be written in the register + 202:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @retval None + 203:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 204:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + 205:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + ARM GAS /tmp/cc58HedN.s page 9 + + + 206:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 207:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @brief Read a value in EXTI register + 208:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @param __REG__ Register to be read + 209:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @retval Register value + 210:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 211:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** #define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) + 212:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 213:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @} + 214:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 215:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 216:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 217:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 218:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @} + 219:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 220:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 221:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 222:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 223:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /* Exported functions --------------------------------------------------------*/ + 224:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + 225:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @{ + 226:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 227:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** @defgroup EXTI_LL_EF_IT_Management IT_Management + 228:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @{ + 229:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 230:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 231:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 232:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + 233:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note The reset value for the direct or internal lines (see RM) + 234:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * is set to 1 in order to enable the interrupt by default. + 235:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * Bits are set automatically at Power on. + 236:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 + 237:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 238:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 239:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 240:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 241:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 242:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 243:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 244:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 245:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 246:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 247:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 248:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 249:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 250:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 251:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 252:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 253:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 254:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 255:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 256:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 257:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 258:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 259:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 260:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 261:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 262:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24 + ARM GAS /tmp/cc58HedN.s page 10 + + + 263:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_25 + 264:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_26 + 265:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_27 + 266:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_28 + 267:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 268:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 269:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 270:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 271:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 272:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @retval None + 273:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 274:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) + 275:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** { + 276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** SET_BIT(EXTI->IMR, ExtiLine); + 277:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 278:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 279:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 280:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + 281:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note The reset value for the direct or internal lines (see RM) + 282:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * is set to 1 in order to enable the interrupt by default. + 283:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * Bits are set automatically at Power on. + 284:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 + 285:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 286:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 287:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 288:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 289:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 290:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 291:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 292:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 293:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 294:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 295:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 296:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 297:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 298:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 299:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 300:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 301:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 302:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 303:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 304:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 305:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 306:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 307:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 308:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 309:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 310:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24 + 311:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_25 + 312:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_26 + 313:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_27 + 314:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_28 + 315:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 316:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 317:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 318:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 319:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + ARM GAS /tmp/cc58HedN.s page 11 + + + 320:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @retval None + 321:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 322:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) + 323:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** { + 324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** CLEAR_BIT(EXTI->IMR, ExtiLine); + 325:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 326:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 327:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 328:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 329:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + 330:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note The reset value for the direct or internal lines (see RM) + 331:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * is set to 1 in order to enable the interrupt by default. + 332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * Bits are set automatically at Power on. + 333:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 + 334:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 335:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 336:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 337:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 338:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 339:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 340:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 341:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 342:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 343:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 344:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 345:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 346:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 347:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 348:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 349:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 350:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 351:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 352:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 353:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 354:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 355:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 356:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 357:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 358:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 359:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24 + 360:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_25 + 361:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_26 + 362:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_27 + 363:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_28 + 364:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 365:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 366:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 367:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 368:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 369:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @retval State of bit (1 or 0). + 370:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 371:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) + 372:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** { + 373:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); + 374:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 375:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 376:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + ARM GAS /tmp/cc58HedN.s page 12 + + + 377:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 378:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @} + 379:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 380:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 381:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** @defgroup EXTI_LL_EF_Event_Management Event_Management + 382:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @{ + 383:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 384:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 385:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 386:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + 387:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 + 388:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 389:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 390:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 391:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 392:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 393:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 394:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 395:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 396:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 397:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 398:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 399:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 400:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 401:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 402:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 403:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 404:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 405:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 406:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 407:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 408:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 409:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 410:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 411:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 412:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 413:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24 + 414:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_25 + 415:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_26 + 416:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_27 + 417:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_28 + 418:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 419:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 420:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 421:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 422:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 423:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @retval None + 424:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 425:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) + 426:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** { + 427:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** SET_BIT(EXTI->EMR, ExtiLine); + 428:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 429:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 430:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 431:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 432:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 433:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + ARM GAS /tmp/cc58HedN.s page 13 + + + 434:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 + 435:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 436:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 437:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 438:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 439:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 440:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 441:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 442:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 443:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 444:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 445:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 446:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 447:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 448:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 449:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 450:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 451:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 452:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 453:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 454:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 455:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 456:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 457:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 458:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 459:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 460:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24 + 461:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_25 + 462:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_26 + 463:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_27 + 464:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_28 + 465:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 466:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 467:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 468:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 469:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 470:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @retval None + 471:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 472:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) + 473:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** { + 474:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** CLEAR_BIT(EXTI->EMR, ExtiLine); + 105 .loc 2 474 0 + 106 0020 294A ldr r2, .L20 + 107 0022 5168 ldr r1, [r2, #4] + 108 0024 9943 bics r1, r3 + 109 0026 5160 str r1, [r2, #4] + 110 .LVL3: + 111 .LBE31: + 112 .LBE30: + 113 .LBB32: + 114 .LBB33: + 276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 115 .loc 2 276 0 + 116 0028 1368 ldr r3, [r2] + 117 002a 0168 ldr r1, [r0] + 118 002c 0B43 orrs r3, r1 + 119 002e 1360 str r3, [r2] + ARM GAS /tmp/cc58HedN.s page 14 + + + 120 .LVL4: + 121 .LBE33: + 122 .LBE32: + 116:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Check the parameters */ + 123 .loc 1 116 0 + 124 0030 0023 movs r3, #0 + 125 .LVL5: + 126 .L7: + 151:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** break; + 152:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** } + 153:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + 127 .loc 1 153 0 + 128 0032 8279 ldrb r2, [r0, #6] + 129 0034 002A cmp r2, #0 + 130 0036 43D0 beq .L6 + 154:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** { + 155:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** switch (EXTI_InitStruct->Trigger) + 131 .loc 1 155 0 + 132 0038 022A cmp r2, #2 + 133 003a 23D0 beq .L11 + 134 003c 032A cmp r2, #3 + 135 003e 2BD0 beq .L12 + 136 0040 012A cmp r2, #1 + 137 0042 15D0 beq .L19 + 156:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** { + 157:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** case LL_EXTI_TRIGGER_RISING: + 158:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* First Disable Falling Trigger on provided Lines */ + 159:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + 160:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Then Enable Rising Trigger on provided Lines */ + 161:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + 162:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** break; + 163:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** case LL_EXTI_TRIGGER_FALLING: + 164:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* First Disable Rising Trigger on provided Lines */ + 165:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + 166:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Then Enable Falling Trigger on provided Lines */ + 167:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + 168:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** break; + 169:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** case LL_EXTI_TRIGGER_RISING_FALLING: + 170:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + 171:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + 172:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** break; + 173:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** default: + 174:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** status = ERROR; + 138 .loc 1 174 0 + 139 0044 0123 movs r3, #1 + 140 .LVL6: + 141 0046 3BE0 b .L6 + 142 .LVL7: + 143 .L8: + 144 .LBB34: + 145 .LBB35: + 324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 146 .loc 2 324 0 + 147 0048 1F4A ldr r2, .L20 + 148 004a 1168 ldr r1, [r2] + 149 004c 9943 bics r1, r3 + 150 004e 1160 str r1, [r2] + ARM GAS /tmp/cc58HedN.s page 15 + + + 151 .LVL8: + 152 .LBE35: + 153 .LBE34: + 154 .LBB36: + 155 .LBB37: + 427:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 156 .loc 2 427 0 + 157 0050 5368 ldr r3, [r2, #4] + 158 0052 0168 ldr r1, [r0] + 159 0054 0B43 orrs r3, r1 + 160 0056 5360 str r3, [r2, #4] + 161 .LVL9: + 162 .LBE37: + 163 .LBE36: + 116:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Check the parameters */ + 164 .loc 1 116 0 + 165 0058 0023 movs r3, #0 + 166 005a EAE7 b .L7 + 167 .LVL10: + 168 .L10: + 169 .LBB38: + 170 .LBB39: + 276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 171 .loc 2 276 0 + 172 005c 1A4A ldr r2, .L20 + 173 005e 1168 ldr r1, [r2] + 174 0060 0B43 orrs r3, r1 + 175 .LVL11: + 176 0062 1360 str r3, [r2] + 177 .LVL12: + 178 .LBE39: + 179 .LBE38: + 180 .LBB40: + 181 .LBB41: + 427:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 182 .loc 2 427 0 + 183 0064 5368 ldr r3, [r2, #4] + 184 0066 0168 ldr r1, [r0] + 185 0068 0B43 orrs r3, r1 + 186 006a 5360 str r3, [r2, #4] + 187 .LVL13: + 188 .LBE41: + 189 .LBE40: + 116:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Check the parameters */ + 190 .loc 1 116 0 + 191 006c 0023 movs r3, #0 + 192 006e E0E7 b .L7 + 193 .LVL14: + 194 .L19: + 195 .LBB42: + 196 .LBB43: + 475:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 476:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 477:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 478:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 479:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + 480:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 + ARM GAS /tmp/cc58HedN.s page 16 + + + 481:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 482:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 483:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 484:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 485:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 486:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 487:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 488:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 489:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 490:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 491:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 492:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 493:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 494:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 495:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 496:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 497:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 498:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 499:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 500:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 501:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 502:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 503:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 504:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 505:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 506:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24 + 507:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_25 + 508:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_26 + 509:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_27 + 510:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_28 + 511:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 512:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 513:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 514:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 515:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 516:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @retval State of bit (1 or 0). + 517:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 518:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) + 519:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** { + 520:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); + 521:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 522:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 523:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 524:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 525:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 526:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @} + 527:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 528:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 529:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + 530:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @{ + 531:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 532:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 533:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 534:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + 535:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note The configurable wakeup lines are edge-triggered. No glitch must be + 536:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * generated on these lines. If a rising edge on a configurable interrupt + 537:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * line occurs during a write operation in the EXTI_RTSR register, the + ARM GAS /tmp/cc58HedN.s page 17 + + + 538:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * pending bit is not set. + 539:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * Rising and falling edge triggers can be set for + 540:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * the same interrupt line. In this case, both generate a trigger + 541:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * condition. + 542:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 + 543:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @param ExtiLine This parameter can be a combination of the following values: + 544:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 545:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 546:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 547:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 548:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 549:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 550:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 551:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 552:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 553:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 554:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 555:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 556:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 557:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 558:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 559:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 560:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 561:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 562:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 563:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 564:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 565:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 566:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 567:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 568:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 569:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 570:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @retval None + 571:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 572:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) + 573:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** { + 574:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** SET_BIT(EXTI->RTSR, ExtiLine); + 575:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 576:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 577:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 578:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 579:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 580:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + 581:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note The configurable wakeup lines are edge-triggered. No glitch must be + 582:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * generated on these lines. If a rising edge on a configurable interrupt + 583:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * line occurs during a write operation in the EXTI_RTSR register, the + 584:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * pending bit is not set. + 585:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * Rising and falling edge triggers can be set for + 586:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * the same interrupt line. In this case, both generate a trigger + 587:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * condition. + 588:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 + 589:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @param ExtiLine This parameter can be a combination of the following values: + 590:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 591:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 592:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 593:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 594:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + ARM GAS /tmp/cc58HedN.s page 18 + + + 595:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 596:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 597:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 598:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 599:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 600:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 601:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 602:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 603:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 604:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 605:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 606:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 607:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 608:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 609:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 610:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 611:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 612:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 613:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 614:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 615:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 616:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @retval None + 617:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 618:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) + 619:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** { + 620:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** CLEAR_BIT(EXTI->RTSR, ExtiLine); + 621:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 622:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 623:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 624:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 625:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 626:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + 627:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 + 628:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @param ExtiLine This parameter can be a combination of the following values: + 629:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 630:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 631:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 632:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 633:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 634:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 635:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 636:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 637:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 638:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 639:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 640:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 641:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 642:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 643:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 644:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 645:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 646:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 647:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 648:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 649:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 650:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 651:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + ARM GAS /tmp/cc58HedN.s page 19 + + + 652:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 653:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 654:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 655:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @retval State of bit (1 or 0). + 656:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 657:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) + 658:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** { + 659:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); + 660:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 661:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 662:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 663:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 664:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @} + 665:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 666:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 667:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + 668:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @{ + 669:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 670:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 671:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 672:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + 673:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note The configurable wakeup lines are edge-triggered. No glitch must be + 674:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * generated on these lines. If a falling edge on a configurable interrupt + 675:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * line occurs during a write operation in the EXTI_FTSR register, the + 676:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * pending bit is not set. + 677:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * Rising and falling edge triggers can be set for + 678:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * the same interrupt line. In this case, both generate a trigger + 679:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * condition. + 680:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 + 681:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @param ExtiLine This parameter can be a combination of the following values: + 682:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 683:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 684:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 685:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 686:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 687:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 688:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 689:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 690:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 691:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 692:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 693:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 694:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 695:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 696:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 697:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 698:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 699:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 700:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 701:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 702:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 703:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 704:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 705:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 706:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 707:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 708:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @retval None + ARM GAS /tmp/cc58HedN.s page 20 + + + 709:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 710:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) + 711:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** { + 712:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** SET_BIT(EXTI->FTSR, ExtiLine); + 713:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 714:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 715:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 716:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** /** + 717:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + 718:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note The configurable wakeup lines are edge-triggered. No glitch must be + 719:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * generated on these lines. If a Falling edge on a configurable interrupt + 720:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * line occurs during a write operation in the EXTI_FTSR register, the + 721:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * pending bit is not set. + 722:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * Rising and falling edge triggers can be set for the same interrupt line. + 723:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * In this case, both generate a trigger condition. + 724:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 + 725:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @param ExtiLine This parameter can be a combination of the following values: + 726:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 727:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 728:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 729:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 730:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 731:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 732:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 733:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 734:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 735:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 736:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 737:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 738:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 739:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 740:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 741:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 742:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 743:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 744:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 745:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 746:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 747:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 748:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_29 + 749:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_30 + 750:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_31 + 751:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 752:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** * @retval None + 753:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** */ + 754:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) + 755:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** { + 756:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** CLEAR_BIT(EXTI->FTSR, ExtiLine); + 197 .loc 2 756 0 + 198 0070 154A ldr r2, .L20 + 199 0072 D168 ldr r1, [r2, #12] + 200 0074 0468 ldr r4, [r0] + 201 0076 A143 bics r1, r4 + 202 0078 D160 str r1, [r2, #12] + 203 .LVL15: + 204 .LBE43: + 205 .LBE42: + ARM GAS /tmp/cc58HedN.s page 21 + + + 161:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** break; + 206 .loc 1 161 0 + 207 007a 0168 ldr r1, [r0] + 208 .LVL16: + 209 .LBB44: + 210 .LBB45: + 574:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 211 .loc 2 574 0 + 212 007c 9068 ldr r0, [r2, #8] + 213 .LVL17: + 214 007e 0143 orrs r1, r0 + 215 .LVL18: + 216 0080 9160 str r1, [r2, #8] + 217 .LVL19: + 218 0082 1DE0 b .L6 + 219 .LVL20: + 220 .L11: + 221 .LBE45: + 222 .LBE44: + 223 .LBB46: + 224 .LBB47: + 620:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 225 .loc 2 620 0 + 226 0084 104A ldr r2, .L20 + 227 0086 9168 ldr r1, [r2, #8] + 228 0088 0468 ldr r4, [r0] + 229 008a A143 bics r1, r4 + 230 008c 9160 str r1, [r2, #8] + 231 .LVL21: + 232 .LBE47: + 233 .LBE46: + 167:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** break; + 234 .loc 1 167 0 + 235 008e 0168 ldr r1, [r0] + 236 .LVL22: + 237 .LBB48: + 238 .LBB49: + 712:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 239 .loc 2 712 0 + 240 0090 D068 ldr r0, [r2, #12] + 241 .LVL23: + 242 0092 0143 orrs r1, r0 + 243 .LVL24: + 244 0094 D160 str r1, [r2, #12] + 245 .LVL25: + 246 0096 13E0 b .L6 + 247 .LVL26: + 248 .L12: + 249 .LBE49: + 250 .LBE48: + 251 .LBB50: + 252 .LBB51: + 574:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** + 253 .loc 2 574 0 + 254 0098 0B4A ldr r2, .L20 + 255 009a 9168 ldr r1, [r2, #8] + 256 009c 0468 ldr r4, [r0] + ARM GAS /tmp/cc58HedN.s page 22 + + + 257 009e 2143 orrs r1, r4 + 258 00a0 9160 str r1, [r2, #8] + 259 .LVL27: + 260 .LBE51: + 261 .LBE50: + 171:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** break; + 262 .loc 1 171 0 + 263 00a2 0168 ldr r1, [r0] + 264 .LVL28: + 265 .LBB52: + 266 .LBB53: + 712:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 267 .loc 2 712 0 + 268 00a4 D068 ldr r0, [r2, #12] + 269 .LVL29: + 270 00a6 0143 orrs r1, r0 + 271 .LVL30: + 272 00a8 D160 str r1, [r2, #12] + 273 .LVL31: + 274 00aa 09E0 b .L6 + 275 .LVL32: + 276 .L5: + 277 .LBE53: + 278 .LBE52: + 279 .LBB54: + 280 .LBB55: + 324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 281 .loc 2 324 0 + 282 00ac 064B ldr r3, .L20 + 283 00ae 1A68 ldr r2, [r3] + 284 00b0 0168 ldr r1, [r0] + 285 00b2 8A43 bics r2, r1 + 286 00b4 1A60 str r2, [r3] + 287 .LVL33: + 288 .LBE55: + 289 .LBE54: + 175:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** break; + 176:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** } + 177:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** } + 178:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** } + 179:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** } + 180:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* DISABLE LineCommand */ + 181:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** else + 182:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** { + 183:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* De-configure EXTI Lines in range from 0 to 31 */ + 184:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + 185:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + 290 .loc 1 185 0 + 291 00b6 0168 ldr r1, [r0] + 292 .LVL34: + 293 .LBB56: + 294 .LBB57: + 474:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h **** } + 295 .loc 2 474 0 + 296 00b8 5A68 ldr r2, [r3, #4] + 297 00ba 8A43 bics r2, r1 + 298 00bc 5A60 str r2, [r3, #4] + ARM GAS /tmp/cc58HedN.s page 23 + + + 299 .LBE57: + 300 .LBE56: + 116:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Check the parameters */ + 301 .loc 1 116 0 + 302 00be 0023 movs r3, #0 + 303 .LVL35: + 304 .L6: + 186:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** } + 187:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** return status; + 188:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** } + 305 .loc 1 188 0 + 306 00c0 1800 movs r0, r3 + 307 @ sp needed + 308 00c2 10BD pop {r4, pc} + 309 .LVL36: + 310 .L14: + 116:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /* Check the parameters */ + 311 .loc 1 116 0 + 312 00c4 0023 movs r3, #0 + 313 00c6 FBE7 b .L6 + 314 .L21: + 315 .align 2 + 316 .L20: + 317 00c8 00040140 .word 1073808384 + 318 .cfi_endproc + 319 .LFE57: + 321 .section .text.LL_EXTI_StructInit,"ax",%progbits + 322 .align 1 + 323 .global LL_EXTI_StructInit + 324 .syntax unified + 325 .code 16 + 326 .thumb_func + 327 .fpu softvfp + 329 LL_EXTI_StructInit: + 330 .LFB58: + 189:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** + 190:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** /** + 191:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. + 192:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. + 193:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** * @retval None + 194:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** */ + 195:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) + 196:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** { + 331 .loc 1 196 0 + 332 .cfi_startproc + 333 @ args = 0, pretend = 0, frame = 0 + 334 @ frame_needed = 0, uses_anonymous_args = 0 + 335 @ link register save eliminated. + 336 .LVL37: + 197:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; + 337 .loc 1 197 0 + 338 0000 0023 movs r3, #0 + 339 0002 0360 str r3, [r0] + 198:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** EXTI_InitStruct->LineCommand = DISABLE; + 340 .loc 1 198 0 + 341 0004 0371 strb r3, [r0, #4] + 199:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; + ARM GAS /tmp/cc58HedN.s page 24 + + + 342 .loc 1 199 0 + 343 0006 4371 strb r3, [r0, #5] + 200:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; + 344 .loc 1 200 0 + 345 0008 0233 adds r3, r3, #2 + 346 000a 8371 strb r3, [r0, #6] + 201:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c **** } + 347 .loc 1 201 0 + 348 @ sp needed + 349 000c 7047 bx lr + 350 .cfi_endproc + 351 .LFE58: + 353 .text + 354 .Letext0: + 355 .file 3 "/usr/include/newlib/machine/_default_types.h" + 356 .file 4 "/usr/include/newlib/sys/_stdint.h" + 357 .file 5 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h" + 358 .file 6 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h" + 359 .file 7 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h" + ARM GAS /tmp/cc58HedN.s page 25 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f0xx_ll_exti.c + /tmp/cc58HedN.s:16 .text.LL_EXTI_DeInit:0000000000000000 $t + /tmp/cc58HedN.s:23 .text.LL_EXTI_DeInit:0000000000000000 LL_EXTI_DeInit + /tmp/cc58HedN.s:54 .text.LL_EXTI_DeInit:0000000000000018 $d + /tmp/cc58HedN.s:61 .text.LL_EXTI_Init:0000000000000000 $t + /tmp/cc58HedN.s:68 .text.LL_EXTI_Init:0000000000000000 LL_EXTI_Init + /tmp/cc58HedN.s:317 .text.LL_EXTI_Init:00000000000000c8 $d + /tmp/cc58HedN.s:322 .text.LL_EXTI_StructInit:0000000000000000 $t + /tmp/cc58HedN.s:329 .text.LL_EXTI_StructInit:0000000000000000 LL_EXTI_StructInit + +NO UNDEFINED SYMBOLS diff --git a/bsl/makeLowLayer/build/stm32f0xx_ll_gpio.lst b/bsl/makeLowLayer/build/stm32f0xx_ll_gpio.lst new file mode 100644 index 0000000..3f78fa5 --- /dev/null +++ b/bsl/makeLowLayer/build/stm32f0xx_ll_gpio.lst @@ -0,0 +1,1732 @@ +ARM GAS /tmp/ccjsaEK1.s page 1 + + + 1 .cpu cortex-m0 + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32f0xx_ll_gpio.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_GPIO_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_GPIO_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_GPIO_DeInit: + 24 .LFB78: + 25 .file 1 "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c" + 1:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @file stm32f0xx_ll_gpio.c + 4:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @brief GPIO LL module driver. + 6:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ****************************************************************************** + 7:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @attention + 8:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * + 9:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** *

© Copyright (c) 2016 STMicroelectronics. + 10:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * All rights reserved.

+ 11:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * + 12:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * This software component is licensed by ST under BSD 3-Clause license, + 13:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * the "License"; You may not use this file except in compliance with the + 14:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * License. You may obtain a copy of the License at: + 15:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * opensource.org/licenses/BSD-3-Clause + 16:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * + 17:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ****************************************************************************** + 18:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** */ + 19:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 20:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #if defined(USE_FULL_LL_DRIVER) + 21:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 22:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Includes ------------------------------------------------------------------*/ + 23:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #include "stm32f0xx_ll_gpio.h" + 24:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #include "stm32f0xx_ll_bus.h" + 25:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #ifdef USE_FULL_ASSERT + 26:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #include "stm32_assert.h" + 27:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #else + 28:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #define assert_param(expr) ((void)0U) + 29:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #endif + 30:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 31:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /** @addtogroup STM32F0xx_LL_Driver + 32:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @{ + 33:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** */ + ARM GAS /tmp/ccjsaEK1.s page 2 + + + 34:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 35:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || + 36:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 37:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /** @addtogroup GPIO_LL + 38:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @{ + 39:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** */ + 40:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /** MISRA C:2012 deviation rule has been granted for following rules: + 41:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + 42:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * range of the shift operator in following API : + 43:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * LL_GPIO_Init + 44:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * LL_GPIO_DeInit + 45:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * LL_GPIO_SetPinMode + 46:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * LL_GPIO_GetPinMode + 47:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * LL_GPIO_SetPinSpeed + 48:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * LL_GPIO_GetPinSpeed + 49:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * LL_GPIO_SetPinPull + 50:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * LL_GPIO_GetPinPull + 51:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * LL_GPIO_GetAFPin_0_7 + 52:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * LL_GPIO_SetAFPin_0_7 + 53:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * LL_GPIO_SetAFPin_8_15 + 54:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * LL_GPIO_GetAFPin_8_15 + 55:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** */ + 56:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 57:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Private types -------------------------------------------------------------*/ + 58:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Private variables ---------------------------------------------------------*/ + 59:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Private constants ---------------------------------------------------------*/ + 60:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Private macros ------------------------------------------------------------*/ + 61:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /** @addtogroup GPIO_LL_Private_Macros + 62:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @{ + 63:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** */ + 64:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #define IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN + 65:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 66:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ + 67:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ + 68:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ + 69:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_MODE_ANALOG)) + 70:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 71:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ + 72:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) + 73:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 74:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ + 75:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ + 76:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)) + 77:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 78:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ + 79:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_PULL_UP) ||\ + 80:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_PULL_DOWN)) + 81:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 82:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ + 83:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_1 ) ||\ + 84:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_2 ) ||\ + 85:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_3 ) ||\ + 86:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_4 ) ||\ + 87:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_5 ) ||\ + 88:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_6 ) ||\ + 89:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_7 )) + 90:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /** + ARM GAS /tmp/ccjsaEK1.s page 3 + + + 91:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @} + 92:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** */ + 93:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 94:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Private function prototypes -----------------------------------------------*/ + 95:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 96:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Exported functions --------------------------------------------------------*/ + 97:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /** @addtogroup GPIO_LL_Exported_Functions + 98:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @{ + 99:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** */ + 100:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 101:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /** @addtogroup GPIO_LL_EF_Init + 102:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @{ + 103:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** */ + 104:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 105:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /** + 106:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @brief De-initialize GPIO registers (Registers restored to their default values). + 107:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @param GPIOx GPIO Port + 108:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @retval An ErrorStatus enumeration value: + 109:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * - SUCCESS: GPIO registers are de-initialized + 110:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * - ERROR: Wrong GPIO Port + 111:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** */ + 112:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) + 113:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 26 .loc 1 113 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 114:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ErrorStatus status = SUCCESS; + 115:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 116:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Check the parameters */ + 117:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + 118:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 119:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Force and Release reset on clock of GPIOx Port */ + 120:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** if (GPIOx == GPIOA) + 32 .loc 1 120 0 + 33 0000 9023 movs r3, #144 + 34 0002 DB05 lsls r3, r3, #23 + 35 0004 9842 cmp r0, r3 + 36 0006 0AD0 beq .L7 + 121:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 122:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA); + 123:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA); + 124:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 125:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** else if (GPIOx == GPIOB) + 37 .loc 1 125 0 + 38 0008 1D4B ldr r3, .L11 + 39 000a 9842 cmp r0, r3 + 40 000c 13D0 beq .L8 + 126:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 127:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB); + 128:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB); + 129:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 130:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** else if (GPIOx == GPIOC) + 41 .loc 1 130 0 + 42 000e 1D4B ldr r3, .L11+4 + ARM GAS /tmp/ccjsaEK1.s page 4 + + + 43 0010 9842 cmp r0, r3 + 44 0012 1CD0 beq .L9 + 131:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 132:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC); + 133:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC); + 134:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 135:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #if defined(GPIOD) + 136:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** else if (GPIOx == GPIOD) + 137:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 138:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD); + 139:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD); + 140:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 141:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #endif /* GPIOD */ + 142:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #if defined(GPIOE) + 143:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** else if (GPIOx == GPIOE) + 144:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 145:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE); + 146:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE); + 147:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 148:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #endif /* GPIOE */ + 149:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #if defined(GPIOF) + 150:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** else if (GPIOx == GPIOF) + 45 .loc 1 150 0 + 46 0014 1C4B ldr r3, .L11+8 + 47 0016 9842 cmp r0, r3 + 48 0018 25D0 beq .L10 + 151:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 152:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF); + 153:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF); + 154:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 155:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** #endif /* GPIOF */ + 156:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** else + 157:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 158:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** status = ERROR; + 49 .loc 1 158 0 + 50 001a 0120 movs r0, #1 + 51 .LVL1: + 52 001c 0AE0 b .L3 + 53 .LVL2: + 54 .L7: + 55 .LBB30: + 56 .LBB31: + 57 .file 2 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h" + 1:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @file stm32f0xx_ll_bus.h + 4:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 7:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** [..] + 11:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + ARM GAS /tmp/ccjsaEK1.s page 5 + + + 15:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 17:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** [..] + 18:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 22:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @attention + 25:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 26:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** *

© Copyright (c) 2016 STMicroelectronics. + 27:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * All rights reserved.

+ 28:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 29:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * This software component is licensed by ST under BSD 3-Clause license, + 30:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * the "License"; You may not use this file except in compliance with the + 31:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * License. You may obtain a copy of the License at: + 32:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * opensource.org/licenses/BSD-3-Clause + 33:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 34:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** ****************************************************************************** + 35:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 36:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 37:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 38:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #ifndef __STM32F0xx_LL_BUS_H + 39:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define __STM32F0xx_LL_BUS_H + 40:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 41:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #ifdef __cplusplus + 42:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** extern "C" { + 43:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif + 44:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 45:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 46:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #include "stm32f0xx.h" + 47:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 48:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @addtogroup STM32F0xx_LL_Driver + 49:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 50:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 51:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 52:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(RCC) + 53:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 54:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 55:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 56:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 57:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 58:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 59:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 60:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 61:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 62:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 63:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 64:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 65:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 66:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 67:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 68:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 69:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 70:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 71:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + ARM GAS /tmp/ccjsaEK1.s page 6 + + + 72:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 73:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 74:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 75:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN + 76:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(DMA2) + 77:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN + 78:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*DMA2*/ + 79:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN + 80:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN + 81:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN + 82:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN + 83:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN + 84:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN + 85:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(GPIOD) + 86:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN + 87:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*GPIOD*/ + 88:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(GPIOE) + 89:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN + 90:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*GPIOE*/ + 91:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN + 92:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(TSC) + 93:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN + 94:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*TSC*/ + 95:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 96:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @} + 97:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 98:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 99:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(TIM2) + 104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN + 105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*TIM2*/ + 106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN + 107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(TIM6) + 108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN + 109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*TIM6*/ + 110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(TIM7) + 111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN + 112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*TIM7*/ + 113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN + 114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN + 115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(SPI2) + 116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN + 117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*SPI2*/ + 118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART2) + 119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN + 120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /* USART2 */ + 121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART3) + 122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN + 123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /* USART3 */ + 124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART4) + 125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN + 126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /* USART4 */ + 127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART5) + 128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN + ARM GAS /tmp/ccjsaEK1.s page 7 + + + 129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /* USART5 */ + 130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN + 131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(I2C2) + 132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN + 133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*I2C2*/ + 134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USB) + 135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN + 136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /* USB */ + 137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(CAN) + 138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN + 139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*CAN*/ + 140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(CRS) + 141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN + 142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*CRS*/ + 143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN + 144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(DAC) + 145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN + 146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*DAC*/ + 147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(CEC) + 148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN + 149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*CEC*/ + 150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @} + 152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + 155:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 156:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 157:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 158:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN + 159:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN + 160:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART8) + 161:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN + 162:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*USART8*/ + 163:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART7) + 164:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN + 165:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*USART7*/ + 166:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART6) + 167:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN + 168:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*USART6*/ + 169:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN + 170:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN + 171:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN + 172:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(TIM15) + 173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN + 174:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*TIM15*/ + 175:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN + 176:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN + 177:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN + 178:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 179:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @} + 180:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 181:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 182:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 183:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @} + 184:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 185:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + ARM GAS /tmp/ccjsaEK1.s page 8 + + + 186:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 187:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 189:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 190:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 191:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 192:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 193:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 194:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 195:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 196:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 197:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 198:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n + 199:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n + 200:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n + 201:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n + 202:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + 203:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + 204:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + 205:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + 206:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n + 207:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + 208:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + 209:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock + 210:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 211:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 212:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + 213:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 214:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + 215:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 216:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 217:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 218:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 219:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + 220:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + 221:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 222:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 223:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 224:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 225:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 226:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 227:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 228:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 229:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __IO uint32_t tmpreg; + 230:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 231:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 232:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 233:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** (void)tmpreg; + 234:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 235:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 236:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 237:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 238:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + 239:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + 240:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n + 241:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n + 242:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + ARM GAS /tmp/ccjsaEK1.s page 9 + + + 243:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + 244:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + 245:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + 246:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + 247:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + 248:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + 249:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock + 250:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 251:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 252:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + 253:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 254:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + 255:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 256:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 257:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 258:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 259:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + 260:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + 261:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 262:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 263:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 264:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 265:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 266:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 267:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 268:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 269:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + 270:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 271:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 272:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 273:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 274:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n + 275:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + 281:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + 282:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n + 283:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + 284:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + 285:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock + 286:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 287:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 288:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + 289:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 290:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + 291:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 292:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 293:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 294:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 295:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + 296:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + 297:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 298:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 299:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + ARM GAS /tmp/ccjsaEK1.s page 10 + + + 300:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 301:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 302:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 303:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 304:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 305:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 306:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 307:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 308:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 309:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 310:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + 311:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + 312:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + 313:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + 314:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + 315:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + 316:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset + 317:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 318:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 319:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 320:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 321:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 322:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + 323:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + 324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 325:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 326:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 327:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 328:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 329:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 330:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 331:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 58 .loc 2 332 0 + 59 001e 1B4B ldr r3, .L11+12 + 60 0020 996A ldr r1, [r3, #40] + 61 0022 8022 movs r2, #128 + 62 0024 9202 lsls r2, r2, #10 + 63 0026 0A43 orrs r2, r1 + 64 0028 9A62 str r2, [r3, #40] + 65 .LVL3: + 66 .LBE31: + 67 .LBE30: + 68 .LBB32: + 69 .LBB33: + 333:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 334:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 335:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 336:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 337:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + 338:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + 339:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + 340:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + 341:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + 342:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + 343:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset + 344:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + ARM GAS /tmp/ccjsaEK1.s page 11 + + + 345:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 346:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 347:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 348:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 349:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + 350:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + 351:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 352:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 353:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 354:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 355:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 356:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 357:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 358:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 359:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 70 .loc 2 359 0 + 71 002a 9A6A ldr r2, [r3, #40] + 72 002c 1849 ldr r1, .L11+16 + 73 002e 0A40 ands r2, r1 + 74 0030 9A62 str r2, [r3, #40] + 75 .LBE33: + 76 .LBE32: + 114:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 77 .loc 1 114 0 + 78 0032 0020 movs r0, #0 + 79 .LVL4: + 80 .L3: + 159:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 160:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 161:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** return (status); + 162:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 81 .loc 1 162 0 + 82 @ sp needed + 83 0034 7047 bx lr + 84 .LVL5: + 85 .L8: + 86 .LBB34: + 87 .LBB35: + 332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 88 .loc 2 332 0 + 89 0036 154B ldr r3, .L11+12 + 90 0038 996A ldr r1, [r3, #40] + 91 003a 8022 movs r2, #128 + 92 003c D202 lsls r2, r2, #11 + 93 003e 0A43 orrs r2, r1 + 94 0040 9A62 str r2, [r3, #40] + 95 .LVL6: + 96 .LBE35: + 97 .LBE34: + 98 .LBB36: + 99 .LBB37: + 100 .loc 2 359 0 + 101 0042 9A6A ldr r2, [r3, #40] + 102 0044 1349 ldr r1, .L11+20 + 103 0046 0A40 ands r2, r1 + 104 0048 9A62 str r2, [r3, #40] + 105 .LBE37: + ARM GAS /tmp/ccjsaEK1.s page 12 + + + 106 .LBE36: + 114:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 107 .loc 1 114 0 + 108 004a 0020 movs r0, #0 + 109 .LVL7: + 110 004c F2E7 b .L3 + 111 .LVL8: + 112 .L9: + 113 .LBB38: + 114 .LBB39: + 332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 115 .loc 2 332 0 + 116 004e 0F4B ldr r3, .L11+12 + 117 0050 996A ldr r1, [r3, #40] + 118 0052 8022 movs r2, #128 + 119 0054 1203 lsls r2, r2, #12 + 120 0056 0A43 orrs r2, r1 + 121 0058 9A62 str r2, [r3, #40] + 122 .LVL9: + 123 .LBE39: + 124 .LBE38: + 125 .LBB40: + 126 .LBB41: + 127 .loc 2 359 0 + 128 005a 9A6A ldr r2, [r3, #40] + 129 005c 0E49 ldr r1, .L11+24 + 130 005e 0A40 ands r2, r1 + 131 0060 9A62 str r2, [r3, #40] + 132 .LBE41: + 133 .LBE40: + 114:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 134 .loc 1 114 0 + 135 0062 0020 movs r0, #0 + 136 .LVL10: + 137 0064 E6E7 b .L3 + 138 .LVL11: + 139 .L10: + 140 .LBB42: + 141 .LBB43: + 332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 142 .loc 2 332 0 + 143 0066 094B ldr r3, .L11+12 + 144 0068 996A ldr r1, [r3, #40] + 145 006a 8022 movs r2, #128 + 146 006c D203 lsls r2, r2, #15 + 147 006e 0A43 orrs r2, r1 + 148 0070 9A62 str r2, [r3, #40] + 149 .LVL12: + 150 .LBE43: + 151 .LBE42: + 152 .LBB44: + 153 .LBB45: + 154 .loc 2 359 0 + 155 0072 9A6A ldr r2, [r3, #40] + 156 0074 0949 ldr r1, .L11+28 + 157 0076 0A40 ands r2, r1 + 158 0078 9A62 str r2, [r3, #40] + ARM GAS /tmp/ccjsaEK1.s page 13 + + + 159 .LBE45: + 160 .LBE44: + 114:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 161 .loc 1 114 0 + 162 007a 0020 movs r0, #0 + 163 .LVL13: + 164 007c DAE7 b .L3 + 165 .L12: + 166 007e C046 .align 2 + 167 .L11: + 168 0080 00040048 .word 1207960576 + 169 0084 00080048 .word 1207961600 + 170 0088 00140048 .word 1207964672 + 171 008c 00100240 .word 1073876992 + 172 0090 FFFFFDFF .word -131073 + 173 0094 FFFFFBFF .word -262145 + 174 0098 FFFFF7FF .word -524289 + 175 009c FFFFBFFF .word -4194305 + 176 .cfi_endproc + 177 .LFE78: + 179 .section .text.LL_GPIO_Init,"ax",%progbits + 180 .align 1 + 181 .global LL_GPIO_Init + 182 .syntax unified + 183 .code 16 + 184 .thumb_func + 185 .fpu softvfp + 187 LL_GPIO_Init: + 188 .LFB79: + 163:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 164:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /** + 165:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. + 166:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @param GPIOx GPIO Port + 167:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + 168:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * that contains the configuration information for the specified GPIO peripheral. + 169:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @retval An ErrorStatus enumeration value: + 170:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content + 171:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * - ERROR: Not applicable + 172:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** */ + 173:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) + 174:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 189 .loc 1 174 0 + 190 .cfi_startproc + 191 @ args = 0, pretend = 0, frame = 0 + 192 @ frame_needed = 0, uses_anonymous_args = 0 + 193 .LVL14: + 194 0000 F0B5 push {r4, r5, r6, r7, lr} + 195 .LCFI0: + 196 .cfi_def_cfa_offset 20 + 197 .cfi_offset 4, -20 + 198 .cfi_offset 5, -16 + 199 .cfi_offset 6, -12 + 200 .cfi_offset 7, -8 + 201 .cfi_offset 14, -4 + 202 .LVL15: + 175:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** uint32_t pinpos; + 176:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** uint32_t currentpin; + ARM GAS /tmp/ccjsaEK1.s page 14 + + + 177:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 178:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Check the parameters */ + 179:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + 180:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); + 181:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); + 182:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); + 183:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 184:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* ------------------------- Configure the port pins ---------------- */ + 185:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Initialize pinpos on first pin set */ + 186:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** pinpos = 0; + 203 .loc 1 186 0 + 204 0002 0022 movs r2, #0 + 187:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 188:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Configure the port pins */ + 189:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u) + 205 .loc 1 189 0 + 206 0004 14E0 b .L14 + 207 .LVL16: + 208 .L16: + 209 .LBB46: + 210 .LBB47: + 211 .file 3 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h" + 1:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @file stm32f0xx_ll_gpio.h + 4:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Header file of GPIO LL module. + 6:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** ****************************************************************************** + 7:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @attention + 8:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * + 9:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** *

© Copyright (c) 2016 STMicroelectronics. + 10:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * All rights reserved.

+ 11:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * + 12:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * This software component is licensed by ST under BSD 3-Clause license, + 13:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * the "License"; You may not use this file except in compliance with the + 14:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * License. You may obtain a copy of the License at: + 15:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * opensource.org/licenses/BSD-3-Clause + 16:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * + 17:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** ****************************************************************************** + 18:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 19:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 20:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 21:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #ifndef __STM32F0xx_LL_GPIO_H + 22:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define __STM32F0xx_LL_GPIO_H + 23:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 24:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #ifdef __cplusplus + 25:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** extern "C" { + 26:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #endif + 27:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 28:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Includes ------------------------------------------------------------------*/ + 29:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #include "stm32f0xx.h" + 30:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 31:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @addtogroup STM32F0xx_LL_Driver + 32:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 33:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 34:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 35:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || + ARM GAS /tmp/ccjsaEK1.s page 15 + + + 36:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 37:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL GPIO + 38:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 39:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 40:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 41:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Private types -------------------------------------------------------------*/ + 42:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Private variables ---------------------------------------------------------*/ + 43:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Private constants ---------------------------------------------------------*/ + 44:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Private macros ------------------------------------------------------------*/ + 45:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #if defined(USE_FULL_LL_DRIVER) + 46:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + 47:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 48:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 49:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 50:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 51:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 52:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 53:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #endif /*USE_FULL_LL_DRIVER*/ + 54:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 55:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Exported types ------------------------------------------------------------*/ + 56:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #if defined(USE_FULL_LL_DRIVER) + 57:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + 58:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 59:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 60:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 61:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 62:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief LL GPIO Init Structure definition + 63:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 64:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** typedef struct + 65:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 66:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + 67:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** This parameter can be any value of @ref GPIO_LL_EC_PIN */ + 68:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 69:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + 70:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_MODE. + 71:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 72:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi + 73:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 74:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** uint32_t Speed; /*!< Specifies the speed for the selected pins. + 75:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_SPEED. + 76:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 77:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi + 78:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 79:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + 80:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + 81:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 82:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi + 83:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 84:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + 85:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_PULL. + 86:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 87:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi + 88:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 89:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + 90:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_AF. + 91:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 92:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi + ARM GAS /tmp/ccjsaEK1.s page 16 + + + 93:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } LL_GPIO_InitTypeDef; + 94:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 95:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 96:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 97:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 98:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #endif /* USE_FULL_LL_DRIVER */ + 99:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Exported constants --------------------------------------------------------*/ + 101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + 102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_PIN PIN + 106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ + 109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ + 110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ + 111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ + 112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ + 113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ + 114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ + 115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ + 116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ + 117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ + 118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ + 119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ + 120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ + 121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ + 122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ + 123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ + 124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ + 125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ + 126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ + 127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ + 128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ + 129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** GPIO_BSRR_BS_15) /*!< Select all pins */ + 130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_MODE Mode + 135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ + 138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ + 139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode + 140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ + 141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_OUTPUT Output Type + 146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ + 149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type * + ARM GAS /tmp/ccjsaEK1.s page 17 + + + 150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_SPEED Output Speed + 155:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 156:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 157:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ + 158:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEEDR0_0 /*!< Select I/O medium output sp + 159:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEEDR0 /*!< Select I/O high output spee + 160:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 161:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 162:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 163:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW + 164:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM + 165:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_HIGH + 166:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 167:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + 168:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 169:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 170:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ + 171:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ + 172:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ + 173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 174:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 175:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 176:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 177:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_AF Alternate Function + 178:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 179:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 180:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ + 181:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ + 182:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ + 183:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ + 184:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ + 185:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ + 186:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ + 187:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ + 188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 189:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 190:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 191:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 192:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 193:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 194:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 195:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 196:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Exported macro ------------------------------------------------------------*/ + 197:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + 198:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 199:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 200:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 201:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + 202:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 203:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 204:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 205:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 206:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Write a value in GPIO register + ARM GAS /tmp/ccjsaEK1.s page 18 + + + 207:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param __INSTANCE__ GPIO Instance + 208:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param __REG__ Register to be written + 209:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param __VALUE__ Value to be written in the register + 210:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 211:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 212:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALU + 213:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 214:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 215:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Read a value in GPIO register + 216:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param __INSTANCE__ GPIO Instance + 217:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param __REG__ Register to be read + 218:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval Register value + 219:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 220:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 221:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 222:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 223:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 224:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 225:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 226:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @} + 227:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 228:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 229:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /* Exported functions --------------------------------------------------------*/ + 230:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + 231:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 232:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 233:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 234:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + 235:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @{ + 236:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 237:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 238:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 239:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Configure gpio mode for a dedicated pin on dedicated port. + 240:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + 241:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 242:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll MODER MODEy LL_GPIO_SetPinMode + 243:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 244:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 245:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 246:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 247:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 248:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 249:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 250:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 251:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 252:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 253:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 254:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 255:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 256:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 257:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 258:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 259:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 260:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 261:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Mode This parameter can be one of the following values: + 262:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_INPUT + 263:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_OUTPUT + ARM GAS /tmp/ccjsaEK1.s page 19 + + + 264:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ALTERNATE + 265:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ANALOG + 266:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 267:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 268:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) + 269:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 270:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0), ((Pin * Pin) * Mode)); + 271:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 272:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 273:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 274:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return gpio mode for a dedicated pin on dedicated port. + 275:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + 276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 277:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll MODER MODEy LL_GPIO_GetPinMode + 278:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 279:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 280:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 281:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 282:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 283:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 284:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 285:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 286:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 287:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 288:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 289:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 290:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 291:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 292:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 293:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 294:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 295:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 296:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 297:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_INPUT + 298:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_OUTPUT + 299:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ALTERNATE + 300:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ANALOG + 301:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 302:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) + 303:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 304:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin)); + 305:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 306:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 307:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 308:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Configure gpio output type for several pins on dedicated port. + 309:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Output type as to be set when gpio pin is in output or + 310:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * alternate modes. Possible type are Push-pull or Open-drain. + 311:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + 312:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 313:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values: + 314:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 315:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 316:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 317:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 318:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 319:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 320:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + ARM GAS /tmp/ccjsaEK1.s page 20 + + + 321:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 322:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 323:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 325:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 326:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 327:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 328:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 329:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 330:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL + 331:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param OutputType This parameter can be one of the following values: + 332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + 333:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + 334:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 335:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 336:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t Outpu + 337:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 338:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); + 339:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 340:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 341:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 342:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return gpio output type for several pins on dedicated port. + 343:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Output type as to be set when gpio pin is in output or + 344:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * alternate modes. Possible type are Push-pull or Open-drain. + 345:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 346:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + 347:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 348:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 349:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 350:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 351:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 352:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 353:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 354:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 355:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 356:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 357:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 358:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 359:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 360:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 361:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 362:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 363:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 364:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 365:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL + 366:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 367:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + 368:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + 369:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 370:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) + 371:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 372:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); + 373:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 374:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 375:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 376:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Configure gpio speed for a dedicated pin on dedicated port. + 377:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note I/O speed can be Low, Medium, Fast or High speed. + ARM GAS /tmp/ccjsaEK1.s page 21 + + + 378:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 379:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Refer to datasheet for frequency specifications and the power + 380:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * supply and load conditions for each speed. + 381:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + 382:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 383:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 384:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 385:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 386:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 387:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 388:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 389:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 390:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 391:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 392:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 393:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 394:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 395:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 396:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 397:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 398:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 399:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 400:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Speed This parameter can be one of the following values: + 401:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_LOW + 402:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + 403:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + 404:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 405:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 406:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) + 407:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 408:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0), ((Pin * Pin) * Speed)); + 409:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 410:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 411:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 412:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return gpio speed for a dedicated pin on dedicated port. + 413:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note I/O speed can be Low, Medium, Fast or High speed. + 414:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 415:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Refer to datasheet for frequency specifications and the power + 416:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * supply and load conditions for each speed. + 417:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + 418:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 419:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 420:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 421:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 422:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 423:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 424:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 425:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 426:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 427:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 428:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 429:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 430:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 431:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 432:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 433:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 434:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + ARM GAS /tmp/ccjsaEK1.s page 22 + + + 435:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 436:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 437:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_LOW + 438:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + 439:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + 440:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 441:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) + 442:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 443:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0)) / (Pin * Pin)); + 444:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 445:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 446:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 447:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + 448:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 449:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + 450:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 451:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 452:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 453:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 454:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 455:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 456:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 457:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 458:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 459:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 460:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 461:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 462:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 463:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 464:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 465:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 466:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 467:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 468:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pull This parameter can be one of the following values: + 469:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_NO + 470:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_UP + 471:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_DOWN + 472:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 473:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 474:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) + 475:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 476:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0), ((Pin * Pin) * Pull)); + 212 .loc 3 476 0 + 213 0006 C668 ldr r6, [r0, #12] + 214 0008 1C00 movs r4, r3 + 215 000a 5C43 muls r4, r3 + 216 000c 6500 lsls r5, r4, #1 + 217 000e 2D19 adds r5, r5, r4 + 218 0010 ED43 mvns r5, r5 + 219 0012 2E40 ands r6, r5 + 220 0014 0F69 ldr r7, [r1, #16] + 221 0016 6743 muls r7, r4 + 222 0018 3E43 orrs r6, r7 + 223 001a C660 str r6, [r0, #12] + 224 .LVL17: + 225 .LBE47: + 226 .LBE46: + ARM GAS /tmp/ccjsaEK1.s page 23 + + + 190:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 191:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Get current io position */ + 192:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos); + 193:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 194:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** if (currentpin != 0x00u) + 195:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 196:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ + 197:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 198:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Check Speed mode parameters */ + 199:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); + 200:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 201:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Speed mode configuration */ + 202:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + 203:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 204:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Check Output mode parameters */ + 205:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + 206:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 207:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Output mode configuration*/ + 208:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); + 209:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 210:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 211:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Pull-up Pull down resistor configuration*/ + 212:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); + 213:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 214:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) + 227 .loc 1 214 0 + 228 001c 4E68 ldr r6, [r1, #4] + 229 001e 022E cmp r6, #2 + 230 0020 24D0 beq .L20 + 231 .LVL18: + 232 .L17: + 233 .LBB48: + 234 .LBB49: + 270:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 235 .loc 3 270 0 + 236 0022 0368 ldr r3, [r0] + 237 0024 1D40 ands r5, r3 + 238 0026 4B68 ldr r3, [r1, #4] + 239 0028 5C43 muls r4, r3 + 240 002a 2C43 orrs r4, r5 + 241 002c 0460 str r4, [r0] + 242 .LVL19: + 243 .L15: + 244 .LBE49: + 245 .LBE48: + 215:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 216:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Check Alternate parameter */ + 217:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); + 218:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 219:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Speed mode configuration */ + 220:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** if (currentpin < LL_GPIO_PIN_8) + 221:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 222:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); + 223:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 224:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** else + 225:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 226:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); + ARM GAS /tmp/ccjsaEK1.s page 24 + + + 227:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 228:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 229:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 230:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Pin Mode configuration */ + 231:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); + 232:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 233:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** pinpos++; + 246 .loc 1 233 0 + 247 002e 0132 adds r2, r2, #1 + 248 .LVL20: + 249 .L14: + 189:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 250 .loc 1 189 0 + 251 0030 0B68 ldr r3, [r1] + 252 0032 1C00 movs r4, r3 + 253 0034 D440 lsrs r4, r4, r2 + 254 0036 35D0 beq .L21 + 192:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 255 .loc 1 192 0 + 256 0038 0124 movs r4, #1 + 257 003a 9440 lsls r4, r4, r2 + 258 003c 2340 ands r3, r4 + 259 .LVL21: + 194:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 260 .loc 1 194 0 + 261 003e F6D0 beq .L15 + 196:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 262 .loc 1 196 0 + 263 0040 4C68 ldr r4, [r1, #4] + 264 0042 013C subs r4, r4, #1 + 265 0044 012C cmp r4, #1 + 266 0046 DED8 bhi .L16 + 267 .LVL22: + 268 .LBB50: + 269 .LBB51: + 408:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 270 .loc 3 408 0 + 271 0048 8468 ldr r4, [r0, #8] + 272 004a 1D00 movs r5, r3 + 273 004c 5D43 muls r5, r3 + 274 004e 6E00 lsls r6, r5, #1 + 275 0050 7619 adds r6, r6, r5 + 276 0052 B443 bics r4, r6 + 277 0054 8E68 ldr r6, [r1, #8] + 278 0056 7543 muls r5, r6 + 279 0058 2C43 orrs r4, r5 + 280 005a 8460 str r4, [r0, #8] + 281 .LVL23: + 282 .LBE51: + 283 .LBE50: + 208:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 284 .loc 1 208 0 + 285 005c 0D68 ldr r5, [r1] + 286 .LVL24: + 287 .LBB52: + 288 .LBB53: + 338:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + ARM GAS /tmp/ccjsaEK1.s page 25 + + + 289 .loc 3 338 0 + 290 005e 4468 ldr r4, [r0, #4] + 291 0060 AC43 bics r4, r5 + 292 0062 CE68 ldr r6, [r1, #12] + 293 0064 7543 muls r5, r6 + 294 .LVL25: + 295 0066 2C43 orrs r4, r5 + 296 0068 4460 str r4, [r0, #4] + 297 .LVL26: + 298 006a CCE7 b .L16 + 299 .LVL27: + 300 .L20: + 301 .LBE53: + 302 .LBE52: + 220:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 303 .loc 1 220 0 + 304 006c FF2B cmp r3, #255 + 305 006e 0BD8 bhi .L18 + 306 .LVL28: + 307 .LBB54: + 308 .LBB55: + 477:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 478:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 479:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 480:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + 481:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 482:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + 483:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 484:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 485:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 486:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 487:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 488:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 489:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 490:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 491:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 492:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 493:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 494:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 495:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 496:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 497:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 498:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 499:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 500:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 501:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 502:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_NO + 503:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_UP + 504:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_DOWN + 505:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 506:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) + 507:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 508:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0)) / (Pin * Pin)); + 509:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 510:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 511:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 512:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + ARM GAS /tmp/ccjsaEK1.s page 26 + + + 513:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Possible values are from AF0 to AF7 depending on target. + 514:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 515:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + 516:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 517:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 518:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 519:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 520:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 521:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 522:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 523:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 524:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 525:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 526:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Alternate This parameter can be one of the following values: + 527:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_0 + 528:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_1 + 529:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_2 + 530:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_3 + 531:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_4 + 532:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_5 + 533:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_6 + 534:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_7 + 535:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 536:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 537:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) + 538:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 539:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), + 309 .loc 3 539 0 + 310 0070 076A ldr r7, [r0, #32] + 311 0072 2600 movs r6, r4 + 312 0074 5E43 muls r6, r3 + 313 0076 7343 muls r3, r6 + 314 .LVL29: + 315 0078 1E01 lsls r6, r3, #4 + 316 007a F61A subs r6, r6, r3 + 317 007c B743 bics r7, r6 + 318 007e 4E69 ldr r6, [r1, #20] + 319 0080 7343 muls r3, r6 + 320 0082 3B43 orrs r3, r7 + 321 0084 0362 str r3, [r0, #32] + 322 .LVL30: + 323 0086 CCE7 b .L17 + 324 .LVL31: + 325 .L18: + 326 .LBE55: + 327 .LBE54: + 328 .LBB56: + 329 .LBB57: + 540:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** ((((Pin * Pin) * Pin) * Pin) * Alternate)); + 541:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 542:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 543:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 544:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + 545:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + 546:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 547:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 548:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + ARM GAS /tmp/ccjsaEK1.s page 27 + + + 549:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 550:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 551:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 552:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 553:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 554:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 555:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 556:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 557:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_0 + 558:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_1 + 559:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_2 + 560:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_3 + 561:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_4 + 562:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_5 + 563:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_6 + 564:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_7 + 565:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 566:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) + 567:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 568:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->AFR[0], + 569:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pi + 570:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** } + 571:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** + 572:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** /** + 573:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + 574:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Possible values are from AF0 to AF7 depending on target. + 575:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 576:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + 577:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param GPIOx GPIO Port + 578:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 579:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 580:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 581:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 582:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 583:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 584:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 585:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 586:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 587:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @param Alternate This parameter can be one of the following values: + 588:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_0 + 589:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_1 + 590:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_2 + 591:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_3 + 592:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_4 + 593:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_5 + 594:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_6 + 595:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_7 + 596:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** * @retval None + 597:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** */ + 598:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) + 599:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** { + 600:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h **** MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFR + 330 .loc 3 600 0 + 331 0088 476A ldr r7, [r0, #36] + 332 008a 1B0A lsrs r3, r3, #8 + 333 .LVL32: + 334 008c 1E00 movs r6, r3 + ARM GAS /tmp/ccjsaEK1.s page 28 + + + 335 008e 5E43 muls r6, r3 + 336 0090 5E43 muls r6, r3 + 337 0092 7343 muls r3, r6 + 338 0094 1E01 lsls r6, r3, #4 + 339 0096 F61A subs r6, r6, r3 + 340 0098 B743 bics r7, r6 + 341 009a 4E69 ldr r6, [r1, #20] + 342 009c 7343 muls r3, r6 + 343 009e 3B43 orrs r3, r7 + 344 00a0 4362 str r3, [r0, #36] + 345 .LVL33: + 346 00a2 BEE7 b .L17 + 347 .LVL34: + 348 .L21: + 349 .LBE57: + 350 .LBE56: + 234:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 235:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 236:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** return (SUCCESS); + 237:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 351 .loc 1 237 0 + 352 00a4 0020 movs r0, #0 + 353 .LVL35: + 354 @ sp needed + 355 00a6 F0BD pop {r4, r5, r6, r7, pc} + 356 .cfi_endproc + 357 .LFE79: + 359 .section .text.LL_GPIO_StructInit,"ax",%progbits + 360 .align 1 + 361 .global LL_GPIO_StructInit + 362 .syntax unified + 363 .code 16 + 364 .thumb_func + 365 .fpu softvfp + 367 LL_GPIO_StructInit: + 368 .LFB80: + 238:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 239:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /** + 240:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. + 241:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + 242:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * whose fields will be set to default values. + 243:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** * @retval None + 244:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** */ + 245:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** + 246:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) + 247:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** { + 369 .loc 1 247 0 + 370 .cfi_startproc + 371 @ args = 0, pretend = 0, frame = 0 + 372 @ frame_needed = 0, uses_anonymous_args = 0 + 373 @ link register save eliminated. + 374 .LVL36: + 248:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** /* Reset GPIO init structure parameters values */ + 249:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; + 375 .loc 1 249 0 + 376 0000 044B ldr r3, .L23 + 377 0002 0360 str r3, [r0] + ARM GAS /tmp/ccjsaEK1.s page 29 + + + 250:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; + 378 .loc 1 250 0 + 379 0004 0323 movs r3, #3 + 380 0006 4360 str r3, [r0, #4] + 251:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; + 381 .loc 1 251 0 + 382 0008 0023 movs r3, #0 + 383 000a 8360 str r3, [r0, #8] + 252:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 384 .loc 1 252 0 + 385 000c C360 str r3, [r0, #12] + 253:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; + 386 .loc 1 253 0 + 387 000e 0361 str r3, [r0, #16] + 254:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** GPIO_InitStruct->Alternate = LL_GPIO_AF_0; + 388 .loc 1 254 0 + 389 0010 4361 str r3, [r0, #20] + 255:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c **** } + 390 .loc 1 255 0 + 391 @ sp needed + 392 0012 7047 bx lr + 393 .L24: + 394 .align 2 + 395 .L23: + 396 0014 FFFF0000 .word 65535 + 397 .cfi_endproc + 398 .LFE80: + 400 .text + 401 .Letext0: + 402 .file 4 "/usr/include/newlib/machine/_default_types.h" + 403 .file 5 "/usr/include/newlib/sys/_stdint.h" + 404 .file 6 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h" + 405 .file 7 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h" + 406 .file 8 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h" + ARM GAS /tmp/ccjsaEK1.s page 30 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f0xx_ll_gpio.c + /tmp/ccjsaEK1.s:16 .text.LL_GPIO_DeInit:0000000000000000 $t + /tmp/ccjsaEK1.s:23 .text.LL_GPIO_DeInit:0000000000000000 LL_GPIO_DeInit + /tmp/ccjsaEK1.s:168 .text.LL_GPIO_DeInit:0000000000000080 $d + /tmp/ccjsaEK1.s:180 .text.LL_GPIO_Init:0000000000000000 $t + /tmp/ccjsaEK1.s:187 .text.LL_GPIO_Init:0000000000000000 LL_GPIO_Init + /tmp/ccjsaEK1.s:360 .text.LL_GPIO_StructInit:0000000000000000 $t + /tmp/ccjsaEK1.s:367 .text.LL_GPIO_StructInit:0000000000000000 LL_GPIO_StructInit + /tmp/ccjsaEK1.s:396 .text.LL_GPIO_StructInit:0000000000000014 $d + +NO UNDEFINED SYMBOLS diff --git a/bsl/makeLowLayer/build/stm32f0xx_ll_pwr.lst b/bsl/makeLowLayer/build/stm32f0xx_ll_pwr.lst new file mode 100644 index 0000000..ba5d193 --- /dev/null +++ b/bsl/makeLowLayer/build/stm32f0xx_ll_pwr.lst @@ -0,0 +1,812 @@ +ARM GAS /tmp/ccr4x8E3.s page 1 + + + 1 .cpu cortex-m0 + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32f0xx_ll_pwr.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_PWR_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_PWR_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_PWR_DeInit: + 24 .LFB76: + 25 .file 1 "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c" + 1:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * @file stm32f0xx_ll_pwr.c + 4:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * @brief PWR LL module driver. + 6:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** ****************************************************************************** + 7:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * @attention + 8:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * + 9:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** *

© Copyright (c) 2016 STMicroelectronics. + 10:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * All rights reserved.

+ 11:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * + 12:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * This software component is licensed by ST under BSD 3-Clause license, + 13:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * the "License"; You may not use this file except in compliance with the + 14:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * License. You may obtain a copy of the License at: + 15:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * opensource.org/licenses/BSD-3-Clause + 16:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * + 17:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** ****************************************************************************** + 18:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** */ + 19:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** + 20:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** #if defined(USE_FULL_LL_DRIVER) + 21:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** + 22:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** /* Includes ------------------------------------------------------------------*/ + 23:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** #include "stm32f0xx_ll_pwr.h" + 24:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** #include "stm32f0xx_ll_bus.h" + 25:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** + 26:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** /** @addtogroup STM32F0xx_LL_Driver + 27:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * @{ + 28:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** */ + 29:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** + 30:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** #if defined(PWR) + 31:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** + 32:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** /** @defgroup PWR_LL PWR + 33:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * @{ + ARM GAS /tmp/ccr4x8E3.s page 2 + + + 34:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** */ + 35:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** + 36:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** /* Private types -------------------------------------------------------------*/ + 37:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** /* Private variables ---------------------------------------------------------*/ + 38:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** /* Private constants ---------------------------------------------------------*/ + 39:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** /* Private macros ------------------------------------------------------------*/ + 40:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** /* Private function prototypes -----------------------------------------------*/ + 41:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** + 42:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** /* Exported functions --------------------------------------------------------*/ + 43:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** /** @addtogroup PWR_LL_Exported_Functions + 44:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * @{ + 45:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** */ + 46:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** + 47:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** /** @addtogroup PWR_LL_EF_Init + 48:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * @{ + 49:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** */ + 50:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** + 51:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** /** + 52:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * @brief De-initialize the PWR registers to their default reset values. + 53:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * @retval An ErrorStatus enumeration value: + 54:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * - SUCCESS: PWR registers are de-initialized + 55:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** * - ERROR: not applicable + 56:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** */ + 57:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** ErrorStatus LL_PWR_DeInit(void) + 58:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** { + 26 .loc 1 58 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 .LVL0: + 32 .LBB6: + 33 .LBB7: + 34 .file 2 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h" + 1:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @file stm32f0xx_ll_bus.h + 4:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 7:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** @verbatim + 8:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** [..] + 11:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 17:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** [..] + 18:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 22:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** ****************************************************************************** + ARM GAS /tmp/ccr4x8E3.s page 3 + + + 24:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @attention + 25:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 26:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** *

© Copyright (c) 2016 STMicroelectronics. + 27:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * All rights reserved.

+ 28:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 29:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * This software component is licensed by ST under BSD 3-Clause license, + 30:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * the "License"; You may not use this file except in compliance with the + 31:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * License. You may obtain a copy of the License at: + 32:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * opensource.org/licenses/BSD-3-Clause + 33:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 34:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** ****************************************************************************** + 35:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 36:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 37:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 38:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #ifndef __STM32F0xx_LL_BUS_H + 39:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define __STM32F0xx_LL_BUS_H + 40:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 41:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #ifdef __cplusplus + 42:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** extern "C" { + 43:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif + 44:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 45:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 46:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #include "stm32f0xx.h" + 47:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 48:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @addtogroup STM32F0xx_LL_Driver + 49:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 50:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 51:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 52:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(RCC) + 53:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 54:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 55:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 56:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 57:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 58:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 59:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 60:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 61:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 62:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 63:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 64:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 65:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 66:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 67:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 68:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 69:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 70:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 71:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 72:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 73:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 74:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 75:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN + 76:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(DMA2) + 77:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN + 78:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*DMA2*/ + 79:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN + 80:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN + ARM GAS /tmp/ccr4x8E3.s page 4 + + + 81:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN + 82:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN + 83:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN + 84:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN + 85:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(GPIOD) + 86:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN + 87:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*GPIOD*/ + 88:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(GPIOE) + 89:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN + 90:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*GPIOE*/ + 91:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN + 92:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(TSC) + 93:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN + 94:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*TSC*/ + 95:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 96:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @} + 97:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 98:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 99:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(TIM2) + 104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN + 105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*TIM2*/ + 106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN + 107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(TIM6) + 108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN + 109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*TIM6*/ + 110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(TIM7) + 111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN + 112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*TIM7*/ + 113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN + 114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN + 115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(SPI2) + 116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN + 117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*SPI2*/ + 118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART2) + 119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN + 120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /* USART2 */ + 121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART3) + 122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN + 123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /* USART3 */ + 124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART4) + 125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN + 126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /* USART4 */ + 127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART5) + 128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN + 129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /* USART5 */ + 130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN + 131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(I2C2) + 132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN + 133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*I2C2*/ + 134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USB) + 135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN + 136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /* USB */ + 137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(CAN) + ARM GAS /tmp/ccr4x8E3.s page 5 + + + 138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN + 139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*CAN*/ + 140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(CRS) + 141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN + 142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*CRS*/ + 143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN + 144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(DAC) + 145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN + 146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*DAC*/ + 147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(CEC) + 148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN + 149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*CEC*/ + 150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @} + 152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + 155:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 156:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 157:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU + 158:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN + 159:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN + 160:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART8) + 161:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN + 162:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*USART8*/ + 163:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART7) + 164:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN + 165:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*USART7*/ + 166:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(USART6) + 167:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN + 168:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*USART6*/ + 169:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN + 170:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN + 171:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN + 172:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #if defined(TIM15) + 173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN + 174:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #endif /*TIM15*/ + 175:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN + 176:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN + 177:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** #define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN + 178:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 179:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @} + 180:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 181:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 182:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 183:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @} + 184:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 185:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 186:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 187:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 189:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 190:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 191:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 192:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 193:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 194:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + ARM GAS /tmp/ccr4x8E3.s page 6 + + + 195:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 196:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 197:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 198:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n + 199:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n + 200:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n + 201:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n + 202:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + 203:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + 204:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + 205:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + 206:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n + 207:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + 208:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + 209:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_EnableClock + 210:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 211:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 212:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + 213:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 214:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + 215:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 216:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 217:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 218:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 219:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + 220:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + 221:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 222:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 223:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 224:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 225:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 226:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 227:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 228:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 229:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __IO uint32_t tmpreg; + 230:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs); + 231:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 232:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 233:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** (void)tmpreg; + 234:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 235:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 236:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 237:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 238:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + 239:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + 240:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n + 241:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n + 242:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 243:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + 244:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + 245:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + 246:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + 247:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + 248:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + 249:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock + 250:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 251:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + ARM GAS /tmp/ccr4x8E3.s page 7 + + + 252:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + 253:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 254:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + 255:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 256:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 257:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 258:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 259:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + 260:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + 261:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 262:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 263:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 264:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 265:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 266:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 267:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 268:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 269:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); + 270:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 271:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 272:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 273:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 274:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n + 275:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n + 276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n + 277:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n + 278:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + 279:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + 280:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + 281:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + 282:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n + 283:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + 284:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + 285:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBENR TSCEN LL_AHB1_GRP1_DisableClock + 286:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 287:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 288:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + 289:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + 290:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + 291:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 292:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 293:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 294:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 295:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + 296:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + 297:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 298:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 299:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 300:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 301:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 302:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 303:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 304:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 305:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs); + 306:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 307:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 308:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + ARM GAS /tmp/ccr4x8E3.s page 8 + + + 309:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 310:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + 311:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + 312:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + 313:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + 314:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + 315:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + 316:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset + 317:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 318:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 319:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 320:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 321:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 322:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + 323:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + 324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 325:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 326:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 327:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 328:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 329:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 330:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 331:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs); + 333:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 334:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 335:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 336:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 337:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + 338:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + 339:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + 340:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + 341:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + 342:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + 343:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset + 344:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 345:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 346:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 347:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 348:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 349:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + 350:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + 351:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 352:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + 353:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 354:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 355:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 356:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 357:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 358:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 359:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs); + 360:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 361:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 362:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 363:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @} + 364:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 365:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + ARM GAS /tmp/ccr4x8E3.s page 9 + + + 366:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1 + 367:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @{ + 368:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 369:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 370:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 371:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Enable APB1 peripherals clock (available in register 1). + 372:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + 373:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + 374:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + 375:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + 376:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n + 377:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + 378:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + 379:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + 380:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n + 381:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + 382:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + 383:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + 384:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + 385:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + 386:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n + 387:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + 388:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + 389:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + 390:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_EnableClock + 391:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 392:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + 393:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + 394:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 395:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 396:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + 397:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 398:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 399:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + 400:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + 401:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 402:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 403:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 404:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 405:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 406:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + 407:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 408:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 409:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 410:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + 411:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 412:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 413:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 414:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 415:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) + 416:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 417:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __IO uint32_t tmpreg; + 418:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 419:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 420:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + 421:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** (void)tmpreg; + 422:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + ARM GAS /tmp/ccr4x8E3.s page 10 + + + 423:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 424:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 425:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not (available in register 1). + 426:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + 427:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + 428:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + 429:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + 430:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n + 431:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + 432:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + 433:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + 434:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + 435:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + 436:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + 437:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + 438:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + 439:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + 440:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n + 441:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + 442:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + 443:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + 444:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock + 445:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 446:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + 447:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + 448:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 449:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 450:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + 451:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 452:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 453:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + 454:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + 455:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 456:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 457:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 458:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 459:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 460:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + 461:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 462:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 463:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 464:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + 465:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 466:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 467:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 468:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 469:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) + 470:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 471:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); + 472:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 473:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 474:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 475:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Disable APB1 peripherals clock (available in register 1). + 476:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + 477:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + 478:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + 479:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + ARM GAS /tmp/ccr4x8E3.s page 11 + + + 480:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n + 481:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + 482:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + 483:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + 484:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n + 485:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + 486:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + 487:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + 488:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + 489:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + 490:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n + 491:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + 492:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + 493:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + 494:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_DisableClock + 495:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 496:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + 497:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + 498:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 499:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 500:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + 501:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 502:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 503:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + 504:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + 505:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 506:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 507:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 508:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 509:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 510:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + 511:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 512:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 513:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 514:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + 515:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 516:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 517:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 518:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 519:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) + 520:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 521:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); + 522:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 523:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 524:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 525:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Force APB1 peripherals reset (available in register 1). + 526:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + 527:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + 528:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + 529:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + 530:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n + 531:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + 532:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + 533:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + 534:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n + 535:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + 536:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + ARM GAS /tmp/ccr4x8E3.s page 12 + + + 537:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + 538:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + 539:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + 540:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n + 541:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + 542:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + 543:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + 544:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ForceReset + 545:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 546:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 547:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + 548:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + 549:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 550:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 551:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + 552:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 553:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 554:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + 555:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + 556:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 557:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 558:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 559:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 560:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 561:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + 562:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 563:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 564:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 565:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + 566:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 567:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 568:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 569:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 570:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) + 571:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 572:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); + 35 .loc 2 572 0 + 36 0000 054B ldr r3, .L2 + 37 0002 1969 ldr r1, [r3, #16] + 38 0004 8022 movs r2, #128 + 39 0006 5205 lsls r2, r2, #21 + 40 0008 0A43 orrs r2, r1 + 41 000a 1A61 str r2, [r3, #16] + 42 .LVL1: + 43 .LBE7: + 44 .LBE6: + 45 .LBB8: + 46 .LBB9: + 573:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** } + 574:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** + 575:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** /** + 576:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @brief Release APB1 peripherals reset (available in register 1). + 577:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + 578:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + 579:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + 580:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + 581:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n + ARM GAS /tmp/ccr4x8E3.s page 13 + + + 582:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + 583:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + 584:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + 585:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + 586:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + 587:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + 588:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + 589:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + 590:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + 591:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n + 592:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + 593:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + 594:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + 595:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset + 596:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 597:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL + 598:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + 599:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + 600:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + 601:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + 602:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + 603:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + 604:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + 605:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + 606:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + 607:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + 608:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + 609:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + 610:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + 611:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + 612:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + 613:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + 614:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + 615:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + 616:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + 617:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * + 618:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * (*) value not defined in all devices. + 619:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** * @retval None + 620:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** */ + 621:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) + 622:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** { + 623:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); + 47 .loc 2 623 0 + 48 000c 1A69 ldr r2, [r3, #16] + 49 000e 0349 ldr r1, .L2+4 + 50 0010 0A40 ands r2, r1 + 51 0012 1A61 str r2, [r3, #16] + 52 .LVL2: + 53 .LBE9: + 54 .LBE8: + 59:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** /* Force reset of PWR clock */ + 60:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR); + 61:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** + 62:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** /* Release reset of PWR clock */ + 63:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR); + 64:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** + 65:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** return SUCCESS; + ARM GAS /tmp/ccr4x8E3.s page 14 + + + 66:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c **** } + 55 .loc 1 66 0 + 56 0014 0020 movs r0, #0 + 57 @ sp needed + 58 0016 7047 bx lr + 59 .L3: + 60 .align 2 + 61 .L2: + 62 0018 00100240 .word 1073876992 + 63 001c FFFFFFEF .word -268435457 + 64 .cfi_endproc + 65 .LFE76: + 67 .text + 68 .Letext0: + 69 .file 3 "/usr/include/newlib/machine/_default_types.h" + 70 .file 4 "/usr/include/newlib/sys/_stdint.h" + 71 .file 5 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h" + 72 .file 6 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h" + 73 .file 7 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h" + ARM GAS /tmp/ccr4x8E3.s page 15 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f0xx_ll_pwr.c + /tmp/ccr4x8E3.s:16 .text.LL_PWR_DeInit:0000000000000000 $t + /tmp/ccr4x8E3.s:23 .text.LL_PWR_DeInit:0000000000000000 LL_PWR_DeInit + /tmp/ccr4x8E3.s:62 .text.LL_PWR_DeInit:0000000000000018 $d + +NO UNDEFINED SYMBOLS diff --git a/bsl/makeLowLayer/build/stm32f0xx_ll_rcc.lst b/bsl/makeLowLayer/build/stm32f0xx_ll_rcc.lst new file mode 100644 index 0000000..3ed4fd9 --- /dev/null +++ b/bsl/makeLowLayer/build/stm32f0xx_ll_rcc.lst @@ -0,0 +1,3703 @@ +ARM GAS /tmp/ccTAt98O.s page 1 + + + 1 .cpu cortex-m0 + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32f0xx_ll_rcc.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.LL_RCC_DeInit,"ax",%progbits + 16 .align 1 + 17 .global LL_RCC_DeInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 LL_RCC_DeInit: + 24 .LFB151: + 25 .file 1 "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c" + 1:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @file stm32f0xx_ll_rcc.c + 4:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @brief RCC LL module driver. + 6:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** ****************************************************************************** + 7:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @attention + 8:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * + 9:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** *

© Copyright (c) 2016 STMicroelectronics. + 10:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * All rights reserved.

+ 11:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * + 12:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * This software component is licensed by ST under BSD 3-Clause license, + 13:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * the "License"; You may not use this file except in compliance with the + 14:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * License. You may obtain a copy of the License at: + 15:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * opensource.org/licenses/BSD-3-Clause + 16:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * + 17:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** ****************************************************************************** + 18:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 19:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 20:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(USE_FULL_LL_DRIVER) + 21:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 22:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Includes ------------------------------------------------------------------*/ + 23:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #include "stm32f0xx_ll_rcc.h" + 24:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #ifdef USE_FULL_ASSERT + 25:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #include "stm32_assert.h" + 26:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #else + 27:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #define assert_param(expr) ((void)0U) + 28:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* USE_FULL_ASSERT */ + 29:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** @addtogroup STM32F0xx_LL_Driver + 30:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @{ + 31:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 32:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 33:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(RCC) + ARM GAS /tmp/ccTAt98O.s page 2 + + + 34:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 35:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** @defgroup RCC_LL RCC + 36:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @{ + 37:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 38:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 39:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Private types -------------------------------------------------------------*/ + 40:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Private variables ---------------------------------------------------------*/ + 41:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 42:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Private constants ---------------------------------------------------------*/ + 43:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Private macros ------------------------------------------------------------*/ + 44:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** @addtogroup RCC_LL_Private_Macros + 45:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @{ + 46:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 47:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW) + 48:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + 49:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ + 50:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) + 51:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW) + 52:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + 53:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) + 54:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW) + 55:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + 56:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) + 57:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #else + 58:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE)) + 59:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */ + 60:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 61:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) + 62:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 63:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(USB) + 64:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) + 65:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* USB */ + 66:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 67:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(CEC) + 68:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE)) + 69:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* CEC */ + 70:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 71:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** + 72:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @} + 73:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 74:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 75:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Private function prototypes -----------------------------------------------*/ + 76:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** @defgroup RCC_LL_Private_Functions RCC Private functions + 77:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @{ + 78:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 79:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t RCC_GetSystemClockFreq(void); + 80:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); + 81:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); + 82:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_SYS(void); + 83:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** + 84:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @} + 85:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 86:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 87:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 88:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Exported functions --------------------------------------------------------*/ + 89:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** @addtogroup RCC_LL_Exported_Functions + 90:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @{ + ARM GAS /tmp/ccTAt98O.s page 3 + + + 91:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 92:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 93:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** @addtogroup RCC_LL_EF_Init + 94:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @{ + 95:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 96:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 97:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** + 98:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @brief Reset the RCC clock configuration to the default reset state. + 99:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @note The default reset state of the clock configuration is given below: + 100:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * - HSI ON and used as system clock source + 101:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * - HSE and PLL OFF + 102:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * - AHB and APB1 prescaler set to 1. + 103:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * - CSS, MCO OFF + 104:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * - All interrupts disabled + 105:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @note This function doesn't modify the configuration of the + 106:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * - Peripheral clocks + 107:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * - LSI, LSE and RTC clocks + 108:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @retval An ErrorStatus enumeration value: + 109:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * - SUCCESS: RCC registers are de-initialized + 110:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * - ERROR: not applicable + 111:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 112:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** ErrorStatus LL_RCC_DeInit(void) + 113:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 26 .loc 1 113 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 8 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 31 0000 82B0 sub sp, sp, #8 + 32 .LCFI0: + 33 .cfi_def_cfa_offset 8 + 34 .LBB58: + 35 .LBB59: + 36 .file 2 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h" + 1:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @file stm32f0xx_ll_rcc.h + 4:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Header file of RCC LL module. + 6:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** ****************************************************************************** + 7:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @attention + 8:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * + 9:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** *

© Copyright (c) 2016 STMicroelectronics. + 10:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * All rights reserved.

+ 11:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * + 12:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * This software component is licensed by ST under BSD 3-Clause license, + 13:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * the "License"; You may not use this file except in compliance with the + 14:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * License. You may obtain a copy of the License at: + 15:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * opensource.org/licenses/BSD-3-Clause + 16:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * + 17:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** ****************************************************************************** + 18:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 19:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 20:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 21:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #ifndef __STM32F0xx_LL_RCC_H + 22:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define __STM32F0xx_LL_RCC_H + 23:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + ARM GAS /tmp/ccTAt98O.s page 4 + + + 24:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #ifdef __cplusplus + 25:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** extern "C" { + 26:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif + 27:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 28:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Includes ------------------------------------------------------------------*/ + 29:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #include "stm32f0xx.h" + 30:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 31:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @addtogroup STM32F0xx_LL_Driver + 32:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 33:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 34:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 35:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC) + 36:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 37:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL RCC + 38:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 39:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 40:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 41:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Private types -------------------------------------------------------------*/ + 42:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Private variables ---------------------------------------------------------*/ + 43:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Private constants ---------------------------------------------------------*/ + 44:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Constants RCC Private Constants + 45:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 46:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 47:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Defines used for the bit position in the register and perform offsets*/ + 48:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HPRE (uint32_t)4U /*!< field position in register RCC_CFGR */ + 49:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_PPRE1 (uint32_t)8U /*!< field position in register RCC_CFGR */ + 50:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_PLLMUL (uint32_t)18U /*!< field position in register RCC_CFGR */ + 51:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HSICAL (uint32_t)8U /*!< field position in register RCC_CR */ + 52:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HSITRIM (uint32_t)3U /*!< field position in register RCC_CR */ + 53:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HSI14TRIM (uint32_t)3U /*!< field position in register RCC_CR2 */ + 54:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HSI14CAL (uint32_t)8U /*!< field position in register RCC_CR2 */ + 55:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 56:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HSI48CAL (uint32_t)24U /*!< field position in register RCC_CR2 */ + 57:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 58:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */ + 59:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */ + 60:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */ + 61:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 62:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 63:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 64:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 65:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 66:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Private macros ------------------------------------------------------------*/ + 67:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 68:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Macros RCC Private Macros + 69:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 70:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 71:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 72:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 73:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 74:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /*USE_FULL_LL_DRIVER*/ + 75:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Exported types ------------------------------------------------------------*/ + 76:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 77:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Types RCC Exported Types + 78:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 79:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 80:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + ARM GAS /tmp/ccTAt98O.s page 5 + + + 81:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + 82:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 83:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 84:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 85:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 86:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief RCC Clocks Frequency Structure + 87:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 88:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** typedef struct + 89:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 90:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + 91:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + 92:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + 93:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } LL_RCC_ClocksTypeDef; + 94:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 95:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 96:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 97:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 98:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 99:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */ + 103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Exported constants --------------------------------------------------------*/ + 105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + 106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + 110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Defines used to adapt values of different oscillators + 111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note These values could be modified in the user environment according to + 112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * HW set-up. + 113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if !defined (HSE_VALUE) + 116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ + 117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* HSE_VALUE */ + 118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if !defined (HSI_VALUE) + 120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ + 121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* HSI_VALUE */ + 122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if !defined (LSE_VALUE) + 124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ + 125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* LSE_VALUE */ + 126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if !defined (LSI_VALUE) + 128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ + 129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* LSI_VALUE */ + 130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if !defined (HSI48_VALUE) + 133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ + 134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* HSI48_VALUE */ + 135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + ARM GAS /tmp/ccTAt98O.s page 6 + + + 138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + 141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_WriteReg function + 142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ + 145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ + 146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ + 147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ + 148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ + 149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC /*!< HSI14 Ready Interrupt Clear */ + 150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI48RDYC RCC_CIR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ + 152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt + 154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 155:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 156:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 157:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 158:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + 159:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_ReadReg function + 160:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 161:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 162:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ + 163:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ + 164:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ + 165:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ + 166:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ + 167:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF /*!< HSI14 Ready Interrupt flag */ + 168:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 169:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI48RDYF RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ + 170:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 171:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt f + 172:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ + 173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ + 174:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ + 175:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ + 176:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset f + 177:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag * + 178:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ + 179:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CSR_V18PWRRSTF) + 180:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V doma + 181:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CSR_V18PWRRSTF */ + 182:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 183:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 184:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 185:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 186:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_IT IT Defines + 187:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + 188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 189:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 190:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ + 191:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ + 192:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ + 193:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ + 194:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ + ARM GAS /tmp/ccTAt98O.s page 7 + + + 195:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE /*!< HSI14 Ready Interrupt Enable * + 196:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 197:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI48RDYIE RCC_CIR_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable * + 198:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 199:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 200:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 201:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 202:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 203:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + 204:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 205:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 206:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving cap + 207:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capa + 208:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving cap + 209:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capabili + 210:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 211:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 212:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 213:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 214:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + 215:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 216:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 217:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ + 218:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ + 219:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ + 220:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_SW_HSI48) + 221:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 /*!< HSI48 selection as system clock + 222:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_SW_HSI48 */ + 223:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 224:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 225:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 226:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 227:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + 228:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 229:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 230:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ + 231:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ + 232:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ + 233:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_SWS_HSI48) + 234:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 /*!< HSI48 used as system clock */ + 235:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_SWS_HSI48 */ + 236:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 237:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 238:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 239:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 240:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + 241:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 242:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 243:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ + 244:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ + 245:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ + 246:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ + 247:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ + 248:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ + 249:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ + 250:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ + 251:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ + ARM GAS /tmp/ccTAt98O.s page 8 + + + 252:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 253:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 254:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 255:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 256:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + 257:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 258:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 259:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */ + 260:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */ + 261:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */ + 262:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */ + 263:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */ + 264:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 265:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 266:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 267:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 268:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + 269:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 270:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 271:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, n + 272:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCOSEL_HSI14 /*!< HSI14 oscillator clock + 273:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MC + 274:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO s + 275:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO s + 276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO s + 277:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO s + 278:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_MCOSEL_HSI48) + 279:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /*!< HSI48 selection as MCO + 280:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_MCOSEL_HSI48 */ + 281:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2 + 282:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_PLLNODIV) + 283:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL + 284:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_PLLNODIV */ + 285:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 286:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 287:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 288:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 289:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + 290:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 291:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 292:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */ + 293:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_MCOPRE) + 294:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ + 295:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ + 296:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ + 297:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ + 298:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */ + 299:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */ + 300:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */ + 301:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_MCOPRE */ + 302:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 303:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 304:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 305:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 306:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 307:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + 308:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + ARM GAS /tmp/ccTAt98O.s page 9 + + + 309:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 310:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the periphera + 311:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as ex + 312:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 313:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 314:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 315:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */ + 316:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 317:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection + 318:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 319:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 320:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USA + 321:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USA + 322:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USA + 323:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USA + 324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR3_USART2SW) + 325:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USA + 326:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USA + 327:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USA + 328:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USA + 329:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR3_USART2SW */ + 330:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR3_USART3SW) + 331:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USA + 332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USA + 333:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USA + 334:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USA + 335:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR3_USART3SW */ + 336:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 337:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 338:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 339:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 340:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection + 341:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 342:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 343:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI /*!< HSI oscillator clock used a + 344:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK /*!< System clock selected as I2 + 345:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 346:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 347:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 348:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 349:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(CEC) + 350:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + 351:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 352:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 353:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 + 354:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HD + 355:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 356:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 357:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 358:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 359:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* CEC */ + 360:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 361:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USB) + 362:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + 363:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 364:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 365:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR3_USBSW_HSI48) + ARM GAS /tmp/ccTAt98O.s page 10 + + + 366:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 oscillator clock used + 367:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #else + 368:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_NONE ((uint32_t)0x00000000) /*!< USB Clock disabled */ + 369:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /*RCC_CFGR3_USBSW_HSI48*/ + 370:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL selected as USB clock s + 371:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 372:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 373:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 374:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 375:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* USB */ + 376:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 377:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source + 378:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 379:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 380:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection + 381:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR3_USART2SW) + 382:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection + 383:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR3_USART2SW */ + 384:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR3_USART3SW) + 385:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection + 386:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR3_USART3SW */ + 387:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 388:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 389:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 390:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 391:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source + 392:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 393:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 394:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */ + 395:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 396:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 397:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 398:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 399:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(CEC) + 400:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + 401:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 402:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 403:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selecti + 404:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 405:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 406:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 407:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* CEC */ + 408:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 409:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USB) + 410:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + 411:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 412:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 413:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE RCC_CFGR3_USBSW /*!< USB Clock source selection + 414:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 415:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 416:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 417:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* USB */ + 418:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 419:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + 420:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 421:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 422:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC + ARM GAS /tmp/ccTAt98O.s page 11 + + + 423:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used a + 424:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used a + 425:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divide + 426:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 427:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 428:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 429:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 430:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor + 431:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 432:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 433:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */ + 434:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */ + 435:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */ + 436:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */ + 437:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */ + 438:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */ + 439:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */ + 440:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */ + 441:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */ + 442:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */ + 443:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */ + 444:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */ + 445:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */ + 446:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */ + 447:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */ + 448:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 449:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 450:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 451:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 452:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE + 453:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 454:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 455:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No cl + 456:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/P + 457:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + 458:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/P + 459:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_SW_HSI48) + 460:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< HSI48 + 461:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_SW_HSI48 */ + 462:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #else + 463:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI c + 464:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) + 465:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) + 466:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) + 467:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) + 468:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) + 469:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) + 470:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) + 471:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) + 472:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) + 473:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) + 474:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) + 475:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) + 476:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) + 477:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) + 478:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) + 479:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) + ARM GAS /tmp/ccTAt98O.s page 12 + + + 480:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + 481:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 482:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 483:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 484:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 485:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor + 486:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 487:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 488:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divi + 489:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided + 490:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided + 491:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided + 492:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided + 493:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided + 494:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided + 495:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided + 496:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided + 497:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided + 498:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided + 499:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided + 500:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided + 501:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided + 502:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided + 503:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided + 504:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 505:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 506:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 507:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 508:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 509:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 510:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 511:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 512:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Exported macro ------------------------------------------------------------*/ + 513:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + 514:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 515:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 516:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 517:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + 518:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 519:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 520:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 521:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 522:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Write a value in RCC register + 523:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __REG__ Register to be written + 524:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __VALUE__ Value to be written in the register + 525:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 526:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 527:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + 528:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 529:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 530:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Read a value in RCC register + 531:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __REG__ Register to be read + 532:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Register value + 533:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 534:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) + 535:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 536:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + ARM GAS /tmp/ccTAt98O.s page 13 + + + 537:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 538:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 539:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + 540:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 541:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 542:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 543:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + 544:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 545:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency + 546:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator() + 547:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * , @ref LL_RCC_PLL_GetPrediv()); + 548:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/HSI48) + 549:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __PLLMUL__ This parameter can be one of the following values: + 550:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_2 + 551:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3 + 552:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4 + 553:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_5 + 554:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6 + 555:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_7 + 556:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8 + 557:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_9 + 558:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_10 + 559:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_11 + 560:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12 + 561:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_13 + 562:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_14 + 563:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_15 + 564:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16 + 565:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __PLLPREDIV__ This parameter can be one of the following values: + 566:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_1 + 567:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_2 + 568:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_3 + 569:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_4 + 570:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_5 + 571:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_6 + 572:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_7 + 573:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_8 + 574:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_9 + 575:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_10 + 576:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_11 + 577:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_12 + 578:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_13 + 579:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_14 + 580:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_15 + 581:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_16 + 582:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) + 583:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 584:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \ + 585:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RC + 586:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 587:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #else + 588:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 589:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency + 590:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref + 591:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2) + 592:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __PLLMUL__ This parameter can be one of the following values: + 593:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_2 + ARM GAS /tmp/ccTAt98O.s page 14 + + + 594:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3 + 595:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4 + 596:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_5 + 597:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6 + 598:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_7 + 599:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8 + 600:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_9 + 601:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_10 + 602:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_11 + 603:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12 + 604:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_13 + 605:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_14 + 606:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_15 + 607:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16 + 608:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) + 609:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 610:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ + 611:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) + 612:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + 613:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 614:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Helper macro to calculate the HCLK frequency + 615:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler + 616:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) + 617:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) + 618:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __AHBPRESCALER__ This parameter can be one of the following values: + 619:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 + 620:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 + 621:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 + 622:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 + 623:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 + 624:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 + 625:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 + 626:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 + 627:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 + 628:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval HCLK clock frequency (in Hz) + 629:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 630:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTabl + 631:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 632:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 633:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + 634:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler + 635:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) + 636:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __HCLKFREQ__ HCLK frequency + 637:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __APB1PRESCALER__ This parameter can be one of the following values: + 638:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 + 639:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 + 640:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 + 641:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 + 642:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 + 643:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval PCLK1 clock frequency (in Hz) + 644:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 645:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[ + 646:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 647:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 648:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 649:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 650:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + ARM GAS /tmp/ccTAt98O.s page 15 + + + 651:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 652:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 653:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 654:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 655:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Exported functions --------------------------------------------------------*/ + 656:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + 657:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 658:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 659:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 660:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSE HSE + 661:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 662:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 663:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 664:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 665:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable the Clock Security System. + 666:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + 667:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 668:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 669:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) + 670:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 671:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_CSSON); + 672:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 673:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 674:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 675:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable the Clock Security System. + 676:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note Cannot be disabled in HSE is ready (only by hardware) + 677:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS + 678:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 679:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 680:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_DisableCSS(void) + 681:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 682:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_CSSON); + 683:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 684:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 685:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 686:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable HSE external oscillator (HSE Bypass) + 687:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + 688:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 689:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 690:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) + 691:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 692:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEBYP); + 693:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 694:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 695:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 696:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable HSE external oscillator (HSE Bypass) + 697:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + 698:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 699:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 700:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) + 701:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 702:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + 703:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 704:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 705:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 706:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable HSE crystal oscillator (HSE ON) + 707:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Enable + ARM GAS /tmp/ccTAt98O.s page 16 + + + 708:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 709:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 710:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Enable(void) + 711:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 712:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEON); + 713:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 714:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 715:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 716:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable HSE crystal oscillator (HSE ON) + 717:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Disable + 718:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 719:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 720:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Disable(void) + 721:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 722:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEON); + 723:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 724:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 725:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 726:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if HSE oscillator Ready + 727:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + 728:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 729:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 730:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) + 731:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 732:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); + 733:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 734:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 735:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 736:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 737:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 738:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 739:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI HSI + 740:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 741:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 742:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 743:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 744:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable HSI oscillator + 745:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Enable + 746:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 747:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 748:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Enable(void) + 749:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 750:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSION); + 37 .loc 2 750 0 + 38 0002 2A4A ldr r2, .L5 + 39 0004 1368 ldr r3, [r2] + 40 0006 0121 movs r1, #1 + 41 0008 0B43 orrs r3, r1 + 42 000a 1360 str r3, [r2] + 43 .L2: + 44 .LBE59: + 45 .LBE58: + 46 .LBB60: + 47 .LBB61: + 751:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 752:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 753:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + ARM GAS /tmp/ccTAt98O.s page 17 + + + 754:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable HSI oscillator + 755:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Disable + 756:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 757:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 758:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Disable(void) + 759:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 760:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSION); + 761:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 762:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 763:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 764:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if HSI clock is ready + 765:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + 766:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 767:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 768:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) + 769:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 770:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); + 48 .loc 2 770 0 discriminator 1 + 49 000c 274B ldr r3, .L5 + 50 000e 1B68 ldr r3, [r3] + 51 .LBE61: + 52 .LBE60: + 114:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** __IO uint32_t vl_mask; + 115:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 116:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Set HSION bit */ + 117:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_HSI_Enable(); + 118:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 119:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Wait for HSI READY bit */ + 120:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** while(LL_RCC_HSI_IsReady() != 1U) + 53 .loc 1 120 0 discriminator 1 + 54 0010 9B07 lsls r3, r3, #30 + 55 0012 FBD5 bpl .L2 + 56 .LVL0: + 57 .LBB62: + 58 .LBB63: + 771:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 772:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 773:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 774:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get HSI Calibration value + 775:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note When HSITRIM is written, HSICAL is updated with the sum of + 776:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * HSITRIM and the factory trim value + 777:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration + 778:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + 779:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 780:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) + 781:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 782:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); + 783:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 784:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 785:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 786:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set HSI Calibration trimming + 787:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note user-programmable trimming value that is added to the HSICAL + 788:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note Default value is 16, which, when added to the HSICAL value, + 789:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * should trim the HSI to 16 MHz +/- 1 % + 790:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming + 791:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Value between Min_Data = 0x00 and Max_Data = 0x1F + 792:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + ARM GAS /tmp/ccTAt98O.s page 18 + + + 793:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 794:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) + 795:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 796:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); + 59 .loc 2 796 0 + 60 0014 254A ldr r2, .L5 + 61 0016 1368 ldr r3, [r2] + 62 0018 F821 movs r1, #248 + 63 001a 8B43 bics r3, r1 + 64 001c 7839 subs r1, r1, #120 + 65 001e 0B43 orrs r3, r1 + 66 0020 1360 str r3, [r2] + 67 .LVL1: + 68 .LBE63: + 69 .LBE62: + 121:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** {} + 122:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 123:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Set HSITRIM bits to the reset value*/ + 124:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_HSI_SetCalibTrimming(0x10U); + 125:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 126:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Reset SW, HPRE, PPRE and MCOSEL bits */ + 127:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** vl_mask = 0xFFFFFFFFU; + 70 .loc 1 127 0 + 71 0022 0123 movs r3, #1 + 72 0024 5B42 rsbs r3, r3, #0 + 73 0026 0193 str r3, [sp, #4] + 128:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCOSEL)); + 74 .loc 1 128 0 + 75 0028 019B ldr r3, [sp, #4] + 76 002a 2149 ldr r1, .L5+4 + 77 002c 0B40 ands r3, r1 + 78 002e 0193 str r3, [sp, #4] + 129:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 130:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Write new value in CFGR register */ + 131:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_WriteReg(CFGR, vl_mask); + 79 .loc 1 131 0 + 80 0030 019B ldr r3, [sp, #4] + 81 0032 5360 str r3, [r2, #4] + 82 .L3: + 83 .LBB64: + 84 .LBB65: + 797:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 798:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 799:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 800:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get HSI Calibration trimming + 801:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming + 802:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + 803:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 804:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) + 805:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 806:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + 807:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 808:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 809:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 810:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 811:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 812:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + ARM GAS /tmp/ccTAt98O.s page 19 + + + 813:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 814:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI48 HSI48 + 815:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 816:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 817:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 818:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 819:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable HSI48 + 820:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Enable + 821:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 822:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 823:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI48_Enable(void) + 824:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 825:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR2, RCC_CR2_HSI48ON); + 826:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 827:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 828:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 829:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable HSI48 + 830:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Disable + 831:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 832:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 833:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI48_Disable(void) + 834:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 835:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON); + 836:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 837:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 838:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 839:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if HSI48 oscillator Ready + 840:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI48RDY LL_RCC_HSI48_IsReady + 841:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 842:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 843:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) + 844:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 845:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CR2, RCC_CR2_HSI48RDY) == (RCC_CR2_HSI48RDY)); + 846:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 847:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 848:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 849:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get HSI48 Calibration value + 850:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI48CAL LL_RCC_HSI48_GetCalibration + 851:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + 852:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 853:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) + 854:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 855:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48CAL) >> RCC_POSITION_HSI48CAL); + 856:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 857:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 858:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 859:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 860:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 861:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 862:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 863:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 864:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI14 HSI14 + 865:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 866:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 867:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 868:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 869:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable HSI14 + ARM GAS /tmp/ccTAt98O.s page 20 + + + 870:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Enable + 871:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 872:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 873:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI14_Enable(void) + 874:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 875:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR2, RCC_CR2_HSI14ON); + 876:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 877:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 878:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 879:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable HSI14 + 880:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Disable + 881:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 882:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 883:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI14_Disable(void) + 884:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 885:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON); + 886:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 887:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 888:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 889:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if HSI14 oscillator Ready + 890:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14RDY LL_RCC_HSI14_IsReady + 891:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 892:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 893:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI14_IsReady(void) + 894:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 895:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CR2, RCC_CR2_HSI14RDY) == (RCC_CR2_HSI14RDY)); + 896:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 897:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 898:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 899:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief ADC interface can turn on the HSI14 oscillator + 900:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_EnableADCControl + 901:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 902:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 903:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI14_EnableADCControl(void) + 904:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 905:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS); + 906:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 907:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 908:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 909:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief ADC interface can not turn on the HSI14 oscillator + 910:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_DisableADCControl + 911:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 912:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 913:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI14_DisableADCControl(void) + 914:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 915:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS); + 916:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 917:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 918:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 919:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set HSI14 Calibration trimming + 920:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note user-programmable trimming value that is added to the HSI14CAL + 921:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note Default value is 16, which, when added to the HSI14CAL value, + 922:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * should trim the HSI14 to 14 MHz +/- 1 % + 923:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_SetCalibTrimming + 924:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Value between Min_Data = 0x00 and Max_Data = 0xFF + 925:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 926:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + ARM GAS /tmp/ccTAt98O.s page 21 + + + 927:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI14_SetCalibTrimming(uint32_t Value) + 928:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 929:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, Value << RCC_POSITION_HSI14TRIM); + 930:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 931:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 932:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 933:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get HSI14 Calibration value + 934:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note When HSI14TRIM is written, HSI14CAL is updated with the sum of + 935:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * HSI14TRIM and the factory trim value + 936:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_GetCalibTrimming + 937:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + 938:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 939:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibTrimming(void) + 940:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 941:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14TRIM) >> RCC_POSITION_HSI14TRIM); + 942:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 943:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 944:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 945:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get HSI14 Calibration trimming + 946:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14CAL LL_RCC_HSI14_GetCalibration + 947:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + 948:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 949:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibration(void) + 950:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 951:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14CAL) >> RCC_POSITION_HSI14CAL); + 952:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 953:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 954:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 955:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 956:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 957:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 958:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSE LSE + 959:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 960:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 961:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 962:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 963:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable Low Speed External (LSE) crystal. + 964:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + 965:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 966:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 967:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Enable(void) + 968:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 969:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); + 970:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 971:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 972:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 973:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable Low Speed External (LSE) crystal. + 974:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + 975:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 976:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 977:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Disable(void) + 978:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 979:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); + 980:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 981:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 982:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 983:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable external clock source (LSE bypass). + ARM GAS /tmp/ccTAt98O.s page 22 + + + 984:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + 985:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 986:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 987:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) + 988:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 989:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + 990:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 991:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 992:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 993:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable external clock source (LSE bypass). + 994:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + 995:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 996:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 997:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) + 998:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 999:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +1000:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1001:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1002:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1003:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set LSE oscillator drive capability +1004:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note The oscillator is in Xtal mode when it is not in bypass mode. +1005:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability +1006:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param LSEDrive This parameter can be one of the following values: +1007:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_LOW +1008:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW +1009:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH +1010:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_HIGH +1011:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1012:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1013:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +1014:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1015:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +1016:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1017:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1018:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1019:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get LSE oscillator drive capability +1020:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability +1021:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1022:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_LOW +1023:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW +1024:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH +1025:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_HIGH +1026:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1027:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +1028:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1029:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +1030:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1031:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1032:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1033:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if LSE oscillator Ready +1034:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady +1035:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1036:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1037:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +1038:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1039:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); +1040:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + ARM GAS /tmp/ccTAt98O.s page 23 + + +1041:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1042:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1043:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} +1044:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1045:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1046:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSI LSI +1047:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ +1048:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1049:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1050:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1051:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable LSI Oscillator +1052:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Enable +1053:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1054:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1055:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Enable(void) +1056:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1057:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_LSION); +1058:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1059:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1060:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1061:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable LSI Oscillator +1062:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Disable +1063:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1064:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1065:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Disable(void) +1066:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1067:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +1068:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1069:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1070:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1071:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if LSI is Ready +1072:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady +1073:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1074:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1075:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +1076:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1077:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +1078:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1079:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1080:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1081:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} +1082:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1083:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1084:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_System System +1085:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ +1086:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1087:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1088:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1089:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure the system clock source +1090:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR SW LL_RCC_SetSysClkSource +1091:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +1092:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI +1093:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE +1094:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL +1095:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI48 (*) +1096:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1097:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices + ARM GAS /tmp/ccTAt98O.s page 24 + + +1098:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1099:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +1101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +1103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get the system clock source +1107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR SWS LL_RCC_GetSysClkSource +1108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI +1110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE +1111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL +1112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*) +1113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices +1115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +1117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); + 85 .loc 2 1118 0 discriminator 1 + 86 0034 1D4B ldr r3, .L5 + 87 0036 5B68 ldr r3, [r3, #4] + 88 0038 0C22 movs r2, #12 + 89 .LBE65: + 90 .LBE64: + 132:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 133:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Wait till system clock source is ready */ + 134:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) + 91 .loc 1 134 0 discriminator 1 + 92 003a 1A42 tst r2, r3 + 93 003c FAD1 bne .L3 + 135:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** {} + 136:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 137:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Read CR register */ + 138:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** vl_mask = LL_RCC_ReadReg(CR); + 94 .loc 1 138 0 + 95 003e 1B4A ldr r2, .L5 + 96 0040 1368 ldr r3, [r2] + 97 0042 0193 str r3, [sp, #4] + 139:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 140:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Reset HSEON, CSSON, PLLON bits */ + 141:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON)); + 98 .loc 1 141 0 + 99 0044 019B ldr r3, [sp, #4] + 100 0046 1B49 ldr r1, .L5+8 + 101 0048 0B40 ands r3, r1 + 102 004a 0193 str r3, [sp, #4] + 142:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 143:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Write new value in CR register */ + 144:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_WriteReg(CR, vl_mask); + 103 .loc 1 144 0 + 104 004c 019B ldr r3, [sp, #4] + 105 004e 1360 str r3, [r2] + 106 .L4: + 107 .LBB66: + ARM GAS /tmp/ccTAt98O.s page 25 + + + 108 .LBB67: +1119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set AHB prescaler +1123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler +1124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +1125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 +1126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +1127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +1128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +1129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +1130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +1131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +1132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +1133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +1134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +1137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +1139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set APB1 prescaler +1143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler +1144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +1145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +1146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +1147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +1148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +1149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +1150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +1153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); +1155:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1156:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1157:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1158:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get AHB prescaler +1159:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler +1160:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1161:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 +1162:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +1163:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +1164:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +1165:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +1166:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +1167:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +1168:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +1169:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +1170:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1171:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +1172:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +1174:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + ARM GAS /tmp/ccTAt98O.s page 26 + + +1175:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1176:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1177:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get APB1 prescaler +1178:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler +1179:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1180:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +1181:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +1182:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +1183:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +1184:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +1185:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1186:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +1187:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); +1189:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1190:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1191:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1192:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} +1193:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1194:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1195:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_MCO MCO +1196:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ +1197:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1198:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1199:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1200:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure MCOx +1201:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n +1202:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR MCOPRE LL_RCC_ConfigMCO\n +1203:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR PLLNODIV LL_RCC_ConfigMCO +1204:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param MCOxSource This parameter can be one of the following values: +1205:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK +1206:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSI14 +1207:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK +1208:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSI +1209:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSE +1210:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_LSI +1211:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_LSE +1212:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) +1213:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*) +1214:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 +1215:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1216:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices +1217:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param MCOxPrescaler This parameter can be one of the following values: +1218:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_1 +1219:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_2 (*) +1220:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_4 (*) +1221:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_8 (*) +1222:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_16 (*) +1223:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_32 (*) +1224:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_64 (*) +1225:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_128 (*) +1226:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1227:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices +1228:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1229:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1230:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +1231:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + ARM GAS /tmp/ccTAt98O.s page 27 + + +1232:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_MCOPRE) +1233:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_PLLNODIV) +1234:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPre +1235:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #else +1236:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); +1237:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_PLLNODIV */ +1238:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #else +1239:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); +1240:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_MCOPRE */ +1241:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1242:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1243:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1244:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} +1245:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1246:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1247:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source +1248:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ +1249:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1250:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1251:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1252:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure USARTx clock source +1253:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n +1254:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n +1255:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR3 USART3SW LL_RCC_SetUSARTClockSource +1256:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param USARTxSource This parameter can be one of the following values: +1257:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 +1258:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK +1259:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE +1260:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI +1261:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) +1262:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) +1263:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) +1264:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) +1265:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) +1266:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) +1267:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) +1268:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) +1269:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1270:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices. +1271:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1272:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1273:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +1274:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1275:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSou +1276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1277:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1278:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1279:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure I2Cx clock source +1280:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource +1281:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param I2CxSource This parameter can be one of the following values: +1282:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI +1283:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK +1284:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1285:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1286:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +1287:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1288:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, I2CxSource); + ARM GAS /tmp/ccTAt98O.s page 28 + + +1289:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1290:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1291:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(CEC) +1292:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1293:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure CEC clock source +1294:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource +1295:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param CECxSource This parameter can be one of the following values: +1296:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 +1297:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE +1298:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1299:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1300:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource) +1301:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1302:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource); +1303:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1304:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* CEC */ +1305:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1306:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USB) +1307:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1308:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure USB clock source +1309:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR3 USBSW LL_RCC_SetUSBClockSource +1310:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param USBxSource This parameter can be one of the following values: +1311:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) +1312:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) +1313:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL +1314:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1315:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices. +1316:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1317:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1318:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +1319:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1320:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, USBxSource); +1321:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1322:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* USB */ +1323:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1325:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get USARTx clock source +1326:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n +1327:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n +1328:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR3 USART3SW LL_RCC_GetUSARTClockSource +1329:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param USARTx This parameter can be one of the following values: +1330:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE +1331:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE (*) +1332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE (*) +1333:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1334:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices. +1335:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1336:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 +1337:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK +1338:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE +1339:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI +1340:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) +1341:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) +1342:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) +1343:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) +1344:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) +1345:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + ARM GAS /tmp/ccTAt98O.s page 29 + + +1346:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) +1347:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) +1348:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1349:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices. +1350:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1351:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +1352:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1353:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U)); +1354:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1355:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1356:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1357:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get I2Cx clock source +1358:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource +1359:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param I2Cx This parameter can be one of the following values: +1360:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE +1361:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1362:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI +1363:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK +1364:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1365:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +1366:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1367:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx)); +1368:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1369:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1370:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(CEC) +1371:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1372:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get CEC clock source +1373:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource +1374:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param CECx This parameter can be one of the following values: +1375:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE +1376:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1377:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 +1378:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE +1379:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1380:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) +1381:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1382:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR3, CECx)); +1383:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1384:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* CEC */ +1385:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1386:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USB) +1387:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1388:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get USBx clock source +1389:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR3 USBSW LL_RCC_GetUSBClockSource +1390:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param USBx This parameter can be one of the following values: +1391:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE +1392:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1393:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) +1394:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) +1395:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL +1396:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1397:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices. +1398:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1399:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +1400:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1401:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR3, USBx)); +1402:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + ARM GAS /tmp/ccTAt98O.s page 30 + + +1403:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* USB */ +1404:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1405:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1406:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} +1407:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1408:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1409:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_RTC RTC +1410:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ +1411:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1412:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1413:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1414:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set RTC Clock Source +1415:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note Once the RTC clock source has been selected, it cannot be changed any more unless +1416:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * the Backup domain is reset. The BDRST bit can be used to reset them. +1417:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource +1418:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +1419:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE +1420:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE +1421:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI +1422:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 +1423:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1424:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1425:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +1426:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1427:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +1428:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1429:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1430:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1431:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get RTC Clock Source +1432:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource +1433:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1434:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE +1435:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE +1436:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI +1437:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 +1438:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1439:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +1440:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1441:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +1442:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1443:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1444:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1445:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable RTC +1446:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR RTCEN LL_RCC_EnableRTC +1447:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1448:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1449:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_EnableRTC(void) +1450:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1451:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +1452:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1453:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1454:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1455:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable RTC +1456:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR RTCEN LL_RCC_DisableRTC +1457:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1458:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1459:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_DisableRTC(void) + ARM GAS /tmp/ccTAt98O.s page 31 + + +1460:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1461:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +1462:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1463:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1464:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1465:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if RTC has been enabled or not +1466:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC +1467:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1468:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1469:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +1470:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1471:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); +1472:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1473:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1474:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1475:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Force the Backup domain reset +1476:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset +1477:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1478:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1479:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +1480:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1481:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +1482:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1483:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1484:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1485:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Release the Backup domain reset +1486:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset +1487:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1488:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1489:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +1490:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1491:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +1492:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1493:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1494:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1495:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} +1496:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1497:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1498:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLL PLL +1499:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ +1500:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1501:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1502:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1503:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable PLL +1504:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR PLLON LL_RCC_PLL_Enable +1505:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1506:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1507:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Enable(void) +1508:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1509:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_PLLON); +1510:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1511:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1512:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1513:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable PLL +1514:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note Cannot be disabled if the PLL clock is used as the system clock +1515:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR PLLON LL_RCC_PLL_Disable +1516:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + ARM GAS /tmp/ccTAt98O.s page 32 + + +1517:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1518:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Disable(void) +1519:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1520:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +1521:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1522:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1523:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1524:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if PLL Ready +1525:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady +1526:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1527:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1528:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +1529:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1530:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); + 109 .loc 2 1530 0 discriminator 1 + 110 0050 164B ldr r3, .L5 + 111 0052 1B68 ldr r3, [r3] + 112 .LBE67: + 113 .LBE66: + 145:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 146:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Wait for PLL READY bit to be reset */ + 147:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** while(LL_RCC_PLL_IsReady() != 0U) + 114 .loc 1 147 0 discriminator 1 + 115 0054 9B01 lsls r3, r3, #6 + 116 0056 FBD4 bmi .L4 + 117 .LBB68: + 118 .LBB69: + 702:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 119 .loc 2 702 0 + 120 0058 144B ldr r3, .L5 + 121 005a 1A68 ldr r2, [r3] + 122 005c 1649 ldr r1, .L5+12 + 123 005e 0A40 ands r2, r1 + 124 0060 1A60 str r2, [r3] + 125 .LBE69: + 126 .LBE68: + 148:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** {} + 149:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 150:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Reset HSEBYP bit */ + 151:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_HSE_DisableBypass(); + 152:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 153:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Reset CFGR register */ + 154:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_WriteReg(CFGR, 0x00000000U); + 127 .loc 1 154 0 + 128 0062 0022 movs r2, #0 + 129 0064 5A60 str r2, [r3, #4] + 155:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 156:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(RCC_HSI48_SUPPORT) + 157:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Reset CR2 register */ + 158:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_WriteReg(CR2, 0x00000000U); + 130 .loc 1 158 0 + 131 0066 5A63 str r2, [r3, #52] + 132 .LBB70: + 133 .LBB71: + 835:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 134 .loc 2 835 0 + 135 0068 596B ldr r1, [r3, #52] + ARM GAS /tmp/ccTAt98O.s page 33 + + + 136 006a 1448 ldr r0, .L5+16 + 137 006c 0140 ands r1, r0 + 138 006e 5963 str r1, [r3, #52] + 139 .LVL2: + 140 .LBE71: + 141 .LBE70: + 142 .LBB72: + 143 .LBB73: + 929:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 144 .loc 2 929 0 + 145 0070 596B ldr r1, [r3, #52] + 146 0072 F820 movs r0, #248 + 147 0074 8143 bics r1, r0 + 148 0076 7838 subs r0, r0, #120 + 149 0078 0143 orrs r1, r0 + 150 007a 5963 str r1, [r3, #52] + 151 .LVL3: + 152 .LBE73: + 153 .LBE72: + 154 .LBB74: + 155 .LBB75: + 885:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 156 .loc 2 885 0 + 157 007c 596B ldr r1, [r3, #52] + 158 007e 7F38 subs r0, r0, #127 + 159 0080 8143 bics r1, r0 + 160 0082 5963 str r1, [r3, #52] + 161 .LBE75: + 162 .LBE74: + 163 .LBB76: + 164 .LBB77: + 905:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 165 .loc 2 905 0 + 166 0084 596B ldr r1, [r3, #52] + 167 0086 0330 adds r0, r0, #3 + 168 0088 8143 bics r1, r0 + 169 008a 5963 str r1, [r3, #52] + 170 .LBE77: + 171 .LBE76: + 159:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 160:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Disable HSI48 */ + 161:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_HSI48_Disable(); + 162:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 163:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /*RCC_HSI48_SUPPORT*/ + 164:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Set HSI14TRIM/HSI14ON/HSI14DIS bits to the reset value*/ + 165:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_HSI14_SetCalibTrimming(0x10U); + 166:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_HSI14_Disable(); + 167:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_HSI14_EnableADCControl(); + 168:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 169:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Reset CFGR2 register */ + 170:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_WriteReg(CFGR2, 0x00000000U); + 172 .loc 1 170 0 + 173 008c DA62 str r2, [r3, #44] + 171:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 172:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Reset CFGR3 register */ + 173:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_WriteReg(CFGR3, 0x00000000U); + 174 .loc 1 173 0 + ARM GAS /tmp/ccTAt98O.s page 34 + + + 175 008e 1A63 str r2, [r3, #48] + 174:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 175:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Clear pending flags */ + 176:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(RCC_HSI48_SUPPORT) + 177:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC |\ + 176 .loc 1 177 0 + 177 0090 FF21 movs r1, #255 + 178 0092 0904 lsls r1, r1, #16 + 179 0094 0191 str r1, [sp, #4] + 178:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_HSI48RDYC | LL_RCC_CIR_CSSC); + 179:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #else + 180:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC |\ + 181:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_CSSC); + 182:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* RCC_HSI48_SUPPORT */ + 183:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 184:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Write new value in CIR register */ + 185:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_WriteReg(CIR, vl_mask); + 180 .loc 1 185 0 + 181 0096 0199 ldr r1, [sp, #4] + 182 0098 9960 str r1, [r3, #8] + 186:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 187:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Disable all interrupts */ + 188:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_WriteReg(CIR, 0x00000000U); + 183 .loc 1 188 0 + 184 009a 9A60 str r2, [r3, #8] + 185 .LBB78: + 186 .LBB79: +1531:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1532:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1533:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) +1534:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1535:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure PLL used for SYSCLK Domain +1536:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n +1537:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n +1538:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS +1539:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +1540:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +1541:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +1542:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) +1543:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1544:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices +1545:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param PLLMul This parameter can be one of the following values: +1546:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_2 +1547:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3 +1548:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4 +1549:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_5 +1550:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6 +1551:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_7 +1552:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8 +1553:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_9 +1554:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_10 +1555:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_11 +1556:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12 +1557:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_13 +1558:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_14 +1559:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_15 +1560:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16 + ARM GAS /tmp/ccTAt98O.s page 35 + + +1561:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param PLLDiv This parameter can be one of the following values: +1562:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_1 +1563:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_2 +1564:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_3 +1565:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_4 +1566:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_5 +1567:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_6 +1568:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_7 +1569:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_8 +1570:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_9 +1571:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_10 +1572:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_11 +1573:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_12 +1574:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_13 +1575:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_14 +1576:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_15 +1577:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_16 +1578:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1579:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1580:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) +1581:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1582:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul); +1583:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); +1584:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1585:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1586:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #else +1587:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1588:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1589:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure PLL used for SYSCLK Domain +1590:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n +1591:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n +1592:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS +1593:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +1594:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 +1595:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 +1596:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 +1597:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 +1598:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 +1599:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 +1600:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 +1601:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 +1602:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 +1603:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 +1604:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 +1605:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 +1606:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 +1607:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 +1608:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 +1609:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 +1610:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 +1611:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param PLLMul This parameter can be one of the following values: +1612:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_2 +1613:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3 +1614:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4 +1615:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_5 +1616:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6 +1617:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_7 + ARM GAS /tmp/ccTAt98O.s page 36 + + +1618:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8 +1619:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_9 +1620:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_10 +1621:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_11 +1622:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12 +1623:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_13 +1624:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_14 +1625:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_15 +1626:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16 +1627:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1628:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1629:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) +1630:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1631:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul); +1632:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV)); +1633:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1634:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ +1635:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1636:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1637:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure PLL clock source +1638:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource +1639:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param PLLSource This parameter can be one of the following values: +1640:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_NONE +1641:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI (*) +1642:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*) +1643:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +1644:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) +1645:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1646:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices +1647:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1648:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1649:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +1650:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1651:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource); +1652:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1653:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1654:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1655:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get the oscillator used as PLL clock source. +1656:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource +1657:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1658:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_NONE +1659:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI (*) +1660:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*) +1661:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +1662:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) +1663:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1664:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices +1665:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1666:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +1667:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1668:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); +1669:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1670:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1671:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1672:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get PLL multiplication Factor +1673:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator +1674:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: + ARM GAS /tmp/ccTAt98O.s page 37 + + +1675:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_2 +1676:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3 +1677:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4 +1678:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_5 +1679:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6 +1680:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_7 +1681:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8 +1682:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_9 +1683:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_10 +1684:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_11 +1685:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12 +1686:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_13 +1687:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_14 +1688:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_15 +1689:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16 +1690:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1691:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) +1692:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1693:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); +1694:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1695:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1696:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1697:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get PREDIV division factor for the main PLL +1698:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note They can be written only when the PLL is disabled +1699:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv +1700:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1701:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_1 +1702:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_2 +1703:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_3 +1704:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_4 +1705:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_5 +1706:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_6 +1707:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_7 +1708:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_8 +1709:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_9 +1710:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_10 +1711:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_11 +1712:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_12 +1713:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_13 +1714:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_14 +1715:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_15 +1716:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_16 +1717:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1718:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) +1719:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1720:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)); +1721:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1722:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1723:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1724:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} +1725:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1726:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1727:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management +1728:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ +1729:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1730:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1731:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + ARM GAS /tmp/ccTAt98O.s page 38 + + +1732:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Clear LSI ready interrupt flag +1733:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY +1734:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1735:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1736:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +1737:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1738:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); +1739:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1740:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1741:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1742:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Clear LSE ready interrupt flag +1743:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY +1744:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1745:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1746:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +1747:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1748:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); +1749:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1750:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1751:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1752:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Clear HSI ready interrupt flag +1753:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY +1754:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1755:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1756:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +1757:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1758:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); +1759:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1760:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1761:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1762:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Clear HSE ready interrupt flag +1763:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY +1764:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1765:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1766:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +1767:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1768:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); +1769:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1770:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1771:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1772:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Clear PLL ready interrupt flag +1773:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY +1774:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1775:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1776:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +1777:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1778:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); +1779:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1780:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1781:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1782:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Clear HSI14 ready interrupt flag +1783:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CIR HSI14RDYC LL_RCC_ClearFlag_HSI14RDY +1784:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1785:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1786:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ClearFlag_HSI14RDY(void) +1787:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1788:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYC); + ARM GAS /tmp/ccTAt98O.s page 39 + + +1789:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1790:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1791:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) +1792:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1793:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Clear HSI48 ready interrupt flag +1794:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CIR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY +1795:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1796:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1797:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) +1798:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1799:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYC); +1800:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1801:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ +1802:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1803:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1804:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Clear Clock security system interrupt flag +1805:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS +1806:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1807:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1808:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +1809:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1810:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CIR, RCC_CIR_CSSC); +1811:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1812:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1813:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1814:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if LSI ready interrupt occurred or not +1815:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY +1816:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1817:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1818:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +1819:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1820:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); +1821:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1822:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1823:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1824:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if LSE ready interrupt occurred or not +1825:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY +1826:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1827:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1828:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +1829:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1830:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); +1831:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1832:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1833:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1834:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if HSI ready interrupt occurred or not +1835:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY +1836:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1837:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1838:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +1839:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1840:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); +1841:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1842:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1843:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1844:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if HSE ready interrupt occurred or not +1845:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY + ARM GAS /tmp/ccTAt98O.s page 40 + + +1846:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1847:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1848:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +1849:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1850:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); +1851:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1852:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1853:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1854:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if PLL ready interrupt occurred or not +1855:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY +1856:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1857:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1858:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +1859:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1860:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); +1861:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1862:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1863:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1864:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if HSI14 ready interrupt occurred or not +1865:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CIR HSI14RDYF LL_RCC_IsActiveFlag_HSI14RDY +1866:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1867:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1868:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI14RDY(void) +1869:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1870:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYF) == (RCC_CIR_HSI14RDYF)); +1871:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1872:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1873:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) +1874:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1875:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if HSI48 ready interrupt occurred or not +1876:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY +1877:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1878:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1879:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) +1880:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1881:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYF) == (RCC_CIR_HSI48RDYF)); +1882:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1883:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ +1884:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1885:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1886:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if Clock security system interrupt occurred or not +1887:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS +1888:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1889:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1890:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +1891:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1892:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); +1893:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1894:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1895:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1896:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if RCC flag Independent Watchdog reset is set or not. +1897:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST +1898:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1899:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1900:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +1901:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1902:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); + ARM GAS /tmp/ccTAt98O.s page 41 + + +1903:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1904:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1905:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1906:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if RCC flag Low Power reset is set or not. +1907:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST +1908:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1909:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1910:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +1911:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1912:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); +1913:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1914:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1915:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1916:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if RCC flag is set or not. +1917:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST +1918:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1919:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1920:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) +1921:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1922:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); +1923:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1924:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1925:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1926:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if RCC flag Pin reset is set or not. +1927:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST +1928:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1929:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1930:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +1931:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1932:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); +1933:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1934:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1935:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1936:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if RCC flag POR/PDR reset is set or not. +1937:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST +1938:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1939:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1940:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +1941:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1942:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); +1943:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1944:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1945:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1946:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if RCC flag Software reset is set or not. +1947:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST +1948:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1949:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1950:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +1951:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1952:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); +1953:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1954:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1955:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1956:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if RCC flag Window Watchdog reset is set or not. +1957:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST +1958:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1959:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + ARM GAS /tmp/ccTAt98O.s page 42 + + +1960:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +1961:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1962:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); +1963:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1964:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1965:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CSR_V18PWRRSTF) +1966:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1967:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if RCC Reset flag of the 1.8 V domain is set or not. +1968:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST +1969:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1970:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1971:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void) +1972:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1973:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF)); +1974:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1975:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CSR_V18PWRRSTF */ +1976:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1977:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1978:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set RMVF bit to clear the reset flags. +1979:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR RMVF LL_RCC_ClearResetFlags +1980:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1981:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1982:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ClearResetFlags(void) +1983:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1984:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_RMVF); + 187 .loc 2 1984 0 + 188 009c 596A ldr r1, [r3, #36] + 189 009e 8022 movs r2, #128 + 190 00a0 5204 lsls r2, r2, #17 + 191 00a2 0A43 orrs r2, r1 + 192 00a4 5A62 str r2, [r3, #36] + 193 .LBE79: + 194 .LBE78: + 189:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 190:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Clear reset flags */ + 191:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** LL_RCC_ClearResetFlags(); + 192:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 193:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** return SUCCESS; + 194:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 195 .loc 1 194 0 + 196 00a6 0020 movs r0, #0 + 197 00a8 02B0 add sp, sp, #8 + 198 @ sp needed + 199 00aa 7047 bx lr + 200 .L6: + 201 .align 2 + 202 .L5: + 203 00ac 00100240 .word 1073876992 + 204 00b0 0CF8FFF0 .word -251660276 + 205 00b4 FFFFF6FE .word -17367041 + 206 00b8 FFFFFBFF .word -262145 + 207 00bc FFFFFEFF .word -65537 + 208 .cfi_endproc + 209 .LFE151: + 211 .section .text.LL_RCC_GetCECClockFreq,"ax",%progbits + 212 .align 1 + 213 .global LL_RCC_GetCECClockFreq + ARM GAS /tmp/ccTAt98O.s page 43 + + + 214 .syntax unified + 215 .code 16 + 216 .thumb_func + 217 .fpu softvfp + 219 LL_RCC_GetCECClockFreq: + 220 .LFB156: + 195:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 196:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** + 197:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @} + 198:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 199:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 200:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** @addtogroup RCC_LL_EF_Get_Freq + 201:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks + 202:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * and different peripheral clocks available on the device. + 203:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + 204:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + 205:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @note If SYSCLK source is PLL, function returns values based on + 206:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + 207:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @note (**) HSI_VALUE is a defined constant but the real value may vary + 208:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * depending on the variations in voltage and temperature. + 209:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @note (***) HSE_VALUE is a defined constant, user has to ensure that + 210:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * HSE_VALUE is same as the real frequency of the crystal used. + 211:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * Otherwise, this function may have wrong result. + 212:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @note The result of this function could be incorrect when using fractional + 213:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * value for HSE crystal. + 214:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @note This function can be used by the user application to compute the + 215:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * baud-rate for the communication peripherals or configure other parameters. + 216:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @{ + 217:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 218:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 219:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** + 220:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks + 221:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @note Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function + 222:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * must be called to update structure fields. Otherwise, any + 223:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * configuration based on this function will be incorrect. + 224:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks + 225:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @retval None + 226:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 227:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) + 228:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 229:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Get SYSCLK frequency */ + 230:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); + 231:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 232:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* HCLK clock frequency */ + 233:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); + 234:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 235:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* PCLK1 clock frequency */ + 236:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); + 237:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 238:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 239:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** + 240:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @brief Return USARTx clock frequency + 241:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @param USARTxSource This parameter can be one of the following values: + 242:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @arg @ref LL_RCC_USART1_CLKSOURCE + 243:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @arg @ref LL_RCC_USART2_CLKSOURCE (*) + 244:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @arg @ref LL_RCC_USART3_CLKSOURCE (*) + 245:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * + ARM GAS /tmp/ccTAt98O.s page 44 + + + 246:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * (*) value not defined in all devices. + 247:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @retval USART clock frequency (in Hz) + 248:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not read + 249:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 250:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) + 251:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 252:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 253:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 254:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Check parameter */ + 255:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); + 256:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(RCC_CFGR3_USART1SW) + 257:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** if (USARTxSource == LL_RCC_USART1_CLKSOURCE) + 258:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 259:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* USART1CLK clock frequency */ + 260:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + 261:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 262:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ + 263:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** usart_frequency = RCC_GetSystemClockFreq(); + 264:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 265:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 266:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ + 267:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 268:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 269:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** usart_frequency = HSI_VALUE; + 270:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 271:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 272:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 273:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ + 274:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 275:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 276:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** usart_frequency = LSE_VALUE; + 277:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 278:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 279:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 280:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */ + 281:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** default: + 282:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 283:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 284:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 285:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 286:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* RCC_CFGR3_USART1SW */ + 287:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 288:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(RCC_CFGR3_USART2SW) + 289:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** if (USARTxSource == LL_RCC_USART2_CLKSOURCE) + 290:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 291:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* USART2CLK clock frequency */ + 292:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + 293:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 294:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ + 295:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** usart_frequency = RCC_GetSystemClockFreq(); + 296:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 297:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 298:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ + 299:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 300:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 301:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** usart_frequency = HSI_VALUE; + 302:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + ARM GAS /tmp/ccTAt98O.s page 45 + + + 303:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 304:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 305:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ + 306:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 307:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 308:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** usart_frequency = LSE_VALUE; + 309:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 310:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 311:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 312:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ + 313:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** default: + 314:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 315:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 316:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 317:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 318:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* RCC_CFGR3_USART2SW */ + 319:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 320:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(RCC_CFGR3_USART3SW) + 321:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** if (USARTxSource == LL_RCC_USART3_CLKSOURCE) + 322:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 323:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* USART3CLK clock frequency */ + 324:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + 325:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 326:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */ + 327:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** usart_frequency = RCC_GetSystemClockFreq(); + 328:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 329:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 330:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ + 331:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 332:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 333:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** usart_frequency = HSI_VALUE; + 334:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 335:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 336:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 337:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */ + 338:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 339:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 340:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** usart_frequency = LSE_VALUE; + 341:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 342:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 343:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 344:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */ + 345:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** default: + 346:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 347:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 348:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 349:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 350:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 351:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* RCC_CFGR3_USART3SW */ + 352:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** return usart_frequency; + 353:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 354:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 355:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** + 356:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @brief Return I2Cx clock frequency + 357:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @param I2CxSource This parameter can be one of the following values: + 358:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @arg @ref LL_RCC_I2C1_CLKSOURCE + 359:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @retval I2C clock frequency (in Hz) + ARM GAS /tmp/ccTAt98O.s page 46 + + + 360:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready + 361:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 362:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) + 363:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 364:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 365:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 366:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Check parameter */ + 367:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); + 368:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 369:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* I2C1 CLK clock frequency */ + 370:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) + 371:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 372:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** switch (LL_RCC_GetI2CClockSource(I2CxSource)) + 373:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 374:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ + 375:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** i2c_frequency = RCC_GetSystemClockFreq(); + 376:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 377:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 378:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ + 379:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** default: + 380:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 381:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 382:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** i2c_frequency = HSI_VALUE; + 383:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 384:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 385:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 386:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 387:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 388:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** return i2c_frequency; + 389:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 390:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 391:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(USB) + 392:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** + 393:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @brief Return USBx clock frequency + 394:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @param USBxSource This parameter can be one of the following values: + 395:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @arg @ref LL_RCC_USB_CLKSOURCE + 396:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @retval USB clock frequency (in Hz) + 397:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not re + 398:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + 399:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 400:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) + 401:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 402:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 403:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 404:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Check parameter */ + 405:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); + 406:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 407:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* USBCLK clock frequency */ + 408:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** switch (LL_RCC_GetUSBClockSource(USBxSource)) + 409:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 410:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ + 411:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** if (LL_RCC_PLL_IsReady()) + 412:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 413:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** usb_frequency = RCC_PLL_GetFreqDomain_SYS(); + 414:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 415:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 416:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + ARM GAS /tmp/ccTAt98O.s page 47 + + + 417:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(RCC_CFGR3_USBSW_HSI48) + 418:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */ + 419:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** default: + 420:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** if (LL_RCC_HSI48_IsReady()) + 421:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 422:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** usb_frequency = HSI48_VALUE; + 423:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 424:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 425:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #else + 426:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */ + 427:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** default: + 428:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + 429:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 430:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* RCC_CFGR3_USBSW_HSI48 */ + 431:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 432:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 433:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** return usb_frequency; + 434:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 435:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* USB */ + 436:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 437:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(CEC) + 438:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** + 439:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @brief Return CECx clock frequency + 440:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @param CECxSource This parameter can be one of the following values: + 441:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @arg @ref LL_RCC_CEC_CLKSOURCE + 442:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @retval CEC clock frequency (in Hz) + 443:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not rea + 444:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 445:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) + 446:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 221 .loc 1 446 0 + 222 .cfi_startproc + 223 @ args = 0, pretend = 0, frame = 0 + 224 @ frame_needed = 0, uses_anonymous_args = 0 + 225 @ link register save eliminated. + 226 .LVL4: + 227 .LBB80: + 228 .LBB81: +1382:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 229 .loc 2 1382 0 + 230 0000 0A4B ldr r3, .L14 + 231 0002 1B6B ldr r3, [r3, #48] + 232 .LVL5: + 233 .LBE81: + 234 .LBE80: + 447:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 448:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 449:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Check parameter */ + 450:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource)); + 451:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 452:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* CECCLK clock frequency */ + 453:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** switch (LL_RCC_GetCECClockSource(CECxSource)) + 235 .loc 1 453 0 + 236 0004 0342 tst r3, r0 + 237 0006 05D1 bne .L13 + 238 .LBB82: + 239 .LBB83: + ARM GAS /tmp/ccTAt98O.s page 48 + + + 770:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 240 .loc 2 770 0 + 241 0008 084B ldr r3, .L14 + 242 000a 1B68 ldr r3, [r3] + 243 .LBE83: + 244 .LBE82: + 454:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 455:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */ + 456:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 245 .loc 1 456 0 + 246 000c 9B07 lsls r3, r3, #30 + 247 000e 07D4 bmi .L11 + 447:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 248 .loc 1 447 0 + 249 0010 0020 movs r0, #0 + 250 .LVL6: + 251 .L7: + 457:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 458:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** cec_frequency = HSI_VALUE / 244U; + 459:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 460:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 461:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 462:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */ + 463:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** default: + 464:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 465:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 466:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** cec_frequency = LSE_VALUE; + 467:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 468:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 469:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 470:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 471:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** return cec_frequency; + 472:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 252 .loc 1 472 0 + 253 @ sp needed + 254 0012 7047 bx lr + 255 .LVL7: + 256 .L13: + 257 .LBB84: + 258 .LBB85: +1039:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 259 .loc 2 1039 0 + 260 0014 054B ldr r3, .L14 + 261 0016 1B6A ldr r3, [r3, #32] + 262 .LBE85: + 263 .LBE84: + 464:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 264 .loc 1 464 0 + 265 0018 9B07 lsls r3, r3, #30 + 266 001a 03D4 bmi .L12 + 447:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 267 .loc 1 447 0 + 268 001c 0020 movs r0, #0 + 269 .LVL8: + 270 001e F8E7 b .L7 + 271 .LVL9: + 272 .L11: + ARM GAS /tmp/ccTAt98O.s page 49 + + + 458:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 273 .loc 1 458 0 + 274 0020 0348 ldr r0, .L14+4 + 275 .LVL10: + 276 0022 F6E7 b .L7 + 277 .LVL11: + 278 .L12: + 466:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 279 .loc 1 466 0 + 280 0024 8020 movs r0, #128 + 281 .LVL12: + 282 0026 0002 lsls r0, r0, #8 + 283 .LVL13: + 471:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 284 .loc 1 471 0 + 285 0028 F3E7 b .L7 + 286 .L15: + 287 002a C046 .align 2 + 288 .L14: + 289 002c 00100240 .word 1073876992 + 290 0030 12800000 .word 32786 + 291 .cfi_endproc + 292 .LFE156: + 294 .section .text.RCC_GetHCLKClockFreq,"ax",%progbits + 295 .align 1 + 296 .global RCC_GetHCLKClockFreq + 297 .syntax unified + 298 .code 16 + 299 .thumb_func + 300 .fpu softvfp + 302 RCC_GetHCLKClockFreq: + 303 .LFB158: + 473:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* CEC */ + 474:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 475:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** + 476:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @} + 477:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 478:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 479:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** + 480:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @} + 481:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 482:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 483:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** @addtogroup RCC_LL_Private_Functions + 484:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @{ + 485:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 486:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 487:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** + 488:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @brief Return SYSTEM clock frequency + 489:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @retval SYSTEM clock frequency (in Hz) + 490:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 491:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t RCC_GetSystemClockFreq(void) + 492:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 493:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t frequency = 0U; + 494:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 495:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Get SYSCLK source -------------------------------------------------------*/ + 496:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** switch (LL_RCC_GetSysClkSource()) + 497:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + ARM GAS /tmp/ccTAt98O.s page 50 + + + 498:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + 499:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** frequency = HSI_VALUE; + 500:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 501:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 502:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + 503:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** frequency = HSE_VALUE; + 504:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 505:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 506:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ + 507:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** frequency = RCC_PLL_GetFreqDomain_SYS(); + 508:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 509:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 510:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(RCC_HSI48_SUPPORT) + 511:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_SYS_CLKSOURCE_STATUS_HSI48:/* HSI48 used as system clock source */ + 512:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** frequency = HSI48_VALUE; + 513:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 514:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* RCC_HSI48_SUPPORT */ + 515:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 516:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** default: + 517:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** frequency = HSI_VALUE; + 518:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 519:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 520:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 521:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** return frequency; + 522:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 523:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 524:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** + 525:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @brief Return HCLK clock frequency + 526:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @param SYSCLK_Frequency SYSCLK clock frequency + 527:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @retval HCLK clock frequency (in Hz) + 528:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 529:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) + 530:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 304 .loc 1 530 0 + 305 .cfi_startproc + 306 @ args = 0, pretend = 0, frame = 0 + 307 @ frame_needed = 0, uses_anonymous_args = 0 + 308 @ link register save eliminated. + 309 .LVL14: + 310 .LBB86: + 311 .LBB87: +1173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 312 .loc 2 1173 0 + 313 0000 044B ldr r3, .L17 + 314 0002 5A68 ldr r2, [r3, #4] + 315 .LBE87: + 316 .LBE86: + 531:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* HCLK clock frequency */ + 532:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); + 317 .loc 1 532 0 + 318 0004 1209 lsrs r2, r2, #4 + 319 0006 0F23 movs r3, #15 + 320 0008 1340 ands r3, r2 + 321 000a 034A ldr r2, .L17+4 + 322 000c D35C ldrb r3, [r2, r3] + 323 000e D840 lsrs r0, r0, r3 + 324 .LVL15: + ARM GAS /tmp/ccTAt98O.s page 51 + + + 533:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 325 .loc 1 533 0 + 326 @ sp needed + 327 0010 7047 bx lr + 328 .L18: + 329 0012 C046 .align 2 + 330 .L17: + 331 0014 00100240 .word 1073876992 + 332 0018 00000000 .word AHBPrescTable + 333 .cfi_endproc + 334 .LFE158: + 336 .section .text.RCC_GetPCLK1ClockFreq,"ax",%progbits + 337 .align 1 + 338 .global RCC_GetPCLK1ClockFreq + 339 .syntax unified + 340 .code 16 + 341 .thumb_func + 342 .fpu softvfp + 344 RCC_GetPCLK1ClockFreq: + 345 .LFB159: + 534:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 535:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** + 536:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @brief Return PCLK1 clock frequency + 537:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @param HCLK_Frequency HCLK clock frequency + 538:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @retval PCLK1 clock frequency (in Hz) + 539:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 540:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) + 541:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 346 .loc 1 541 0 + 347 .cfi_startproc + 348 @ args = 0, pretend = 0, frame = 0 + 349 @ frame_needed = 0, uses_anonymous_args = 0 + 350 @ link register save eliminated. + 351 .LVL16: + 352 .LBB88: + 353 .LBB89: +1188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 354 .loc 2 1188 0 + 355 0000 044B ldr r3, .L20 + 356 0002 5A68 ldr r2, [r3, #4] + 357 .LBE89: + 358 .LBE88: + 542:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* PCLK1 clock frequency */ + 543:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); + 359 .loc 1 543 0 + 360 0004 120A lsrs r2, r2, #8 + 361 0006 0723 movs r3, #7 + 362 0008 1340 ands r3, r2 + 363 000a 034A ldr r2, .L20+4 + 364 000c D35C ldrb r3, [r2, r3] + 365 000e D840 lsrs r0, r0, r3 + 366 .LVL17: + 544:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 367 .loc 1 544 0 + 368 @ sp needed + 369 0010 7047 bx lr + 370 .L21: + ARM GAS /tmp/ccTAt98O.s page 52 + + + 371 0012 C046 .align 2 + 372 .L20: + 373 0014 00100240 .word 1073876992 + 374 0018 00000000 .word APBPrescTable + 375 .cfi_endproc + 376 .LFE159: + 378 .global __aeabi_uidiv + 379 .section .text.RCC_PLL_GetFreqDomain_SYS,"ax",%progbits + 380 .align 1 + 381 .global RCC_PLL_GetFreqDomain_SYS + 382 .syntax unified + 383 .code 16 + 384 .thumb_func + 385 .fpu softvfp + 387 RCC_PLL_GetFreqDomain_SYS: + 388 .LFB160: + 545:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /** + 546:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @brief Return PLL clock frequency used for system domain + 547:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** * @retval PLL clock frequency (in Hz) + 548:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** */ + 549:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_SYS(void) + 550:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 389 .loc 1 550 0 + 390 .cfi_startproc + 391 @ args = 0, pretend = 0, frame = 0 + 392 @ frame_needed = 0, uses_anonymous_args = 0 + 393 0000 70B5 push {r4, r5, r6, lr} + 394 .LCFI1: + 395 .cfi_def_cfa_offset 16 + 396 .cfi_offset 4, -16 + 397 .cfi_offset 5, -12 + 398 .cfi_offset 6, -8 + 399 .cfi_offset 14, -4 + 400 .LVL18: + 401 .LBB90: + 402 .LBB91: +1668:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 403 .loc 2 1668 0 + 404 0002 0B4B ldr r3, .L26 + 405 0004 5B68 ldr r3, [r3, #4] + 406 0006 C022 movs r2, #192 + 407 0008 5202 lsls r2, r2, #9 + 408 000a 1340 ands r3, r2 + 409 .LVL19: + 410 .LBE91: + 411 .LBE90: + 551:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t pllinputfreq = 0U, pllsource = 0U; + 552:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 553:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */ + 554:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 555:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Get PLL source */ + 556:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** pllsource = LL_RCC_PLL_GetMainSource(); + 557:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 558:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** switch (pllsource) + 412 .loc 1 558 0 + 413 000c 9342 cmp r3, r2 + 414 000e 01D0 beq .L25 + ARM GAS /tmp/ccTAt98O.s page 53 + + + 559:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 560:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + 561:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + 562:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; + 415 .loc 1 562 0 + 416 0010 0848 ldr r0, .L26+4 + 417 0012 00E0 b .L24 + 418 .L25: + 563:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #else + 564:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */ + 565:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** pllinputfreq = HSI_VALUE / 2U; + 566:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + 567:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 568:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 569:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(RCC_HSI48_SUPPORT) + 570:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSI48: /* HSI48 used as PLL clock source */ + 571:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** pllinputfreq = HSI48_VALUE; + 419 .loc 1 571 0 + 420 0014 0848 ldr r0, .L26+8 + 421 .L24: + 422 .LVL20: + 423 .LBB92: + 424 .LBB93: +1720:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 425 .loc 2 1720 0 + 426 0016 064D ldr r5, .L26 + 427 0018 E96A ldr r1, [r5, #44] + 428 001a 0F24 movs r4, #15 + 429 001c 2140 ands r1, r4 + 430 .LBE93: + 431 .LBE92: + 572:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 573:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* RCC_HSI48_SUPPORT */ + 574:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 575:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + 576:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** pllinputfreq = HSE_VALUE; + 577:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 578:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 579:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** default: + 580:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + 581:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; + 582:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #else + 583:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** pllinputfreq = HSI_VALUE / 2U; + 584:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + 585:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 586:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 587:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + 588:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPredi + 432 .loc 1 588 0 + 433 001e 0131 adds r1, r1, #1 + 434 0020 FFF7FEFF bl __aeabi_uidiv + 435 .LVL21: + 436 .LBB94: + 437 .LBB95: +1693:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 438 .loc 2 1693 0 + 439 0024 6B68 ldr r3, [r5, #4] + ARM GAS /tmp/ccTAt98O.s page 54 + + + 440 .LBE95: + 441 .LBE94: + 442 .loc 1 588 0 + 443 0026 9B0C lsrs r3, r3, #18 + 444 0028 1C40 ands r4, r3 + 445 002a 0234 adds r4, r4, #2 + 446 002c 6043 muls r0, r4 + 589:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #else + 590:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMu + 591:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + 592:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 447 .loc 1 592 0 + 448 @ sp needed + 449 002e 70BD pop {r4, r5, r6, pc} + 450 .L27: + 451 .align 2 + 452 .L26: + 453 0030 00100240 .word 1073876992 + 454 0034 00127A00 .word 8000000 + 455 0038 006CDC02 .word 48000000 + 456 .cfi_endproc + 457 .LFE160: + 459 .section .text.LL_RCC_GetUSBClockFreq,"ax",%progbits + 460 .align 1 + 461 .global LL_RCC_GetUSBClockFreq + 462 .syntax unified + 463 .code 16 + 464 .thumb_func + 465 .fpu softvfp + 467 LL_RCC_GetUSBClockFreq: + 468 .LFB155: + 401:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 469 .loc 1 401 0 + 470 .cfi_startproc + 471 @ args = 0, pretend = 0, frame = 0 + 472 @ frame_needed = 0, uses_anonymous_args = 0 + 473 .LVL22: + 474 0000 10B5 push {r4, lr} + 475 .LCFI2: + 476 .cfi_def_cfa_offset 8 + 477 .cfi_offset 4, -8 + 478 .cfi_offset 14, -4 + 479 .LVL23: + 480 .LBB96: + 481 .LBB97: +1401:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 482 .loc 2 1401 0 + 483 0002 0B4B ldr r3, .L36 + 484 0004 1B6B ldr r3, [r3, #48] + 485 0006 1840 ands r0, r3 + 486 .LVL24: + 487 .LBE97: + 488 .LBE96: + 408:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 489 .loc 1 408 0 + 490 0008 8028 cmp r0, #128 + 491 000a 08D1 bne .L34 + ARM GAS /tmp/ccTAt98O.s page 55 + + + 492 .LBB98: + 493 .LBB99: +1530:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 494 .loc 2 1530 0 + 495 000c 084B ldr r3, .L36 + 496 000e 1B68 ldr r3, [r3] + 497 .LBE99: + 498 .LBE98: + 411:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 499 .loc 1 411 0 + 500 0010 9B01 lsls r3, r3, #6 + 501 0012 01D4 bmi .L35 + 402:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 502 .loc 1 402 0 + 503 0014 0020 movs r0, #0 + 504 0016 07E0 b .L28 + 505 .L35: + 413:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 506 .loc 1 413 0 + 507 0018 FFF7FEFF bl RCC_PLL_GetFreqDomain_SYS + 508 .LVL25: + 509 001c 04E0 b .L28 + 510 .LVL26: + 511 .L34: + 512 .LBB100: + 513 .LBB101: + 845:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 514 .loc 2 845 0 + 515 001e 044B ldr r3, .L36 + 516 0020 5B6B ldr r3, [r3, #52] + 517 .LBE101: + 518 .LBE100: + 420:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 519 .loc 1 420 0 + 520 0022 9B03 lsls r3, r3, #14 + 521 0024 01D4 bmi .L33 + 402:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 522 .loc 1 402 0 + 523 0026 0020 movs r0, #0 + 524 .LVL27: + 525 .L28: + 434:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** #endif /* USB */ + 526 .loc 1 434 0 + 527 @ sp needed + 528 0028 10BD pop {r4, pc} + 529 .LVL28: + 530 .L33: + 422:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 531 .loc 1 422 0 + 532 002a 0248 ldr r0, .L36+4 + 533 .LVL29: + 433:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 534 .loc 1 433 0 + 535 002c FCE7 b .L28 + 536 .L37: + 537 002e C046 .align 2 + 538 .L36: + ARM GAS /tmp/ccTAt98O.s page 56 + + + 539 0030 00100240 .word 1073876992 + 540 0034 006CDC02 .word 48000000 + 541 .cfi_endproc + 542 .LFE155: + 544 .section .text.RCC_GetSystemClockFreq,"ax",%progbits + 545 .align 1 + 546 .global RCC_GetSystemClockFreq + 547 .syntax unified + 548 .code 16 + 549 .thumb_func + 550 .fpu softvfp + 552 RCC_GetSystemClockFreq: + 553 .LFB157: + 492:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t frequency = 0U; + 554 .loc 1 492 0 + 555 .cfi_startproc + 556 @ args = 0, pretend = 0, frame = 0 + 557 @ frame_needed = 0, uses_anonymous_args = 0 + 558 0000 10B5 push {r4, lr} + 559 .LCFI3: + 560 .cfi_def_cfa_offset 8 + 561 .cfi_offset 4, -8 + 562 .cfi_offset 14, -4 + 563 .LVL30: + 564 .LBB102: + 565 .LBB103: +1118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 566 .loc 2 1118 0 + 567 0002 074B ldr r3, .L43 + 568 0004 5A68 ldr r2, [r3, #4] + 569 0006 0C23 movs r3, #12 + 570 0008 1340 ands r3, r2 + 571 .LBE103: + 572 .LBE102: + 496:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 573 .loc 1 496 0 + 574 000a 082B cmp r3, #8 + 575 000c 03D0 beq .L40 + 576 000e 0C2B cmp r3, #12 + 577 0010 04D0 beq .L42 + 499:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 578 .loc 1 499 0 + 579 0012 0448 ldr r0, .L43+4 + 580 .LVL31: + 581 .L38: + 522:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 582 .loc 1 522 0 + 583 @ sp needed + 584 0014 10BD pop {r4, pc} + 585 .LVL32: + 586 .L40: + 507:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 587 .loc 1 507 0 + 588 0016 FFF7FEFF bl RCC_PLL_GetFreqDomain_SYS + 589 .LVL33: + 508:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 590 .loc 1 508 0 + ARM GAS /tmp/ccTAt98O.s page 57 + + + 591 001a FBE7 b .L38 + 592 .LVL34: + 593 .L42: + 512:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 594 .loc 1 512 0 + 595 001c 0248 ldr r0, .L43+8 + 596 .LVL35: + 521:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 597 .loc 1 521 0 + 598 001e F9E7 b .L38 + 599 .L44: + 600 .align 2 + 601 .L43: + 602 0020 00100240 .word 1073876992 + 603 0024 00127A00 .word 8000000 + 604 0028 006CDC02 .word 48000000 + 605 .cfi_endproc + 606 .LFE157: + 608 .section .text.LL_RCC_GetSystemClocksFreq,"ax",%progbits + 609 .align 1 + 610 .global LL_RCC_GetSystemClocksFreq + 611 .syntax unified + 612 .code 16 + 613 .thumb_func + 614 .fpu softvfp + 616 LL_RCC_GetSystemClocksFreq: + 617 .LFB152: + 228:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** /* Get SYSCLK frequency */ + 618 .loc 1 228 0 + 619 .cfi_startproc + 620 @ args = 0, pretend = 0, frame = 0 + 621 @ frame_needed = 0, uses_anonymous_args = 0 + 622 .LVL36: + 623 0000 10B5 push {r4, lr} + 624 .LCFI4: + 625 .cfi_def_cfa_offset 8 + 626 .cfi_offset 4, -8 + 627 .cfi_offset 14, -4 + 628 0002 0400 movs r4, r0 + 230:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 629 .loc 1 230 0 + 630 0004 FFF7FEFF bl RCC_GetSystemClockFreq + 631 .LVL37: + 632 0008 2060 str r0, [r4] + 233:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 633 .loc 1 233 0 + 634 000a FFF7FEFF bl RCC_GetHCLKClockFreq + 635 .LVL38: + 636 000e 6060 str r0, [r4, #4] + 236:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 637 .loc 1 236 0 + 638 0010 FFF7FEFF bl RCC_GetPCLK1ClockFreq + 639 .LVL39: + 640 0014 A060 str r0, [r4, #8] + 237:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 641 .loc 1 237 0 + 642 @ sp needed + ARM GAS /tmp/ccTAt98O.s page 58 + + + 643 .LVL40: + 644 0016 10BD pop {r4, pc} + 645 .cfi_endproc + 646 .LFE152: + 648 .section .text.LL_RCC_GetUSARTClockFreq,"ax",%progbits + 649 .align 1 + 650 .global LL_RCC_GetUSARTClockFreq + 651 .syntax unified + 652 .code 16 + 653 .thumb_func + 654 .fpu softvfp + 656 LL_RCC_GetUSARTClockFreq: + 657 .LFB153: + 251:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 658 .loc 1 251 0 + 659 .cfi_startproc + 660 @ args = 0, pretend = 0, frame = 0 + 661 @ frame_needed = 0, uses_anonymous_args = 0 + 662 .LVL41: + 663 0000 10B5 push {r4, lr} + 664 .LCFI5: + 665 .cfi_def_cfa_offset 8 + 666 .cfi_offset 4, -8 + 667 .cfi_offset 14, -4 + 668 .LVL42: + 257:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 669 .loc 1 257 0 + 670 0002 0028 cmp r0, #0 + 671 0004 23D1 bne .L52 + 672 .LVL43: + 673 .LBB104: + 674 .LBB105: +1353:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 675 .loc 2 1353 0 + 676 0006 134B ldr r3, .L57 + 677 0008 1A6B ldr r2, [r3, #48] + 678 000a 0323 movs r3, #3 + 679 000c 8340 lsls r3, r3, r0 + 680 000e 1340 ands r3, r2 + 681 0010 0206 lsls r2, r0, #24 + 682 0012 1343 orrs r3, r2 + 683 .LVL44: + 684 .LBE105: + 685 .LBE104: + 260:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 686 .loc 1 260 0 + 687 0014 022B cmp r3, #2 + 688 0016 13D0 beq .L49 + 689 0018 032B cmp r3, #3 + 690 001a 0BD0 beq .L50 + 691 001c 012B cmp r3, #1 + 692 001e 06D0 beq .L56 + 282:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 693 .loc 1 282 0 + 694 0020 FFF7FEFF bl RCC_GetSystemClockFreq + 695 .LVL45: + 696 0024 FFF7FEFF bl RCC_GetHCLKClockFreq + ARM GAS /tmp/ccTAt98O.s page 59 + + + 697 .LVL46: + 698 0028 FFF7FEFF bl RCC_GetPCLK1ClockFreq + 699 .LVL47: + 283:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 700 .loc 1 283 0 + 701 002c 10E0 b .L46 + 702 .LVL48: + 703 .L56: + 263:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 704 .loc 1 263 0 + 705 002e FFF7FEFF bl RCC_GetSystemClockFreq + 706 .LVL49: + 264:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 707 .loc 1 264 0 + 708 0032 0DE0 b .L46 + 709 .LVL50: + 710 .L50: + 711 .LBB106: + 712 .LBB107: + 770:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 713 .loc 2 770 0 + 714 0034 074B ldr r3, .L57 + 715 0036 1B68 ldr r3, [r3] + 716 .LBE107: + 717 .LBE106: + 267:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 718 .loc 1 267 0 + 719 0038 9B07 lsls r3, r3, #30 + 720 003a 09D5 bpl .L46 + 269:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 721 .loc 1 269 0 + 722 003c 0648 ldr r0, .L57+4 + 723 .LVL51: + 724 003e 07E0 b .L46 + 725 .LVL52: + 726 .L49: + 727 .LBB108: + 728 .LBB109: +1039:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 729 .loc 2 1039 0 + 730 0040 044B ldr r3, .L57 + 731 0042 1B6A ldr r3, [r3, #32] + 732 .LBE109: + 733 .LBE108: + 274:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 734 .loc 1 274 0 + 735 0044 9B07 lsls r3, r3, #30 + 736 0046 03D5 bpl .L46 + 276:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 737 .loc 1 276 0 + 738 0048 8020 movs r0, #128 + 739 .LVL53: + 740 004a 0002 lsls r0, r0, #8 + 741 .LVL54: + 352:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 742 .loc 1 352 0 + 743 004c 00E0 b .L46 + ARM GAS /tmp/ccTAt98O.s page 60 + + + 744 .LVL55: + 745 .L52: + 252:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 746 .loc 1 252 0 + 747 004e 0020 movs r0, #0 + 748 .LVL56: + 749 .L46: + 353:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 750 .loc 1 353 0 + 751 @ sp needed + 752 0050 10BD pop {r4, pc} + 753 .L58: + 754 0052 C046 .align 2 + 755 .L57: + 756 0054 00100240 .word 1073876992 + 757 0058 00127A00 .word 8000000 + 758 .cfi_endproc + 759 .LFE153: + 761 .section .text.LL_RCC_GetI2CClockFreq,"ax",%progbits + 762 .align 1 + 763 .global LL_RCC_GetI2CClockFreq + 764 .syntax unified + 765 .code 16 + 766 .thumb_func + 767 .fpu softvfp + 769 LL_RCC_GetI2CClockFreq: + 770 .LFB154: + 363:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 771 .loc 1 363 0 + 772 .cfi_startproc + 773 @ args = 0, pretend = 0, frame = 0 + 774 @ frame_needed = 0, uses_anonymous_args = 0 + 775 .LVL57: + 776 0000 10B5 push {r4, lr} + 777 .LCFI6: + 778 .cfi_def_cfa_offset 8 + 779 .cfi_offset 4, -8 + 780 .cfi_offset 14, -4 + 781 .LVL58: + 370:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 782 .loc 1 370 0 + 783 0002 1028 cmp r0, #16 + 784 0004 01D0 beq .L66 + 364:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 785 .loc 1 364 0 + 786 0006 0020 movs r0, #0 + 787 .LVL59: + 788 .L59: + 389:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 789 .loc 1 389 0 + 790 @ sp needed + 791 0008 10BD pop {r4, pc} + 792 .LVL60: + 793 .L66: + 794 .LBB110: + 795 .LBB111: +1367:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + ARM GAS /tmp/ccTAt98O.s page 61 + + + 796 .loc 2 1367 0 + 797 000a 084B ldr r3, .L68 + 798 000c 1B6B ldr r3, [r3, #48] + 799 000e 1840 ands r0, r3 + 800 .LVL61: + 801 .LBE111: + 802 .LBE110: + 372:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 803 .loc 1 372 0 + 804 0010 1028 cmp r0, #16 + 805 0012 05D0 beq .L67 + 806 .LBB112: + 807 .LBB113: + 770:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 808 .loc 2 770 0 + 809 0014 054B ldr r3, .L68 + 810 0016 1B68 ldr r3, [r3] + 811 .LBE113: + 812 .LBE112: + 380:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** { + 813 .loc 1 380 0 + 814 0018 9B07 lsls r3, r3, #30 + 815 001a 04D4 bmi .L64 + 364:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 816 .loc 1 364 0 + 817 001c 0020 movs r0, #0 + 818 001e F3E7 b .L59 + 819 .L67: + 375:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** break; + 820 .loc 1 375 0 + 821 0020 FFF7FEFF bl RCC_GetSystemClockFreq + 822 .LVL62: + 376:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** + 823 .loc 1 376 0 + 824 0024 F0E7 b .L59 + 825 .LVL63: + 826 .L64: + 382:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 827 .loc 1 382 0 + 828 0026 0248 ldr r0, .L68+4 + 829 .LVL64: + 388:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c **** } + 830 .loc 1 388 0 + 831 0028 EEE7 b .L59 + 832 .L69: + 833 002a C046 .align 2 + 834 .L68: + 835 002c 00100240 .word 1073876992 + 836 0030 00127A00 .word 8000000 + 837 .cfi_endproc + 838 .LFE154: + 840 .text + 841 .Letext0: + 842 .file 3 "/usr/include/newlib/machine/_default_types.h" + 843 .file 4 "/usr/include/newlib/sys/_stdint.h" + 844 .file 5 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h" + 845 .file 6 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h" + ARM GAS /tmp/ccTAt98O.s page 62 + + + 846 .file 7 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h" + ARM GAS /tmp/ccTAt98O.s page 63 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f0xx_ll_rcc.c + /tmp/ccTAt98O.s:16 .text.LL_RCC_DeInit:0000000000000000 $t + /tmp/ccTAt98O.s:23 .text.LL_RCC_DeInit:0000000000000000 LL_RCC_DeInit + /tmp/ccTAt98O.s:203 .text.LL_RCC_DeInit:00000000000000ac $d + /tmp/ccTAt98O.s:212 .text.LL_RCC_GetCECClockFreq:0000000000000000 $t + /tmp/ccTAt98O.s:219 .text.LL_RCC_GetCECClockFreq:0000000000000000 LL_RCC_GetCECClockFreq + /tmp/ccTAt98O.s:289 .text.LL_RCC_GetCECClockFreq:000000000000002c $d + /tmp/ccTAt98O.s:295 .text.RCC_GetHCLKClockFreq:0000000000000000 $t + /tmp/ccTAt98O.s:302 .text.RCC_GetHCLKClockFreq:0000000000000000 RCC_GetHCLKClockFreq + /tmp/ccTAt98O.s:331 .text.RCC_GetHCLKClockFreq:0000000000000014 $d + /tmp/ccTAt98O.s:337 .text.RCC_GetPCLK1ClockFreq:0000000000000000 $t + /tmp/ccTAt98O.s:344 .text.RCC_GetPCLK1ClockFreq:0000000000000000 RCC_GetPCLK1ClockFreq + /tmp/ccTAt98O.s:373 .text.RCC_GetPCLK1ClockFreq:0000000000000014 $d + /tmp/ccTAt98O.s:380 .text.RCC_PLL_GetFreqDomain_SYS:0000000000000000 $t + /tmp/ccTAt98O.s:387 .text.RCC_PLL_GetFreqDomain_SYS:0000000000000000 RCC_PLL_GetFreqDomain_SYS + /tmp/ccTAt98O.s:453 .text.RCC_PLL_GetFreqDomain_SYS:0000000000000030 $d + /tmp/ccTAt98O.s:460 .text.LL_RCC_GetUSBClockFreq:0000000000000000 $t + /tmp/ccTAt98O.s:467 .text.LL_RCC_GetUSBClockFreq:0000000000000000 LL_RCC_GetUSBClockFreq + /tmp/ccTAt98O.s:539 .text.LL_RCC_GetUSBClockFreq:0000000000000030 $d + /tmp/ccTAt98O.s:545 .text.RCC_GetSystemClockFreq:0000000000000000 $t + /tmp/ccTAt98O.s:552 .text.RCC_GetSystemClockFreq:0000000000000000 RCC_GetSystemClockFreq + /tmp/ccTAt98O.s:602 .text.RCC_GetSystemClockFreq:0000000000000020 $d + /tmp/ccTAt98O.s:609 .text.LL_RCC_GetSystemClocksFreq:0000000000000000 $t + /tmp/ccTAt98O.s:616 .text.LL_RCC_GetSystemClocksFreq:0000000000000000 LL_RCC_GetSystemClocksFreq + /tmp/ccTAt98O.s:649 .text.LL_RCC_GetUSARTClockFreq:0000000000000000 $t + /tmp/ccTAt98O.s:656 .text.LL_RCC_GetUSARTClockFreq:0000000000000000 LL_RCC_GetUSARTClockFreq + /tmp/ccTAt98O.s:756 .text.LL_RCC_GetUSARTClockFreq:0000000000000054 $d + /tmp/ccTAt98O.s:762 .text.LL_RCC_GetI2CClockFreq:0000000000000000 $t + /tmp/ccTAt98O.s:769 .text.LL_RCC_GetI2CClockFreq:0000000000000000 LL_RCC_GetI2CClockFreq + /tmp/ccTAt98O.s:835 .text.LL_RCC_GetI2CClockFreq:000000000000002c $d + +UNDEFINED SYMBOLS +AHBPrescTable +APBPrescTable +__aeabi_uidiv diff --git a/bsl/makeLowLayer/build/stm32f0xx_ll_utils.lst b/bsl/makeLowLayer/build/stm32f0xx_ll_utils.lst new file mode 100644 index 0000000..642a305 --- /dev/null +++ b/bsl/makeLowLayer/build/stm32f0xx_ll_utils.lst @@ -0,0 +1,5496 @@ +ARM GAS /tmp/cctNXKqU.s page 1 + + + 1 .cpu cortex-m0 + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32f0xx_ll_utils.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .global __aeabi_uidiv + 16 .section .text.UTILS_GetPLLOutputFrequency,"ax",%progbits + 17 .align 1 + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 UTILS_GetPLLOutputFrequency: + 24 .LFB193: + 25 .file 1 "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c" + 1:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @file stm32f0xx_ll_utils.c + 4:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @brief UTILS LL module driver. + 6:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ****************************************************************************** + 7:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @attention + 8:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * + 9:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** *

© Copyright (c) 2016 STMicroelectronics. + 10:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * All rights reserved.

+ 11:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * + 12:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * This software component is licensed by ST under BSD 3-Clause license, + 13:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * the "License"; You may not use this file except in compliance with the + 14:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * License. You may obtain a copy of the License at: + 15:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * opensource.org/licenses/BSD-3-Clause + 16:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * + 17:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ****************************************************************************** + 18:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 19:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 20:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Includes ------------------------------------------------------------------*/ + 21:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #include "stm32f0xx_ll_rcc.h" + 22:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #include "stm32f0xx_ll_utils.h" + 23:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #include "stm32f0xx_ll_system.h" + 24:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #ifdef USE_FULL_ASSERT + 25:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #include "stm32_assert.h" + 26:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #else + 27:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #define assert_param(expr) ((void)0U) + 28:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #endif + 29:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 30:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** @addtogroup STM32F0xx_LL_Driver + 31:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @{ + 32:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 33:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + ARM GAS /tmp/cctNXKqU.s page 2 + + + 34:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** @addtogroup UTILS_LL + 35:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @{ + 36:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 37:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 38:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Private types -------------------------------------------------------------*/ + 39:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Private variables ---------------------------------------------------------*/ + 40:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Private constants ---------------------------------------------------------*/ + 41:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** @addtogroup UTILS_LL_Private_Constants + 42:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @{ + 43:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 44:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 45:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Defines used for PLL range */ + 46:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #define UTILS_PLL_OUTPUT_MIN 16000000U /*!< Frequency min for PLL output, in Hz * + 47:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #define UTILS_PLL_OUTPUT_MAX 48000000U /*!< Frequency max for PLL output, in Hz */ + 48:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 49:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Defines used for HSE range */ + 50:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz * + 51:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz * + 52:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 53:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Defines used for FLASH latency according to SYSCLK Frequency */ + 54:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 * + 55:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 56:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @} + 57:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 58:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Private macros ------------------------------------------------------------*/ + 59:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** @addtogroup UTILS_LL_Private_Macros + 60:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @{ + 61:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 62:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ + 63:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ + 64:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ + 65:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ + 66:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ + 67:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ + 68:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ + 69:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ + 70:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) + 71:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 72:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ + 73:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ + 74:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ + 75:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ + 76:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB1_DIV_16)) + 77:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 78:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \ + 79:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_3) \ + 80:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_4) \ + 81:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_5) \ + 82:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_6) \ + 83:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_7) \ + 84:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_8) \ + 85:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_9) \ + 86:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_10) \ + 87:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_11) \ + 88:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_12) \ + 89:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_13) \ + 90:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_14) \ + ARM GAS /tmp/cctNXKqU.s page 3 + + + 91:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_15) \ + 92:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLL_MUL_16)) + 93:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 94:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) + 95:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) + 96:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) + 97:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) + 98:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) + 99:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) + 100:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) + 101:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) + 102:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 103:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((UTILS_PLL_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) + 104:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 105:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 106:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ + 107:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) + 108:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 109:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ( + 110:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 111:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @} + 112:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 113:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Private function prototypes -----------------------------------------------*/ + 114:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** @defgroup UTILS_LL_Private_Functions UTILS Private functions + 115:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @{ + 116:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 117:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, + 118:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); + 119:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDe + 120:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** static ErrorStatus UTILS_PLL_IsBusy(void); + 121:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 122:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @} + 123:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 124:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 125:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Exported functions --------------------------------------------------------*/ + 126:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** @addtogroup UTILS_LL_Exported_Functions + 127:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @{ + 128:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 129:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 130:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** @addtogroup UTILS_LL_EF_DELAY + 131:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @{ + 132:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 133:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 134:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 135:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + 136:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @note When a RTOS is used, it is recommended to avoid changing the Systick + 137:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * configuration by calling this function, for a delay use rather osDelay RTOS service. + 138:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @param HCLKFrequency HCLK frequency in Hz + 139:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_Get + 140:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @retval None + 141:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 142:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** void LL_Init1msTick(uint32_t HCLKFrequency) + 143:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 144:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Use frequency provided in argument */ + 145:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_InitTick(HCLKFrequency, 1000U); + 146:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 147:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + ARM GAS /tmp/cctNXKqU.s page 4 + + + 148:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 149:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @brief This function provides accurate delay (in milliseconds) based + 150:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * on SysTick counter flag + 151:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @note When a RTOS is used, it is recommended to avoid using blocking delay + 152:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * and use rather osDelay service. + 153:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which + 154:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * will configure Systick to 1ms + 155:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @param Delay specifies the delay time length, in milliseconds. + 156:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @retval None + 157:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 158:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** void LL_mDelay(uint32_t Delay) + 159:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 160:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + 161:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Add this code to indicate that local variable is not used */ + 162:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ((void)tmp); + 163:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 164:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Add a period to guaranty minimum wait */ + 165:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if (Delay < LL_MAX_DELAY) + 166:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 167:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** Delay++; + 168:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 169:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 170:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** while (Delay) + 171:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 172:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) + 173:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 174:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** Delay--; + 175:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 176:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 177:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 178:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 179:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 180:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @} + 181:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 182:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 183:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** @addtogroup UTILS_EF_SYSTEM + 184:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @brief System Configuration functions + 185:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * + 186:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** @verbatim + 187:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** =============================================================================== + 188:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ##### System Configuration functions ##### + 189:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** =============================================================================== + 190:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** [..] + 191:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** System, AHB and APB buses clocks configuration + 192:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 193:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 48000000 Hz. + 194:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** @endverbatim + 195:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** @internal + 196:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** Depending on the SYSCLK frequency, the flash latency should be adapted accordingly: + 197:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** (++) +-----------------------------------------------+ + 198:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** (++) | Latency | SYSCLK clock frequency (MHz) | + 199:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** (++) |---------------|-------------------------------| + 200:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | + 201:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** (++) |---------------|-------------------------------| + 202:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | + 203:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** (++) +-----------------------------------------------+ + 204:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** @endinternal + ARM GAS /tmp/cctNXKqU.s page 5 + + + 205:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @{ + 206:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 207:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 208:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 209:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @brief This function sets directly SystemCoreClock CMSIS variable. + 210:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @note Variable can be calculated also through SystemCoreClockUpdate function. + 211:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + 212:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @retval None + 213:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 214:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** void LL_SetSystemCoreClock(uint32_t HCLKFrequency) + 215:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 216:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* HCLK clock frequency */ + 217:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** SystemCoreClock = HCLKFrequency; + 218:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 219:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 220:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 221:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @brief Update number of Flash wait states in line with new frequency and current + 222:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** voltage range. + 223:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @param Frequency SYSCLK frequency + 224:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @retval An ErrorStatus enumeration value: + 225:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - SUCCESS: Latency has been modified + 226:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - ERROR: Latency cannot be modified + 227:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 228:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #if defined(FLASH_ACR_LATENCY) + 229:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ErrorStatus LL_SetFlashLatency(uint32_t Frequency) + 230:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 231:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** uint32_t timeout; + 232:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** uint32_t getlatency; + 233:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** uint32_t latency; + 234:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 235:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 236:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Frequency cannot be equal to 0 */ + 237:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if (Frequency == 0U) + 238:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 239:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** status = ERROR; + 240:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 241:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** else + 242:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 243:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if (Frequency > UTILS_LATENCY1_FREQ) + 244:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 245:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */ + 246:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** latency = LL_FLASH_LATENCY_1; + 247:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 248:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** else + 249:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 250:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */ + 251:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** latency = LL_FLASH_LATENCY_0; + 252:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 253:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if (status != ERROR) + 254:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 255:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_FLASH_SetLatency(latency); + 256:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 257:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Check that the new number of wait states is taken into account to access the Flash + 258:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** memory by reading the FLASH_ACR register */ + 259:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** timeout = 2; + 260:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** do + 261:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + ARM GAS /tmp/cctNXKqU.s page 6 + + + 262:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Wait for Flash latency to be updated */ + 263:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** getlatency = LL_FLASH_GetLatency(); + 264:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** timeout--; + 265:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } while ((getlatency != latency) && (timeout > 0)); + 266:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 267:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if(getlatency != latency) + 268:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 269:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** status = ERROR; + 270:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 271:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** else + 272:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 273:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** status = SUCCESS; + 274:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 275:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 276:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 277:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 278:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** return status; + 279:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 280:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #endif /* FLASH_ACR_LATENCY */ + 281:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 282:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 283:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @brief This function configures system clock with HSI as clock source of the PLL + 284:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @note The application need to ensure that PLL is disabled. + 285:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @note Function is based on the following formula: + 286:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL) + 287:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - PREDIV: Set to 2 for few devices + 288:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - PLLMUL: The application software must set correctly the PLL multiplication factor to + 289:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * be in the range 16-48MHz + 290:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @note FLASH latency can be modified through this function. + 291:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + 292:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * the configuration information for the PLL. + 293:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + 294:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * the configuration information for the BUS prescalers. + 295:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @retval An ErrorStatus enumeration value: + 296:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - SUCCESS: Max frequency configuration done + 297:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - ERROR: Max frequency configuration not done + 298:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 299:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + 300:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) + 301:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 302:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 303:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** uint32_t pllfreq = 0U; + 304:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 305:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Check if one of the PLL is enabled */ + 306:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if (UTILS_PLL_IsBusy() == SUCCESS) + 307:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 308:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + 309:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Check PREDIV value */ + 310:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); + 311:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #else + 312:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Force PREDIV value to 2 */ + 313:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2; + 314:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + 315:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Calculate the new PLL output frequency */ + 316:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); + 317:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 318:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Enable HSI if not enabled */ + ARM GAS /tmp/cctNXKqU.s page 7 + + + 319:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if (LL_RCC_HSI_IsReady() != 1U) + 320:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 321:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_RCC_HSI_Enable(); + 322:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** while (LL_RCC_HSI_IsReady() != 1U) + 323:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 324:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Wait for HSI ready */ + 325:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 326:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 327:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 328:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Configure PLL */ + 329:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + 330:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStr + 331:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #else + 332:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul); + 333:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + 334:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 335:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Enable PLL and switch system clock to PLL */ + 336:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + 337:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 338:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** else + 339:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 340:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Current PLL configuration cannot be modified */ + 341:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** status = ERROR; + 342:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 343:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 344:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** return status; + 345:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 346:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 347:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #if defined(RCC_CFGR_SW_HSI48) + 348:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 349:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @brief This function configures system clock with HSI48 as clock source of the PLL + 350:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @note The application need to ensure that PLL is disabled. + 351:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @note Function is based on the following formula: + 352:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - PLL output frequency = ((HSI48 frequency / PREDIV) * PLLMUL) + 353:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - PLLMUL: The application software must set correctly the PLL multiplication factor to + 354:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * be in the range 16-48MHz + 355:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + 356:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * the configuration information for the PLL. + 357:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + 358:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * the configuration information for the BUS prescalers. + 359:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @retval An ErrorStatus enumeration value: + 360:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - SUCCESS: Max frequency configuration done + 361:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - ERROR: Max frequency configuration not done + 362:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 363:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + 364:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) + 365:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 366:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 367:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** uint32_t pllfreq = 0U; + 368:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 369:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Check if one of the PLL is enabled */ + 370:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if (UTILS_PLL_IsBusy() == SUCCESS) + 371:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 372:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Check PREDIV value */ + 373:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); + 374:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 375:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Calculate the new PLL output frequency */ + ARM GAS /tmp/cctNXKqU.s page 8 + + + 376:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** pllfreq = UTILS_GetPLLOutputFrequency(HSI48_VALUE, UTILS_PLLInitStruct); + 377:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 378:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Enable HSI48 if not enabled */ + 379:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if (LL_RCC_HSI48_IsReady() != 1U) + 380:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 381:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_RCC_HSI48_Enable(); + 382:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** while (LL_RCC_HSI48_IsReady() != 1U) + 383:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 384:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Wait for HSI48 ready */ + 385:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 386:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 387:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 388:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Configure PLL */ + 389:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI48, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitS + 390:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 391:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Enable PLL and switch system clock to PLL */ + 392:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + 393:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 394:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** else + 395:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 396:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Current PLL configuration cannot be modified */ + 397:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** status = ERROR; + 398:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 399:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 400:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** return status; + 401:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 402:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 403:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #endif /*RCC_CFGR_SW_HSI48*/ + 404:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 405:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @brief This function configures system clock with HSE as clock source of the PLL + 406:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @note The application need to ensure that PLL is disabled. + 407:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @note Function is based on the following formula: + 408:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - PLL output frequency = ((HSE frequency / PREDIV) * PLLMUL) + 409:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - PLLMUL: The application software must set correctly the PLL multiplication factor to + 410:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * be in the range 16-48MHz + 411:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @note FLASH latency can be modified through this function. + 412:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 32000000 + 413:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @param HSEBypass This parameter can be one of the following values: + 414:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @arg @ref LL_UTILS_HSEBYPASS_ON + 415:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @arg @ref LL_UTILS_HSEBYPASS_OFF + 416:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + 417:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * the configuration information for the PLL. + 418:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + 419:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * the configuration information for the BUS prescalers. + 420:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @retval An ErrorStatus enumeration value: + 421:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - SUCCESS: Max frequency configuration done + 422:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - ERROR: Max frequency configuration not done + 423:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 424:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + 425:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_Clk + 426:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 427:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 428:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** uint32_t pllfreq = 0U; + 429:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 430:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Check the parameters */ + 431:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); + 432:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); + ARM GAS /tmp/cctNXKqU.s page 9 + + + 433:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 434:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Check if one of the PLL is enabled */ + 435:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if (UTILS_PLL_IsBusy() == SUCCESS) + 436:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 437:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Check PREDIV value */ + 438:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + 439:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); + 440:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #else + 441:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv)); + 442:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + 443:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 444:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Calculate the new PLL output frequency */ + 445:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); + 446:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 447:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Enable HSE if not enabled */ + 448:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if (LL_RCC_HSE_IsReady() != 1U) + 449:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 450:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Check if need to enable HSE bypass feature or not */ + 451:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if (HSEBypass == LL_UTILS_HSEBYPASS_ON) + 452:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 453:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_RCC_HSE_EnableBypass(); + 454:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 455:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** else + 456:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 457:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_RCC_HSE_DisableBypass(); + 458:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 459:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 460:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Enable HSE */ + 461:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_RCC_HSE_Enable(); + 462:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** while (LL_RCC_HSE_IsReady() != 1U) + 463:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 464:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Wait for HSE ready */ + 465:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 466:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 467:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 468:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Configure PLL */ + 469:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + 470:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitS + 471:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #else + 472:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_P + 473:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + 474:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 475:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Enable PLL and switch system clock to PLL */ + 476:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + 477:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 478:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** else + 479:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 480:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Current PLL configuration cannot be modified */ + 481:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** status = ERROR; + 482:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 483:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 484:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** return status; + 485:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 486:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 487:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 488:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @} + 489:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + ARM GAS /tmp/cctNXKqU.s page 10 + + + 490:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 491:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 492:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @} + 493:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 494:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 495:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** @addtogroup UTILS_LL_Private_Functions + 496:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @{ + 497:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 498:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 499:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @brief Function to check that PLL can be modified + 500:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @param PLL_InputFrequency PLL input frequency (in Hz) + 501:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + 502:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * the configuration information for the PLL. + 503:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @retval PLL output frequency (in Hz) + 504:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 505:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *U + 506:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 26 .loc 1 506 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 .LVL0: + 31 0000 70B5 push {r4, r5, r6, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 16 + 34 .cfi_offset 4, -16 + 35 .cfi_offset 5, -12 + 36 .cfi_offset 6, -8 + 37 .cfi_offset 14, -4 + 38 0002 0D00 movs r5, r1 + 39 .LVL1: + 507:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** uint32_t pllfreq = 0U; + 508:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 509:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Check the parameters */ + 510:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul)); + 511:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 512:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Check different PLL parameters according to RM */ + 513:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* The application software must set correctly the PLL multiplication factor to + 514:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** be in the range 16-48MHz */ + 515:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + 516:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLIni + 40 .loc 1 516 0 + 41 0004 0F24 movs r4, #15 + 42 0006 4968 ldr r1, [r1, #4] + 43 .LVL2: + 44 0008 2140 ands r1, r4 + 45 000a 0131 adds r1, r1, #1 + 46 000c FFF7FEFF bl __aeabi_uidiv + 47 .LVL3: + 48 0010 2B68 ldr r3, [r5] + 49 0012 9B0C lsrs r3, r3, #18 + 50 0014 1C40 ands r4, r3 + 51 0016 0234 adds r4, r4, #2 + 52 0018 6043 muls r0, r4 + 53 .LVL4: + 517:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #else + 518:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTIL + ARM GAS /tmp/cctNXKqU.s page 11 + + + 519:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + 520:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); + 521:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 522:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** return pllfreq; + 523:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 54 .loc 1 523 0 + 55 @ sp needed + 56 .LVL5: + 57 001a 70BD pop {r4, r5, r6, pc} + 58 .cfi_endproc + 59 .LFE193: + 61 .section .text.UTILS_PLL_IsBusy,"ax",%progbits + 62 .align 1 + 63 .syntax unified + 64 .code 16 + 65 .thumb_func + 66 .fpu softvfp + 68 UTILS_PLL_IsBusy: + 69 .LFB194: + 524:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 525:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 526:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @brief Function to check that PLL can be modified + 527:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @retval An ErrorStatus enumeration value: + 528:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - SUCCESS: PLL modification can be done + 529:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - ERROR: PLL is busy + 530:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 531:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** static ErrorStatus UTILS_PLL_IsBusy(void) + 532:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 70 .loc 1 532 0 + 71 .cfi_startproc + 72 @ args = 0, pretend = 0, frame = 0 + 73 @ frame_needed = 0, uses_anonymous_args = 0 + 74 @ link register save eliminated. + 75 .LVL6: + 76 .LBB52: + 77 .LBB53: + 78 .file 2 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h" + 1:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @file stm32f0xx_ll_rcc.h + 4:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Header file of RCC LL module. + 6:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** ****************************************************************************** + 7:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @attention + 8:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * + 9:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** *

© Copyright (c) 2016 STMicroelectronics. + 10:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * All rights reserved.

+ 11:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * + 12:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * This software component is licensed by ST under BSD 3-Clause license, + 13:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * the "License"; You may not use this file except in compliance with the + 14:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * License. You may obtain a copy of the License at: + 15:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * opensource.org/licenses/BSD-3-Clause + 16:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * + 17:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** ****************************************************************************** + 18:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 19:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 20:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + ARM GAS /tmp/cctNXKqU.s page 12 + + + 21:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #ifndef __STM32F0xx_LL_RCC_H + 22:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define __STM32F0xx_LL_RCC_H + 23:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 24:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #ifdef __cplusplus + 25:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** extern "C" { + 26:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif + 27:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 28:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Includes ------------------------------------------------------------------*/ + 29:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #include "stm32f0xx.h" + 30:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 31:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @addtogroup STM32F0xx_LL_Driver + 32:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 33:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 34:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 35:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC) + 36:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 37:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL RCC + 38:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 39:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 40:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 41:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Private types -------------------------------------------------------------*/ + 42:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Private variables ---------------------------------------------------------*/ + 43:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Private constants ---------------------------------------------------------*/ + 44:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Constants RCC Private Constants + 45:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 46:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 47:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Defines used for the bit position in the register and perform offsets*/ + 48:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HPRE (uint32_t)4U /*!< field position in register RCC_CFGR */ + 49:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_PPRE1 (uint32_t)8U /*!< field position in register RCC_CFGR */ + 50:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_PLLMUL (uint32_t)18U /*!< field position in register RCC_CFGR */ + 51:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HSICAL (uint32_t)8U /*!< field position in register RCC_CR */ + 52:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HSITRIM (uint32_t)3U /*!< field position in register RCC_CR */ + 53:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HSI14TRIM (uint32_t)3U /*!< field position in register RCC_CR2 */ + 54:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HSI14CAL (uint32_t)8U /*!< field position in register RCC_CR2 */ + 55:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 56:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_HSI48CAL (uint32_t)24U /*!< field position in register RCC_CR2 */ + 57:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 58:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */ + 59:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */ + 60:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */ + 61:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 62:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 63:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 64:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 65:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 66:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Private macros ------------------------------------------------------------*/ + 67:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 68:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Macros RCC Private Macros + 69:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 70:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 71:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 72:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 73:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 74:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /*USE_FULL_LL_DRIVER*/ + 75:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Exported types ------------------------------------------------------------*/ + 76:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 77:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Types RCC Exported Types + ARM GAS /tmp/cctNXKqU.s page 13 + + + 78:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 79:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 80:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 81:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + 82:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 83:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 84:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 85:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 86:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief RCC Clocks Frequency Structure + 87:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 88:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** typedef struct + 89:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 90:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + 91:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + 92:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + 93:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } LL_RCC_ClocksTypeDef; + 94:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 95:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 96:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 97:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 98:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 99:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */ + 103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Exported constants --------------------------------------------------------*/ + 105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + 106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + 110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Defines used to adapt values of different oscillators + 111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note These values could be modified in the user environment according to + 112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * HW set-up. + 113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if !defined (HSE_VALUE) + 116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ + 117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* HSE_VALUE */ + 118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if !defined (HSI_VALUE) + 120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ + 121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* HSI_VALUE */ + 122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if !defined (LSE_VALUE) + 124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ + 125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* LSE_VALUE */ + 126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if !defined (LSI_VALUE) + 128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ + 129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* LSI_VALUE */ + 130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if !defined (HSI48_VALUE) + 133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ + 134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* HSI48_VALUE */ + ARM GAS /tmp/cctNXKqU.s page 14 + + + 135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + 141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_WriteReg function + 142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ + 145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ + 146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ + 147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ + 148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ + 149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC /*!< HSI14 Ready Interrupt Clear */ + 150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI48RDYC RCC_CIR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ + 152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt + 154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 155:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 156:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 157:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 158:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + 159:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_ReadReg function + 160:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 161:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 162:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ + 163:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ + 164:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ + 165:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ + 166:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ + 167:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF /*!< HSI14 Ready Interrupt flag */ + 168:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 169:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI48RDYF RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ + 170:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 171:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt f + 172:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ + 173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ + 174:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ + 175:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ + 176:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset f + 177:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag * + 178:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ + 179:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CSR_V18PWRRSTF) + 180:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V doma + 181:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CSR_V18PWRRSTF */ + 182:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 183:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 184:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 185:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 186:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_IT IT Defines + 187:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + 188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 189:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 190:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ + 191:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ + ARM GAS /tmp/cctNXKqU.s page 15 + + + 192:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ + 193:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ + 194:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ + 195:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE /*!< HSI14 Ready Interrupt Enable * + 196:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 197:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CIR_HSI48RDYIE RCC_CIR_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable * + 198:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 199:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 200:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 201:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 202:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 203:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + 204:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 205:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 206:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving cap + 207:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capa + 208:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving cap + 209:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capabili + 210:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 211:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 212:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 213:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 214:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + 215:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 216:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 217:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ + 218:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ + 219:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ + 220:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_SW_HSI48) + 221:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 /*!< HSI48 selection as system clock + 222:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_SW_HSI48 */ + 223:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 224:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 225:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 226:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 227:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + 228:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 229:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 230:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ + 231:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ + 232:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ + 233:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_SWS_HSI48) + 234:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 /*!< HSI48 used as system clock */ + 235:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_SWS_HSI48 */ + 236:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 237:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 238:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 239:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 240:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + 241:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 242:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 243:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ + 244:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ + 245:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ + 246:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ + 247:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ + 248:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ + ARM GAS /tmp/cctNXKqU.s page 16 + + + 249:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ + 250:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ + 251:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ + 252:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 253:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 254:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 255:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 256:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + 257:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 258:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 259:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */ + 260:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */ + 261:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */ + 262:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */ + 263:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */ + 264:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 265:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 266:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 267:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 268:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + 269:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 270:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 271:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, n + 272:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCOSEL_HSI14 /*!< HSI14 oscillator clock + 273:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MC + 274:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO s + 275:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO s + 276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO s + 277:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO s + 278:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_MCOSEL_HSI48) + 279:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /*!< HSI48 selection as MCO + 280:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_MCOSEL_HSI48 */ + 281:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2 + 282:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_PLLNODIV) + 283:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL + 284:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_PLLNODIV */ + 285:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 286:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 287:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 288:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 289:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + 290:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 291:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 292:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */ + 293:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_MCOPRE) + 294:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ + 295:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ + 296:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ + 297:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ + 298:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */ + 299:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */ + 300:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */ + 301:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_MCOPRE */ + 302:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 303:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 304:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 305:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + ARM GAS /tmp/cctNXKqU.s page 17 + + + 306:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 307:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + 308:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 309:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 310:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the periphera + 311:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as ex + 312:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 313:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 314:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 315:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */ + 316:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 317:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection + 318:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 319:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 320:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USA + 321:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USA + 322:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USA + 323:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USA + 324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR3_USART2SW) + 325:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USA + 326:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USA + 327:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USA + 328:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USA + 329:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR3_USART2SW */ + 330:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR3_USART3SW) + 331:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USA + 332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USA + 333:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USA + 334:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USA + 335:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR3_USART3SW */ + 336:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 337:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 338:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 339:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 340:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection + 341:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 342:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 343:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI /*!< HSI oscillator clock used a + 344:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK /*!< System clock selected as I2 + 345:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 346:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 347:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 348:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 349:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(CEC) + 350:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + 351:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 352:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 353:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 + 354:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HD + 355:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 356:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 357:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 358:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 359:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* CEC */ + 360:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 361:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USB) + 362:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + ARM GAS /tmp/cctNXKqU.s page 18 + + + 363:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 364:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 365:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR3_USBSW_HSI48) + 366:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 oscillator clock used + 367:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #else + 368:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_NONE ((uint32_t)0x00000000) /*!< USB Clock disabled */ + 369:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /*RCC_CFGR3_USBSW_HSI48*/ + 370:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL selected as USB clock s + 371:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 372:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 373:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 374:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 375:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* USB */ + 376:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 377:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source + 378:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 379:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 380:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection + 381:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR3_USART2SW) + 382:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection + 383:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR3_USART2SW */ + 384:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR3_USART3SW) + 385:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection + 386:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR3_USART3SW */ + 387:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 388:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 389:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 390:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 391:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source + 392:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 393:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 394:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */ + 395:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 396:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 397:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 398:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 399:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(CEC) + 400:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + 401:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 402:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 403:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selecti + 404:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 405:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 406:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 407:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* CEC */ + 408:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 409:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USB) + 410:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + 411:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 412:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 413:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE RCC_CFGR3_USBSW /*!< USB Clock source selection + 414:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 415:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 416:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 417:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* USB */ + 418:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 419:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + ARM GAS /tmp/cctNXKqU.s page 19 + + + 420:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 421:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 422:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC + 423:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used a + 424:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used a + 425:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divide + 426:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 427:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 428:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 429:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 430:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor + 431:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 432:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 433:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */ + 434:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */ + 435:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */ + 436:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */ + 437:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */ + 438:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */ + 439:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */ + 440:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */ + 441:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */ + 442:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */ + 443:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */ + 444:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */ + 445:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */ + 446:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */ + 447:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */ + 448:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 449:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 450:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 451:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 452:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE + 453:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 454:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 455:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No cl + 456:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/P + 457:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + 458:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/P + 459:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_SW_HSI48) + 460:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< HSI48 + 461:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_SW_HSI48 */ + 462:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #else + 463:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI c + 464:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) + 465:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) + 466:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) + 467:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) + 468:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) + 469:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) + 470:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) + 471:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) + 472:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) + 473:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) + 474:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) + 475:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) + 476:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) + ARM GAS /tmp/cctNXKqU.s page 20 + + + 477:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) + 478:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) + 479:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) + 480:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + 481:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 482:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 483:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 484:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 485:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor + 486:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 487:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 488:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divi + 489:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided + 490:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided + 491:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided + 492:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided + 493:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided + 494:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided + 495:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided + 496:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided + 497:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided + 498:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided + 499:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided + 500:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided + 501:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided + 502:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided + 503:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided + 504:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 505:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 506:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 507:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 508:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 509:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 510:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 511:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 512:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Exported macro ------------------------------------------------------------*/ + 513:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + 514:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 515:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 516:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 517:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + 518:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 519:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 520:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 521:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 522:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Write a value in RCC register + 523:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __REG__ Register to be written + 524:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __VALUE__ Value to be written in the register + 525:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 526:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 527:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + 528:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 529:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 530:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Read a value in RCC register + 531:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __REG__ Register to be read + 532:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Register value + 533:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + ARM GAS /tmp/cctNXKqU.s page 21 + + + 534:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) + 535:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 536:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 537:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 538:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 539:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + 540:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 541:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 542:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 543:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + 544:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 545:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency + 546:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator() + 547:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * , @ref LL_RCC_PLL_GetPrediv()); + 548:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/HSI48) + 549:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __PLLMUL__ This parameter can be one of the following values: + 550:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_2 + 551:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3 + 552:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4 + 553:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_5 + 554:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6 + 555:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_7 + 556:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8 + 557:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_9 + 558:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_10 + 559:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_11 + 560:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12 + 561:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_13 + 562:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_14 + 563:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_15 + 564:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16 + 565:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __PLLPREDIV__ This parameter can be one of the following values: + 566:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_1 + 567:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_2 + 568:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_3 + 569:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_4 + 570:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_5 + 571:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_6 + 572:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_7 + 573:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_8 + 574:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_9 + 575:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_10 + 576:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_11 + 577:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_12 + 578:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_13 + 579:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_14 + 580:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_15 + 581:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_16 + 582:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) + 583:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 584:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \ + 585:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RC + 586:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 587:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #else + 588:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 589:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency + 590:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref + ARM GAS /tmp/cctNXKqU.s page 22 + + + 591:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2) + 592:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __PLLMUL__ This parameter can be one of the following values: + 593:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_2 + 594:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3 + 595:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4 + 596:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_5 + 597:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6 + 598:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_7 + 599:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8 + 600:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_9 + 601:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_10 + 602:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_11 + 603:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12 + 604:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_13 + 605:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_14 + 606:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_15 + 607:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16 + 608:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) + 609:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 610:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ + 611:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) + 612:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + 613:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 614:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Helper macro to calculate the HCLK frequency + 615:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler + 616:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) + 617:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) + 618:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __AHBPRESCALER__ This parameter can be one of the following values: + 619:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 + 620:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 + 621:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 + 622:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 + 623:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 + 624:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 + 625:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 + 626:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 + 627:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 + 628:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval HCLK clock frequency (in Hz) + 629:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 630:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTabl + 631:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 632:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 633:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + 634:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler + 635:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) + 636:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __HCLKFREQ__ HCLK frequency + 637:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param __APB1PRESCALER__ This parameter can be one of the following values: + 638:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 + 639:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 + 640:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 + 641:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 + 642:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 + 643:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval PCLK1 clock frequency (in Hz) + 644:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 645:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[ + 646:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 647:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + ARM GAS /tmp/cctNXKqU.s page 23 + + + 648:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 649:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 650:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 651:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 652:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 653:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 654:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 655:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /* Exported functions --------------------------------------------------------*/ + 656:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + 657:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 658:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 659:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 660:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSE HSE + 661:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 662:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 663:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 664:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 665:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable the Clock Security System. + 666:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + 667:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 668:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 669:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) + 670:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 671:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_CSSON); + 672:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 673:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 674:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 675:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable the Clock Security System. + 676:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note Cannot be disabled in HSE is ready (only by hardware) + 677:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS + 678:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 679:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 680:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_DisableCSS(void) + 681:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 682:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_CSSON); + 683:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 684:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 685:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 686:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable HSE external oscillator (HSE Bypass) + 687:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + 688:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 689:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 690:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) + 691:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 692:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEBYP); + 693:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 694:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 695:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 696:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable HSE external oscillator (HSE Bypass) + 697:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + 698:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 699:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 700:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) + 701:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 702:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + 703:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 704:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + ARM GAS /tmp/cctNXKqU.s page 24 + + + 705:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 706:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable HSE crystal oscillator (HSE ON) + 707:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Enable + 708:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 709:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 710:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Enable(void) + 711:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 712:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEON); + 713:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 714:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 715:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 716:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable HSE crystal oscillator (HSE ON) + 717:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Disable + 718:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 719:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 720:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Disable(void) + 721:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 722:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEON); + 723:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 724:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 725:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 726:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if HSE oscillator Ready + 727:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + 728:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 729:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 730:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) + 731:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 732:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); + 733:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 734:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 735:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 736:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 737:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 738:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 739:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI HSI + 740:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 741:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 742:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 743:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 744:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable HSI oscillator + 745:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Enable + 746:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 747:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 748:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Enable(void) + 749:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 750:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSION); + 751:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 752:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 753:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 754:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable HSI oscillator + 755:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Disable + 756:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 757:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 758:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Disable(void) + 759:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 760:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSION); + 761:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + ARM GAS /tmp/cctNXKqU.s page 25 + + + 762:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 763:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 764:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if HSI clock is ready + 765:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + 766:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 767:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 768:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) + 769:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 770:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); + 771:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 772:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 773:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 774:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get HSI Calibration value + 775:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note When HSITRIM is written, HSICAL is updated with the sum of + 776:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * HSITRIM and the factory trim value + 777:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration + 778:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + 779:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 780:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) + 781:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 782:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); + 783:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 784:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 785:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 786:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set HSI Calibration trimming + 787:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note user-programmable trimming value that is added to the HSICAL + 788:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note Default value is 16, which, when added to the HSICAL value, + 789:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * should trim the HSI to 16 MHz +/- 1 % + 790:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming + 791:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Value between Min_Data = 0x00 and Max_Data = 0x1F + 792:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 793:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 794:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) + 795:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 796:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); + 797:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 798:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 799:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 800:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get HSI Calibration trimming + 801:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming + 802:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + 803:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 804:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) + 805:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 806:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + 807:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 808:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 809:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 810:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 811:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 812:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 813:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 814:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI48 HSI48 + 815:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 816:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 817:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 818:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + ARM GAS /tmp/cctNXKqU.s page 26 + + + 819:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable HSI48 + 820:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Enable + 821:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 822:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 823:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI48_Enable(void) + 824:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 825:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR2, RCC_CR2_HSI48ON); + 826:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 827:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 828:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 829:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable HSI48 + 830:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Disable + 831:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 832:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 833:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI48_Disable(void) + 834:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 835:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON); + 836:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 837:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 838:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 839:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if HSI48 oscillator Ready + 840:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI48RDY LL_RCC_HSI48_IsReady + 841:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 842:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 843:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) + 844:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 845:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CR2, RCC_CR2_HSI48RDY) == (RCC_CR2_HSI48RDY)); + 846:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 847:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 848:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 849:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get HSI48 Calibration value + 850:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI48CAL LL_RCC_HSI48_GetCalibration + 851:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + 852:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 853:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) + 854:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 855:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48CAL) >> RCC_POSITION_HSI48CAL); + 856:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 857:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 858:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 859:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 860:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 861:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 862:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 863:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 864:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI14 HSI14 + 865:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 866:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 867:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 868:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 869:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable HSI14 + 870:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Enable + 871:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 872:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 873:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI14_Enable(void) + 874:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 875:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR2, RCC_CR2_HSI14ON); + ARM GAS /tmp/cctNXKqU.s page 27 + + + 876:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 877:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 878:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 879:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable HSI14 + 880:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Disable + 881:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 882:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 883:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI14_Disable(void) + 884:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 885:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON); + 886:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 887:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 888:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 889:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if HSI14 oscillator Ready + 890:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14RDY LL_RCC_HSI14_IsReady + 891:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). + 892:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 893:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI14_IsReady(void) + 894:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 895:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CR2, RCC_CR2_HSI14RDY) == (RCC_CR2_HSI14RDY)); + 896:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 897:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 898:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 899:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief ADC interface can turn on the HSI14 oscillator + 900:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_EnableADCControl + 901:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 902:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 903:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI14_EnableADCControl(void) + 904:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 905:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS); + 906:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 907:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 908:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 909:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief ADC interface can not turn on the HSI14 oscillator + 910:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_DisableADCControl + 911:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 912:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 913:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI14_DisableADCControl(void) + 914:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 915:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS); + 916:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 917:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 918:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 919:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set HSI14 Calibration trimming + 920:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note user-programmable trimming value that is added to the HSI14CAL + 921:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note Default value is 16, which, when added to the HSI14CAL value, + 922:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * should trim the HSI14 to 14 MHz +/- 1 % + 923:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_SetCalibTrimming + 924:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Value between Min_Data = 0x00 and Max_Data = 0xFF + 925:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 926:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 927:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI14_SetCalibTrimming(uint32_t Value) + 928:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 929:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, Value << RCC_POSITION_HSI14TRIM); + 930:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 931:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 932:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + ARM GAS /tmp/cctNXKqU.s page 28 + + + 933:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get HSI14 Calibration value + 934:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note When HSI14TRIM is written, HSI14CAL is updated with the sum of + 935:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * HSI14TRIM and the factory trim value + 936:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_GetCalibTrimming + 937:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + 938:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 939:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibTrimming(void) + 940:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 941:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14TRIM) >> RCC_POSITION_HSI14TRIM); + 942:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 943:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 944:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 945:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get HSI14 Calibration trimming + 946:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR2 HSI14CAL LL_RCC_HSI14_GetCalibration + 947:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + 948:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 949:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibration(void) + 950:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 951:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14CAL) >> RCC_POSITION_HSI14CAL); + 952:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 953:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 954:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 955:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} + 956:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 957:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 958:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSE LSE + 959:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ + 960:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 961:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 962:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 963:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable Low Speed External (LSE) crystal. + 964:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + 965:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 966:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 967:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Enable(void) + 968:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 969:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); + 970:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 971:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 972:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 973:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable Low Speed External (LSE) crystal. + 974:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + 975:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 976:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 977:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Disable(void) + 978:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 979:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); + 980:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 981:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 982:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 983:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable external clock source (LSE bypass). + 984:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + 985:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 986:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 987:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) + 988:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 989:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + ARM GAS /tmp/cctNXKqU.s page 29 + + + 990:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 991:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** + 992:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + 993:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable external clock source (LSE bypass). + 994:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + 995:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None + 996:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ + 997:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) + 998:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + 999:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +1000:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1001:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1002:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1003:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set LSE oscillator drive capability +1004:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note The oscillator is in Xtal mode when it is not in bypass mode. +1005:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability +1006:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param LSEDrive This parameter can be one of the following values: +1007:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_LOW +1008:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW +1009:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH +1010:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_HIGH +1011:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1012:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1013:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +1014:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1015:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +1016:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1017:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1018:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1019:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get LSE oscillator drive capability +1020:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability +1021:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1022:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_LOW +1023:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW +1024:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH +1025:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_HIGH +1026:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1027:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +1028:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1029:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +1030:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1031:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1032:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1033:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if LSE oscillator Ready +1034:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady +1035:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1036:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1037:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +1038:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1039:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); +1040:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1041:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1042:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1043:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} +1044:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1045:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1046:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSI LSI + ARM GAS /tmp/cctNXKqU.s page 30 + + +1047:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ +1048:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1049:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1050:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1051:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable LSI Oscillator +1052:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Enable +1053:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1054:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1055:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Enable(void) +1056:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1057:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_LSION); +1058:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1059:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1060:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1061:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable LSI Oscillator +1062:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Disable +1063:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1064:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1065:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Disable(void) +1066:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1067:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +1068:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1069:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1070:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1071:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if LSI is Ready +1072:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady +1073:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1074:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1075:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +1076:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1077:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +1078:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1079:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1080:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1081:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} +1082:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1083:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1084:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_System System +1085:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ +1086:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1087:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1088:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1089:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure the system clock source +1090:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR SW LL_RCC_SetSysClkSource +1091:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +1092:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI +1093:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE +1094:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL +1095:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI48 (*) +1096:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1097:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices +1098:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1099:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +1101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +1103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + ARM GAS /tmp/cctNXKqU.s page 31 + + +1104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get the system clock source +1107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR SWS LL_RCC_GetSysClkSource +1108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI +1110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE +1111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL +1112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*) +1113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices +1115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +1117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +1119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set AHB prescaler +1123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler +1124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +1125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 +1126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +1127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +1128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +1129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +1130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +1131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +1132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +1133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +1134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +1137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +1139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set APB1 prescaler +1143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler +1144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +1145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +1146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +1147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +1148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +1149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +1150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +1153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); +1155:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1156:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1157:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1158:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get AHB prescaler +1159:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler +1160:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: + ARM GAS /tmp/cctNXKqU.s page 32 + + +1161:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 +1162:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +1163:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +1164:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +1165:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +1166:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +1167:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +1168:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +1169:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +1170:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1171:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +1172:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +1174:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1175:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1176:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1177:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get APB1 prescaler +1178:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler +1179:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1180:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +1181:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +1182:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +1183:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +1184:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +1185:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1186:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +1187:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); +1189:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1190:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1191:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1192:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} +1193:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1194:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1195:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_MCO MCO +1196:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ +1197:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1198:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1199:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1200:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure MCOx +1201:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n +1202:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR MCOPRE LL_RCC_ConfigMCO\n +1203:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR PLLNODIV LL_RCC_ConfigMCO +1204:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param MCOxSource This parameter can be one of the following values: +1205:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK +1206:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSI14 +1207:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK +1208:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSI +1209:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSE +1210:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_LSI +1211:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_LSE +1212:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) +1213:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*) +1214:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 +1215:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1216:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices +1217:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param MCOxPrescaler This parameter can be one of the following values: + ARM GAS /tmp/cctNXKqU.s page 33 + + +1218:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_1 +1219:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_2 (*) +1220:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_4 (*) +1221:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_8 (*) +1222:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_16 (*) +1223:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_32 (*) +1224:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_64 (*) +1225:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_128 (*) +1226:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1227:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices +1228:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1229:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1230:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +1231:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1232:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_MCOPRE) +1233:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_CFGR_PLLNODIV) +1234:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPre +1235:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #else +1236:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); +1237:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_PLLNODIV */ +1238:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #else +1239:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); +1240:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* RCC_CFGR_MCOPRE */ +1241:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1242:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1243:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1244:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} +1245:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1246:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1247:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source +1248:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ +1249:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1250:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1251:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1252:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure USARTx clock source +1253:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n +1254:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n +1255:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR3 USART3SW LL_RCC_SetUSARTClockSource +1256:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param USARTxSource This parameter can be one of the following values: +1257:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 +1258:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK +1259:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE +1260:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI +1261:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) +1262:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) +1263:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) +1264:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) +1265:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) +1266:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) +1267:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) +1268:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) +1269:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1270:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices. +1271:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1272:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1273:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +1274:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { + ARM GAS /tmp/cctNXKqU.s page 34 + + +1275:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSou +1276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1277:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1278:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1279:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure I2Cx clock source +1280:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource +1281:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param I2CxSource This parameter can be one of the following values: +1282:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI +1283:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK +1284:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1285:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1286:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +1287:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1288:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, I2CxSource); +1289:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1290:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1291:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(CEC) +1292:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1293:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure CEC clock source +1294:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource +1295:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param CECxSource This parameter can be one of the following values: +1296:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 +1297:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE +1298:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1299:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1300:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource) +1301:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1302:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource); +1303:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1304:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* CEC */ +1305:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1306:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USB) +1307:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1308:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure USB clock source +1309:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR3 USBSW LL_RCC_SetUSBClockSource +1310:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param USBxSource This parameter can be one of the following values: +1311:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) +1312:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) +1313:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL +1314:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1315:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices. +1316:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1317:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1318:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +1319:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1320:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, USBxSource); +1321:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1322:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* USB */ +1323:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1325:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get USARTx clock source +1326:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n +1327:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n +1328:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR3 USART3SW LL_RCC_GetUSARTClockSource +1329:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param USARTx This parameter can be one of the following values: +1330:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE +1331:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE (*) + ARM GAS /tmp/cctNXKqU.s page 35 + + +1332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE (*) +1333:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1334:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices. +1335:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1336:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 +1337:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK +1338:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE +1339:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI +1340:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) +1341:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) +1342:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) +1343:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) +1344:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) +1345:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) +1346:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) +1347:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) +1348:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1349:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices. +1350:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1351:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +1352:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1353:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U)); +1354:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1355:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1356:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1357:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get I2Cx clock source +1358:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource +1359:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param I2Cx This parameter can be one of the following values: +1360:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE +1361:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1362:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI +1363:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK +1364:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1365:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +1366:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1367:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx)); +1368:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1369:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1370:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(CEC) +1371:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1372:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get CEC clock source +1373:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource +1374:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param CECx This parameter can be one of the following values: +1375:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE +1376:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1377:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 +1378:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE +1379:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1380:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) +1381:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1382:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR3, CECx)); +1383:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1384:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* CEC */ +1385:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1386:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(USB) +1387:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1388:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get USBx clock source + ARM GAS /tmp/cctNXKqU.s page 36 + + +1389:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR3 USBSW LL_RCC_GetUSBClockSource +1390:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param USBx This parameter can be one of the following values: +1391:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE +1392:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1393:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) +1394:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) +1395:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL +1396:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1397:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices. +1398:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1399:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +1400:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1401:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR3, USBx)); +1402:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1403:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #endif /* USB */ +1404:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1405:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1406:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} +1407:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1408:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1409:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_RTC RTC +1410:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ +1411:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1412:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1413:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1414:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Set RTC Clock Source +1415:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note Once the RTC clock source has been selected, it cannot be changed any more unless +1416:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * the Backup domain is reset. The BDRST bit can be used to reset them. +1417:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource +1418:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +1419:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE +1420:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE +1421:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI +1422:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 +1423:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1424:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1425:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +1426:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1427:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +1428:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1429:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1430:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1431:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Get RTC Clock Source +1432:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource +1433:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1434:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE +1435:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE +1436:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI +1437:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 +1438:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1439:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +1440:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1441:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +1442:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1443:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1444:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1445:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable RTC + ARM GAS /tmp/cctNXKqU.s page 37 + + +1446:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR RTCEN LL_RCC_EnableRTC +1447:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1448:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1449:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_EnableRTC(void) +1450:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1451:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +1452:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1453:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1454:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1455:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable RTC +1456:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR RTCEN LL_RCC_DisableRTC +1457:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1458:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1459:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_DisableRTC(void) +1460:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1461:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +1462:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1463:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1464:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1465:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if RTC has been enabled or not +1466:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC +1467:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1468:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1469:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +1470:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1471:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); +1472:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1473:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1474:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1475:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Force the Backup domain reset +1476:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset +1477:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1478:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1479:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +1480:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1481:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +1482:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1483:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1484:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1485:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Release the Backup domain reset +1486:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset +1487:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1488:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1489:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +1490:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1491:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +1492:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1493:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1494:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1495:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @} +1496:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1497:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1498:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLL PLL +1499:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @{ +1500:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1501:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1502:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** + ARM GAS /tmp/cctNXKqU.s page 38 + + +1503:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Enable PLL +1504:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR PLLON LL_RCC_PLL_Enable +1505:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1506:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1507:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Enable(void) +1508:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1509:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_PLLON); +1510:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1511:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1512:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1513:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Disable PLL +1514:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @note Cannot be disabled if the PLL clock is used as the system clock +1515:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR PLLON LL_RCC_PLL_Disable +1516:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1517:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1518:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Disable(void) +1519:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1520:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +1521:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1522:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1523:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1524:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Check if PLL Ready +1525:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady +1526:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1527:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1528:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +1529:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1530:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); + 79 .loc 2 1530 0 + 80 0000 034B ldr r3, .L6 + 81 0002 1B68 ldr r3, [r3] + 82 .LBE53: + 83 .LBE52: + 533:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 534:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 535:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Check if PLL is busy*/ + 536:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if (LL_RCC_PLL_IsReady() != 0U) + 84 .loc 1 536 0 + 85 0004 9B01 lsls r3, r3, #6 + 86 0006 01D5 bpl .L5 + 537:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 538:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* PLL configuration cannot be modified */ + 539:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** status = ERROR; + 87 .loc 1 539 0 + 88 0008 0120 movs r0, #1 + 89 .L3: + 90 .LVL7: + 540:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 541:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 542:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** return status; + 543:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 91 .loc 1 543 0 + 92 @ sp needed + 93 000a 7047 bx lr + 94 .LVL8: + 95 .L5: + 533:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + ARM GAS /tmp/cctNXKqU.s page 39 + + + 96 .loc 1 533 0 + 97 000c 0020 movs r0, #0 + 98 000e FCE7 b .L3 + 99 .L7: + 100 .align 2 + 101 .L6: + 102 0010 00100240 .word 1073876992 + 103 .cfi_endproc + 104 .LFE194: + 106 .section .text.LL_Init1msTick,"ax",%progbits + 107 .align 1 + 108 .global LL_Init1msTick + 109 .syntax unified + 110 .code 16 + 111 .thumb_func + 112 .fpu softvfp + 114 LL_Init1msTick: + 115 .LFB186: + 143:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Use frequency provided in argument */ + 116 .loc 1 143 0 + 117 .cfi_startproc + 118 @ args = 0, pretend = 0, frame = 0 + 119 @ frame_needed = 0, uses_anonymous_args = 0 + 120 .LVL9: + 121 0000 10B5 push {r4, lr} + 122 .LCFI1: + 123 .cfi_def_cfa_offset 8 + 124 .cfi_offset 4, -8 + 125 .cfi_offset 14, -4 + 126 .LVL10: + 127 .LBB54: + 128 .LBB55: + 129 .file 3 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h" + 1:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @file stm32f0xx_ll_utils.h + 4:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @brief Header file of UTILS LL module. + 6:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** @verbatim + 7:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** ============================================================================== + 8:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** ##### How to use this driver ##### + 9:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** ============================================================================== + 10:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** [..] + 11:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** The LL UTILS driver contains a set of generic APIs that can be + 12:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** used by user: + 13:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** (+) Device electronic signature + 14:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** (+) Timing functions + 15:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** (+) PLL configuration functions + 16:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 17:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** @endverbatim + 18:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** ****************************************************************************** + 19:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @attention + 20:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * + 21:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** *

© Copyright (c) 2016 STMicroelectronics. + 22:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * All rights reserved.

+ 23:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * + 24:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * This software component is licensed by ST under BSD 3-Clause license, + ARM GAS /tmp/cctNXKqU.s page 40 + + + 25:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * the "License"; You may not use this file except in compliance with the + 26:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * License. You may obtain a copy of the License at: + 27:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * opensource.org/licenses/BSD-3-Clause + 28:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * + 29:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** ****************************************************************************** + 30:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 31:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 32:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 33:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** #ifndef __STM32F0xx_LL_UTILS_H + 34:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** #define __STM32F0xx_LL_UTILS_H + 35:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 36:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** #ifdef __cplusplus + 37:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** extern "C" { + 38:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** #endif + 39:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 40:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /* Includes ------------------------------------------------------------------*/ + 41:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** #include "stm32f0xx.h" + 42:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 43:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** @addtogroup STM32F0xx_LL_Driver + 44:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @{ + 45:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 46:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 47:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** @defgroup UTILS_LL UTILS + 48:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @{ + 49:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 50:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 51:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /* Private types -------------------------------------------------------------*/ + 52:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /* Private variables ---------------------------------------------------------*/ + 53:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 54:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /* Private constants ---------------------------------------------------------*/ + 55:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + 56:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @{ + 57:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 58:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 59:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /* Max delay can be used in LL_mDelay */ + 60:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** #define LL_MAX_DELAY 0xFFFFFFFFU + 61:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 62:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** + 63:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @brief Unique device ID register base address + 64:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 65:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** #define UID_BASE_ADDRESS UID_BASE + 66:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 67:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** + 68:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @brief Flash size data register base address + 69:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 70:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + 71:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 72:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** + 73:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @} + 74:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 75:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 76:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /* Private macros ------------------------------------------------------------*/ + 77:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + 78:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @{ + 79:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 80:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** + 81:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @} + ARM GAS /tmp/cctNXKqU.s page 41 + + + 82:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 83:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /* Exported types ------------------------------------------------------------*/ + 84:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + 85:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @{ + 86:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 87:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** + 88:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @brief UTILS PLL structure definition + 89:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 90:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** typedef struct + 91:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** { + 92:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock. + 93:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** This parameter can be a value of @ref RCC_LL_EC_PLL_MUL + 94:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 95:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** This feature can be modified afterwards using unitary function + 96:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + 97:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 98:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + 99:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock. + 100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV + 101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** This feature can be modified afterwards using unitary function + 103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + 104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** #else + 105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source. + 106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV + 107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** This feature can be modified afterwards using unitary function + 109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + 110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + 111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** } LL_UTILS_PLLInitTypeDef; + 112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** + 114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @brief UTILS System, AHB and APB buses clock configuration structure definition + 115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** typedef struct + 117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** { + 118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the + 119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + 120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** This feature can be modified afterwards using unitary functi + 122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** @ref LL_RCC_SetAHBPrescaler(). */ + 123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from t + 125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + 126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** This feature can be modified afterwards using unitary functi + 128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** @ref LL_RCC_SetAPB1Prescaler(). */ + 129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** } LL_UTILS_ClkInitTypeDef; + 130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** + 132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @} + 133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /* Exported constants --------------------------------------------------------*/ + 136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + 137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @{ + 138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + ARM GAS /tmp/cctNXKqU.s page 42 + + + 139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + 141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @{ + 142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled + 144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled + 145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** + 146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @} + 147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** + 150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @} + 151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /* Exported macro ------------------------------------------------------------*/ + 154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 155:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /* Exported functions --------------------------------------------------------*/ + 156:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + 157:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @{ + 158:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 159:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 160:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + 161:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @{ + 162:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 163:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 164:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** + 165:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + 166:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format + 167:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 168:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetUID_Word0(void) + 169:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** { + 170:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); + 171:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** } + 172:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** + 174:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + 175:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) + 176:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 177:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetUID_Word1(void) + 178:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** { + 179:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); + 180:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** } + 181:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 182:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** + 183:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + 184:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] + 185:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 186:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetUID_Word2(void) + 187:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** { + 188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); + 189:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** } + 190:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 191:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** + 192:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @brief Get Flash memory size + 193:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @note This bitfield indicates the size of the device Flash memory expressed in + 194:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + 195:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @retval FLASH_SIZE[15:0]: Flash memory size + ARM GAS /tmp/cctNXKqU.s page 43 + + + 196:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 197:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetFlashSize(void) + 198:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** { + 199:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); + 200:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** } + 201:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 202:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 203:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** + 204:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @} + 205:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 206:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 207:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** @defgroup UTILS_LL_EF_DELAY DELAY + 208:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @{ + 209:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 210:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** + 211:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /** + 212:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @brief This function configures the Cortex-M SysTick source of the time base. + 213:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + 214:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @note When a RTOS is used, it is recommended to avoid changing the SysTick + 215:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * configuration by calling this function, for a delay use rather osDelay RTOS service. + 216:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @param Ticks Number of ticks + 217:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** * @retval None + 218:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** */ + 219:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) + 220:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** { + 221:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** /* Configure the SysTick to have interrupt in 1ms time base */ + 222:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + 130 .loc 3 222 0 + 131 0002 FA21 movs r1, #250 + 132 0004 8900 lsls r1, r1, #2 + 133 0006 FFF7FEFF bl __aeabi_uidiv + 134 .LVL11: + 135 000a 0138 subs r0, r0, #1 + 136 000c 034B ldr r3, .L9 + 137 000e 5860 str r0, [r3, #4] + 223:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 138 .loc 3 223 0 + 139 0010 0022 movs r2, #0 + 140 0012 9A60 str r2, [r3, #8] + 224:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h **** SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 141 .loc 3 224 0 + 142 0014 0532 adds r2, r2, #5 + 143 0016 1A60 str r2, [r3] + 144 .LVL12: + 145 .LBE55: + 146 .LBE54: + 146:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 147 .loc 1 146 0 + 148 @ sp needed + 149 0018 10BD pop {r4, pc} + 150 .L10: + 151 001a C046 .align 2 + 152 .L9: + 153 001c 10E000E0 .word -536813552 + 154 .cfi_endproc + 155 .LFE186: + 157 .section .text.LL_mDelay,"ax",%progbits + ARM GAS /tmp/cctNXKqU.s page 44 + + + 158 .align 1 + 159 .global LL_mDelay + 160 .syntax unified + 161 .code 16 + 162 .thumb_func + 163 .fpu softvfp + 165 LL_mDelay: + 166 .LFB187: + 159:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + 167 .loc 1 159 0 + 168 .cfi_startproc + 169 @ args = 0, pretend = 0, frame = 8 + 170 @ frame_needed = 0, uses_anonymous_args = 0 + 171 @ link register save eliminated. + 172 .LVL13: + 173 0000 82B0 sub sp, sp, #8 + 174 .LCFI2: + 175 .cfi_def_cfa_offset 8 + 160:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Add this code to indicate that local variable is not used */ + 176 .loc 1 160 0 + 177 0002 084B ldr r3, .L17 + 178 0004 1B68 ldr r3, [r3] + 179 0006 0193 str r3, [sp, #4] + 162:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 180 .loc 1 162 0 + 181 0008 019B ldr r3, [sp, #4] + 165:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 182 .loc 1 165 0 + 183 000a 431C adds r3, r0, #1 + 184 000c 00D0 beq .L14 + 167:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 185 .loc 1 167 0 + 186 000e 0130 adds r0, r0, #1 + 187 .LVL14: + 188 .L14: + 170:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 189 .loc 1 170 0 + 190 0010 0028 cmp r0, #0 + 191 0012 05D0 beq .L16 + 172:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 192 .loc 1 172 0 + 193 0014 034B ldr r3, .L17 + 194 0016 1B68 ldr r3, [r3] + 195 0018 DB03 lsls r3, r3, #15 + 196 001a F9D5 bpl .L14 + 174:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 197 .loc 1 174 0 + 198 001c 0138 subs r0, r0, #1 + 199 .LVL15: + 200 001e F7E7 b .L14 + 201 .L16: + 177:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 202 .loc 1 177 0 + 203 0020 02B0 add sp, sp, #8 + 204 @ sp needed + 205 0022 7047 bx lr + 206 .L18: + ARM GAS /tmp/cctNXKqU.s page 45 + + + 207 .align 2 + 208 .L17: + 209 0024 10E000E0 .word -536813552 + 210 .cfi_endproc + 211 .LFE187: + 213 .section .text.LL_SetSystemCoreClock,"ax",%progbits + 214 .align 1 + 215 .global LL_SetSystemCoreClock + 216 .syntax unified + 217 .code 16 + 218 .thumb_func + 219 .fpu softvfp + 221 LL_SetSystemCoreClock: + 222 .LFB188: + 215:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* HCLK clock frequency */ + 223 .loc 1 215 0 + 224 .cfi_startproc + 225 @ args = 0, pretend = 0, frame = 0 + 226 @ frame_needed = 0, uses_anonymous_args = 0 + 227 @ link register save eliminated. + 228 .LVL16: + 217:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 229 .loc 1 217 0 + 230 0000 014B ldr r3, .L20 + 231 0002 1860 str r0, [r3] + 218:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 232 .loc 1 218 0 + 233 @ sp needed + 234 0004 7047 bx lr + 235 .L21: + 236 0006 C046 .align 2 + 237 .L20: + 238 0008 00000000 .word SystemCoreClock + 239 .cfi_endproc + 240 .LFE188: + 242 .section .text.LL_SetFlashLatency,"ax",%progbits + 243 .align 1 + 244 .global LL_SetFlashLatency + 245 .syntax unified + 246 .code 16 + 247 .thumb_func + 248 .fpu softvfp + 250 LL_SetFlashLatency: + 251 .LFB189: + 230:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** uint32_t timeout; + 252 .loc 1 230 0 + 253 .cfi_startproc + 254 @ args = 0, pretend = 0, frame = 0 + 255 @ frame_needed = 0, uses_anonymous_args = 0 + 256 @ link register save eliminated. + 257 .LVL17: + 237:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 258 .loc 1 237 0 + 259 0000 0028 cmp r0, #0 + 260 0002 19D0 beq .L27 + 243:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 261 .loc 1 243 0 + ARM GAS /tmp/cctNXKqU.s page 46 + + + 262 0004 0E4B ldr r3, .L30 + 263 0006 9842 cmp r0, r3 + 264 0008 14D9 bls .L28 + 246:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 265 .loc 1 246 0 + 266 000a 0121 movs r1, #1 + 267 .L24: + 268 .LVL18: + 269 .LBB56: + 270 .LBB57: + 271 .file 4 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h" + 1:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 2:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** ****************************************************************************** + 3:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @file stm32f0xx_ll_system.h + 4:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @author MCD Application Team + 5:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Header file of SYSTEM LL module. + 6:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** @verbatim + 7:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** ============================================================================== + 8:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** ##### How to use this driver ##### + 9:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** ============================================================================== + 10:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** [..] + 11:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** The LL SYSTEM driver contains a set of generic APIs that can be + 12:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** used by user: + 13:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** (+) Some of the FLASH features need to be handled in the SYSTEM file. + 14:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** (+) Access to DBGCMU registers + 15:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** (+) Access to SYSCFG registers + 16:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 17:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** @endverbatim + 18:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** ****************************************************************************** + 19:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @attention + 20:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + 21:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** *

© Copyright (c) 2016 STMicroelectronics. + 22:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * All rights reserved.

+ 23:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + 24:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * This software component is licensed by ST under BSD 3-Clause license, + 25:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * the "License"; You may not use this file except in compliance with the + 26:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * License. You may obtain a copy of the License at: + 27:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * opensource.org/licenses/BSD-3-Clause + 28:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + 29:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** ****************************************************************************** + 30:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 31:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 32:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 33:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #ifndef __STM32F0xx_LL_SYSTEM_H + 34:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define __STM32F0xx_LL_SYSTEM_H + 35:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 36:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #ifdef __cplusplus + 37:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** extern "C" { + 38:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif + 39:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 40:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Includes ------------------------------------------------------------------*/ + 41:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #include "stm32f0xx.h" + 42:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 43:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @addtogroup STM32F0xx_LL_Driver + 44:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 45:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 46:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + ARM GAS /tmp/cctNXKqU.s page 47 + + + 47:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + 48:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 49:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL SYSTEM + 50:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 51:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 52:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 53:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Private types -------------------------------------------------------------*/ + 54:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Private variables ---------------------------------------------------------*/ + 55:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 56:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Private constants ---------------------------------------------------------*/ + 57:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + 58:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 59:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 60:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 61:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 62:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 63:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 64:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 65:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Private macros ------------------------------------------------------------*/ + 66:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 67:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Exported types ------------------------------------------------------------*/ + 68:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Exported constants --------------------------------------------------------*/ + 69:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + 70:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 71:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 72:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 73:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Remap + 74:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 75:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 76:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000U /*!< + 77:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< + 78:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< + 79:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 80:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 81:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 82:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 83:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_IR_MOD) + 84:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation + 85:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 86:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 87:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< Timer1 + 88:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< USART1 + 89:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< USART4 + 90:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 91:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 92:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 93:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 94:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_IR_MOD */ + 95:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 96:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) || defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) || defined(SYS + 97:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_USART1TX_RMP SYSCFG USART DMA Remap + 98:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 99:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_USART1TX_DMA_RMP) + 101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_USART1TX_RMP_DMA1CH2 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) | (uint32_t)0x000 + 102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_USART1TX_RMP_DMA1CH4 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) | SYSCFG_CFGR1_US + 103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_USART1TX_DMA_RMP*/ + ARM GAS /tmp/cctNXKqU.s page 48 + + + 104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_USART1RX_DMA_RMP) + 105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_USART1RX_RMP_DMA1CH3 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) | (uint32_t)0x000 + 106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_USART1RX_RMP_DMA1CH5 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) | SYSCFG_CFGR1_US + 107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_USART1RX_DMA_RMP*/ + 108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_USART2_DMA_RMP) + 109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_USART2_RMP_DMA1CH54 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) | (uint32_t)0x00000 + 110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_USART2_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) | SYSCFG_CFGR1_USAR + 111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_USART2_DMA_RMP*/ + 112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_USART3_DMA_RMP) + 113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_USART3_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) | (uint32_t)0x00000 + 114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_USART3_RMP_DMA1CH32 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) | SYSCFG_CFGR1_USAR + 115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_USART3_DMA_RMP */ + 116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP || SYSCFG_CFGR1_USART1RX_DMA_RMP || SYSCFG_CFGR1_USART2_DMA + 120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_SPI2_DMA_RMP) + 122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_SPI2_RMP_DMA1 SYSCFG SPI2 DMA Remap + 123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_SPI2_RMP_DMA1_CH45 (uint32_t)0x00000000U /*!< SPI2_RX and SPI2_TX DMA + 126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_SPI2_RMP_DMA1_CH67 SYSCFG_CFGR1_SPI2_DMA_RMP /*!< SPI2_RX and SPI2_TX DMA + 127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_SPI2_DMA_RMP*/ + 132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_I2C1_DMA_RMP) + 134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_I2C1_RMP_DMA1 SYSCFG I2C1 DMA Remap + 135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C1_RMP_DMA1_CH32 (uint32_t)0x00000000U /*!< I2C1_RX and I2C1_TX DMA + 138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C1_RMP_DMA1_CH76 SYSCFG_CFGR1_I2C1_DMA_RMP /*!< I2C1_RX and I2C1_TX DMA + 139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_I2C1_DMA_RMP*/ + 144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_ADC_DMA_RMP) + 146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_ADC1_RMP_DMA1 SYSCFG ADC1 DMA Remap + 147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_ADC1_RMP_DMA1_CH1 (uint32_t)0x00000000U /*!< ADC DMA request mapped on + 150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_ADC1_RMP_DMA1_CH2 SYSCFG_CFGR1_ADC_DMA_RMP /*!< ADC DMA request mapped on + 151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 155:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_ADC_DMA_RMP */ + 156:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 157:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) || defined(SYSCFG_CFGR1_TIM17_DMA_RMP) || defined(SYSCFG_CF + 158:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_TIM16_RMP_DMA1 SYSCFG TIM DMA Remap + 159:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 160:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + ARM GAS /tmp/cctNXKqU.s page 49 + + + 161:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) + 162:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_TIM16_DMA_RMP2) + 163:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM16_RMP_DMA1_CH3 (((SYSCFG_CFGR1_TIM16_DMA_RMP | SYSCFG_CFGR1_TIM16_DMA_R + 164:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM16_RMP_DMA1_CH4 (((SYSCFG_CFGR1_TIM16_DMA_RMP | SYSCFG_CFGR1_TIM16_DMA_R + 165:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP2 >> 8U) | SYSCFG_CFGR1_TIM1 + 166:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #else + 167:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) | (uint32_t)0x000000 + 168:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM16_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM16 + 169:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_TIM16_DMA_RMP2 */ + 170:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_TIM16_DMA_RMP */ + 171:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_TIM17_DMA_RMP) + 172:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_TIM17_DMA_RMP2) + 173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM17_RMP_DMA1_CH1 (((SYSCFG_CFGR1_TIM17_DMA_RMP | SYSCFG_CFGR1_TIM17_DMA_R + 174:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM17_RMP_DMA1_CH2 (((SYSCFG_CFGR1_TIM17_DMA_RMP | SYSCFG_CFGR1_TIM17_DMA_R + 175:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP2 >> 8U) | SYSCFG_CFGR1_TIM1 + 176:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #else + 177:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) | (uint32_t)0x000000 + 178:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM17_RMP_DMA1_CH2 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM17 + 179:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_TIM17_DMA_RMP2 */ + 180:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_TIM17_DMA_RMP */ + 181:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_TIM1_DMA_RMP) + 182:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM1_RMP_DMA1_CH234 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) | (uint32_t)0x0000000 + 183:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM1_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM1_D + 184:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_TIM1_DMA_RMP*/ + 185:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_TIM2_DMA_RMP) + 186:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM2_RMP_DMA1_CH34 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) | (uint32_t)0x0000000 + 187:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM2_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM2_D + 188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_TIM2_DMA_RMP*/ + 189:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined (SYSCFG_CFGR1_TIM3_DMA_RMP) + 190:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM3_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) | (uint32_t)0x0000000 + 191:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIM3_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM3_D + 192:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_TIM3_DMA_RMP*/ + 193:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 194:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 195:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 196:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 197:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_TIM16_DMA_RMP || SYSCFG_CFGR1_TIM17_DMA_RMP || SYSCFG_CFGR1_TIM1_DMA_RMP || + 198:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 199:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + 200:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 201:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 202:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< I2C PB6 Fast mode plus */ + 203:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< I2C PB7 Fast mode plus */ + 204:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< I2C PB8 Fast mode plus */ + 205:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< I2C PB9 Fast mode plus */ + 206:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) + 207:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on + 208:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_I2C_FMP_I2C1*/ + 209:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) + 210:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable I2C2 Fast mode plu + 211:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_I2C_FMP_I2C2*/ + 212:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_I2C_FMP_PA9) + 213:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on P + 214:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_I2C_FMP_PA9*/ + 215:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_I2C_FMP_PA10) + 216:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on + 217:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR1_I2C_FMP_PA10*/ + ARM GAS /tmp/cctNXKqU.s page 50 + + + 218:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 219:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 220:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 221:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 222:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT + 223:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 224:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 225:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /*!< EXTI PORT A */ + 226:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /*!< EXTI PORT B */ + 227:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /*!< EXTI PORT C */ + 228:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(GPIOD_BASE) + 229:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /*!< EXTI PORT D */ + 230:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*GPIOD_BASE*/ + 231:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(GPIOE_BASE) + 232:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /*!< EXTI PORT E */ + 233:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*GPIOE_BASE*/ + 234:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /*!< EXTI PORT F */ + 235:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 236:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 237:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 238:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 239:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE + 240:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 241:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 242:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0U << 16U | 0U) /*!< EXTI_POSITION_0 | EXTI + 243:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(4U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTI + 244:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(8U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTI + 245:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(12U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTI + 246:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0U << 16U | 1U) /*!< EXTI_POSITION_0 | EXTI + 247:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(4U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTI + 248:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(8U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTI + 249:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(12U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTI + 250:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0U << 16U | 2U) /*!< EXTI_POSITION_0 | EXTI + 251:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(4U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTI + 252:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(8U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTI + 253:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(12U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTI + 254:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0U << 16U | 3U) /*!< EXTI_POSITION_0 | EXTI + 255:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(4U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTI + 256:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(8U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTI + 257:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(12U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTI + 258:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 259:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 260:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 261:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 262:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + 263:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 264:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 265:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR2_PVD_LOCK) + 266:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD co + 267:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** with TIM1/15/16U/17 Break In + 268:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** the PVDE and PLS bits of the + 269:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR2_PVD_LOCK*/ + 270:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks t + 271:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** with Break Input of + 272:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LO + 273:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** CortexM0 with Break Inpu + 274:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + ARM GAS /tmp/cctNXKqU.s page 51 + + + 275:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 277:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 278:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + 279:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 280:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 281:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) + 282:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter st + 283:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*DBGMCU_APB1_FZ_DBG_TIM2_STOP*/ + 284:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter st + 285:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) + 286:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter st + 287:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*DBGMCU_APB1_FZ_DBG_TIM6_STOP*/ + 288:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) + 289:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter st + 290:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*DBGMCU_APB1_FZ_DBG_TIM7_STOP*/ + 291:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter s + 292:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Calendar fr + 293:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Wa + 294:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independe + 295:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS ti + 296:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) + 297:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /*!< CAN debug stopp + 298:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*DBGMCU_APB1_FZ_DBG_CAN_STOP*/ + 299:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 300:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 301:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 302:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 303:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_APB1 GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP + 304:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 305:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 306:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter st + 307:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) + 308:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP2_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /*!< TIM15 counter s + 309:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*DBGMCU_APB2_FZ_DBG_TIM15_STOP*/ + 310:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /*!< TIM16 counter s + 311:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /*!< TIM17 counter s + 312:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 313:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 314:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 315:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 316:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + 317:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 318:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 319:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ + 320:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ + 321:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 322:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 323:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 325:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 326:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} + 327:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 328:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 329:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Exported macro ------------------------------------------------------------*/ + 330:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 331:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /* Exported functions --------------------------------------------------------*/ + ARM GAS /tmp/cctNXKqU.s page 52 + + + 332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + 333:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 334:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 335:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 336:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + 337:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ + 338:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 339:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 340:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 341:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set memory mapping at address 0x00000000 + 342:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory + 343:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Memory This parameter can be one of the following values: + 344:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_FLASH + 345:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + 346:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_SRAM + 347:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 348:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 349:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) + 350:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 351:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory); + 352:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 353:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 354:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 355:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Get memory mapping at address 0x00000000 + 356:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory + 357:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval Returned value can be one of the following values: + 358:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_FLASH + 359:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + 360:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_SRAM + 361:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 362:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) + 363:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 364:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)); + 365:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 366:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 367:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_IR_MOD) + 368:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 369:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set IR Modulation Envelope signal source. + 370:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal + 371:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Source This parameter can be one of the following values: + 372:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_IR_MOD_TIM16 + 373:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_IR_MOD_USART1 + 374:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_IR_MOD_USART4 + 375:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 376:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 377:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source) + 378:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 379:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source); + 380:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 381:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 382:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 383:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Get IR Modulation Envelope signal source. + 384:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal + 385:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval Returned value can be one of the following values: + 386:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_IR_MOD_TIM16 + 387:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_IR_MOD_USART1 + 388:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_IR_MOD_USART4 + ARM GAS /tmp/cctNXKqU.s page 53 + + + 389:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 390:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void) + 391:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 392:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD)); + 393:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 394:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_IR_MOD */ + 395:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 396:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) || defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) || defined(SYS + 397:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 398:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set DMA request remapping bits for USART + 399:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 USART1TX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n + 400:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 USART1RX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n + 401:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 USART2_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n + 402:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 USART3_DMA_RMP LL_SYSCFG_SetRemapDMA_USART + 403:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Remap This parameter can be one of the following values: + 404:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH2 (*) + 405:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH4 (*) + 406:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH3 (*) + 407:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH5 (*) + 408:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH54 (*) + 409:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH67 (*) + 410:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH67 (*) + 411:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH32 (*) + 412:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + 413:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices. + 414:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 415:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 416:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_USART(uint32_t Remap) + 417:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 418:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U)); + 419:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 420:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP || SYSCFG_CFGR1_USART1RX_DMA_RMP || SYSCFG_CFGR1_USART2_DMA + 421:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 422:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_SPI2_DMA_RMP) + 423:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 424:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set DMA request remapping bits for SPI + 425:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 SPI2_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI + 426:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Remap This parameter can be one of the following values: + 427:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH45 + 428:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH67 + 429:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 430:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 431:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap) + 432:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 433:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_SPI2_DMA_RMP, Remap); + 434:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 435:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_SPI2_DMA_RMP */ + 436:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 437:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_I2C1_DMA_RMP) + 438:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 439:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set DMA request remapping bits for I2C + 440:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 I2C1_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C + 441:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Remap This parameter can be one of the following values: + 442:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH32 + 443:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH76 + 444:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 445:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + ARM GAS /tmp/cctNXKqU.s page 54 + + + 446:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap) + 447:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 448:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_I2C1_DMA_RMP, Remap); + 449:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 450:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_I2C1_DMA_RMP */ + 451:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 452:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_ADC_DMA_RMP) + 453:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 454:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set DMA request remapping bits for ADC + 455:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 ADC_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC + 456:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Remap This parameter can be one of the following values: + 457:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH1 + 458:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH2 + 459:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 460:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 461:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap) + 462:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 463:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ADC_DMA_RMP, Remap); + 464:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 465:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_ADC_DMA_RMP */ + 466:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 467:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) || defined(SYSCFG_CFGR1_TIM17_DMA_RMP) || defined(SYSCFG_CF + 468:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 469:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set DMA request remapping bits for TIM + 470:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + 471:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + 472:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 TIM16_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n + 473:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 TIM17_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n + 474:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 TIM1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + 475:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 TIM2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + 476:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 TIM3_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM + 477:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Remap This parameter can be one of the following values: + 478:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 (*) + 479:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH4 (*) + 480:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6 (*) + 481:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 (*) + 482:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH2 (*) + 483:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7 (*) + 484:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH234 (*) + 485:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH6 (*) + 486:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH34 (*) + 487:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH7 (*) + 488:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH4 (*) + 489:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH6 (*) + 490:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + 491:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices. + 492:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 493:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 494:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap) + 495:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 496:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U)); + 497:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 498:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_TIM16_DMA_RMP || SYSCFG_CFGR1_TIM17_DMA_RMP || SYSCFG_CFGR1_TIM1_DMA_RMP || + 499:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 500:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR1_PA11_PA12_RMP) + 501:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 502:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Enable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either + ARM GAS /tmp/cctNXKqU.s page 55 + + + 503:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * PA9/10 or PA11/12 pin pair on small pin-count packages) + 504:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_EnablePinRemap + 505:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 506:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 507:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_EnablePinRemap(void) + 508:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 509:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP); + 510:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 511:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 512:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 513:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Disable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either + 514:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * PA9/10 or PA11/12 pin pair on small pin-count packages) + 515:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_DisablePinRemap + 516:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 517:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 518:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_DisablePinRemap(void) + 519:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 520:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP); + 521:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 522:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ + 523:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 524:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 525:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Enable the I2C fast mode plus driving capability. + 526:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n + 527:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n + 528:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n + 529:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n + 530:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n + 531:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus\n + 532:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n + 533:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus + 534:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param ConfigFastModePlus This parameter can be a combination of the following values: + 535:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + 536:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + 537:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + 538:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + 539:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*) + 540:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + 541:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*) + 542:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*) + 543:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + 544:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices + 545:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 546:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 547:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) + 548:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 549:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); + 550:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 551:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 552:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 553:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Disable the I2C fast mode plus driving capability. + 554:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n + 555:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n + 556:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n + 557:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n + 558:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n + 559:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus\n + ARM GAS /tmp/cctNXKqU.s page 56 + + + 560:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n + 561:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus + 562:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param ConfigFastModePlus This parameter can be a combination of the following values: + 563:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + 564:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + 565:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + 566:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + 567:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*) + 568:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + 569:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*) + 570:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*) + 571:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + 572:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices + 573:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 574:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 575:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) + 576:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 577:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); + 578:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 579:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 580:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 581:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Configure source input for the EXTI external interrupt. + 582:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n + 583:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n + 584:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n + 585:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n + 586:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n + 587:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n + 588:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n + 589:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n + 590:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n + 591:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n + 592:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n + 593:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n + 594:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n + 595:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n + 596:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n + 597:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource + 598:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Port This parameter can be one of the following values: + 599:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTA + 600:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTB + 601:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTC + 602:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTD (*) + 603:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + 604:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTF + 605:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + 606:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices + 607:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Line This parameter can be one of the following values: + 608:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE0 + 609:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE1 + 610:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE2 + 611:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE3 + 612:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE4 + 613:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE5 + 614:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE6 + 615:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE7 + 616:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE8 + ARM GAS /tmp/cctNXKqU.s page 57 + + + 617:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE9 + 618:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE10 + 619:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE11 + 620:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE12 + 621:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE13 + 622:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE14 + 623:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE15 + 624:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None + 625:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 626:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) + 627:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 628:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], SYSCFG_EXTICR1_EXTI0 << (Line >> 16), Port << (Line >> 16 + 629:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 630:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 631:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 632:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Get the configured defined for specific EXTI Line + 633:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n + 634:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n + 635:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n + 636:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n + 637:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n + 638:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n + 639:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n + 640:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n + 641:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n + 642:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n + 643:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n + 644:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n + 645:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n + 646:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n + 647:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n + 648:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource + 649:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Line This parameter can be one of the following values: + 650:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE0 + 651:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE1 + 652:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE2 + 653:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE3 + 654:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE4 + 655:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE5 + 656:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE6 + 657:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE7 + 658:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE8 + 659:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE9 + 660:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE10 + 661:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE11 + 662:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE12 + 663:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE13 + 664:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE14 + 665:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE15 + 666:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval Returned value can be one of the following values: + 667:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTA + 668:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTB + 669:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTC + 670:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTD (*) + 671:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + 672:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTF + 673:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * + ARM GAS /tmp/cctNXKqU.s page 58 + + + 674:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices + 675:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 676:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) + 677:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 678:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16))) > + 679:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 680:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 681:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE0_SR_EWDG) + 682:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 683:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Window watchdog interrupt occurred or not. + 684:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG + 685:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 686:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 687:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void) + 688:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 689:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG)); + 690:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 691:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE0_SR_EWDG */ + 692:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 693:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE1_SR_PVDOUT) + 694:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 695:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if PVD supply monitoring interrupt occurred or not (EXTI line 16). + 696:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE1 SR_PVDOUT LL_SYSCFG_IsActiveFlag_PVDOUT + 697:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 698:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 699:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void) + 700:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 701:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT)); + 702:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 703:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE1_SR_PVDOUT */ + 704:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 705:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE1_SR_VDDIO2) + 706:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 707:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if VDDIO2 supply monitoring interrupt occurred or not (EXTI line 31). + 708:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE1 SR_VDDIO2 LL_SYSCFG_IsActiveFlag_VDDIO2 + 709:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 710:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 711:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VDDIO2(void) + 712:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 713:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_VDDIO2) == (SYSCFG_ITLINE1_SR_VDDIO2)); + 714:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 715:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE1_SR_VDDIO2 */ + 716:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 717:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE2_SR_RTC_WAKEUP) + 718:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 719:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if RTC Wake Up interrupt occurred or not (EXTI line 20). + 720:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP LL_SYSCFG_IsActiveFlag_RTC_WAKEUP + 721:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 722:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 723:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void) + 724:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 725:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_WAKEUP) == (SYSCFG_ITLINE2_SR_RTC_W + 726:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 727:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE2_SR_RTC_WAKEUP */ + 728:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 729:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE2_SR_RTC_TSTAMP) + 730:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + ARM GAS /tmp/cctNXKqU.s page 59 + + + 731:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 19). + 732:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE2 SR_RTC_TSTAMP LL_SYSCFG_IsActiveFlag_RTC_TSTAMP + 733:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 734:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 735:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_TSTAMP(void) + 736:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 737:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_TSTAMP) == (SYSCFG_ITLINE2_SR_RTC_T + 738:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 739:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE2_SR_RTC_TSTAMP */ + 740:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 741:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE2_SR_RTC_ALRA) + 742:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 743:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if RTC Alarm interrupt occurred or not (EXTI line 17). + 744:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE2 SR_RTC_ALRA LL_SYSCFG_IsActiveFlag_RTC_ALRA + 745:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 746:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 747:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_ALRA(void) + 748:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 749:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_ALRA) == (SYSCFG_ITLINE2_SR_RTC_ALR + 750:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 751:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE2_SR_RTC_ALRA */ + 752:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 753:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE3_SR_FLASH_ITF) + 754:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 755:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Flash interface interrupt occurred or not. + 756:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF + 757:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 758:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 759:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void) + 760:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 761:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ + 762:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 763:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */ + 764:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 765:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE4_SR_CRS) + 766:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 767:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Clock recovery system interrupt occurred or not. + 768:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS + 769:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 770:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 771:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void) + 772:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 773:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS)); + 774:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 775:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE4_SR_CRS */ + 776:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 777:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE4_SR_CLK_CTRL) + 778:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 779:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Reset and clock control interrupt occurred or not. + 780:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL + 781:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 782:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 783:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void) + 784:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 785:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTR + 786:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 787:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */ + ARM GAS /tmp/cctNXKqU.s page 60 + + + 788:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 789:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE5_SR_EXTI0) + 790:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 791:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 0 interrupt occurred or not. + 792:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0 + 793:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 794:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 795:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void) + 796:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 797:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0)); + 798:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 799:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE5_SR_EXTI0 */ + 800:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 801:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE5_SR_EXTI1) + 802:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 803:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 1 interrupt occurred or not. + 804:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1 + 805:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 806:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 807:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void) + 808:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 809:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1)); + 810:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 811:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE5_SR_EXTI1 */ + 812:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 813:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE6_SR_EXTI2) + 814:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 815:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 2 interrupt occurred or not. + 816:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2 + 817:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 818:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 819:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void) + 820:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 821:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2)); + 822:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 823:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE6_SR_EXTI2 */ + 824:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 825:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE6_SR_EXTI3) + 826:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 827:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 3 interrupt occurred or not. + 828:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3 + 829:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 830:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 831:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void) + 832:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 833:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3)); + 834:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 835:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE6_SR_EXTI3 */ + 836:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 837:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI4) + 838:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 839:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 4 interrupt occurred or not. + 840:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4 + 841:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 842:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 843:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void) + 844:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + ARM GAS /tmp/cctNXKqU.s page 61 + + + 845:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4)); + 846:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 847:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI4 */ + 848:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 849:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI5) + 850:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 851:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 5 interrupt occurred or not. + 852:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5 + 853:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 854:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 855:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void) + 856:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 857:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5)); + 858:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 859:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI5 */ + 860:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 861:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI6) + 862:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 863:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 6 interrupt occurred or not. + 864:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6 + 865:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 866:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 867:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void) + 868:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 869:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6)); + 870:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 871:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI6 */ + 872:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 873:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI7) + 874:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 875:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 7 interrupt occurred or not. + 876:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7 + 877:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 878:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 879:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void) + 880:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 881:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7)); + 882:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 883:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI7 */ + 884:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 885:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI8) + 886:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 887:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 8 interrupt occurred or not. + 888:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8 + 889:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 890:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 891:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void) + 892:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 893:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8)); + 894:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 895:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI8 */ + 896:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 897:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI9) + 898:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 899:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 9 interrupt occurred or not. + 900:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9 + 901:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + ARM GAS /tmp/cctNXKqU.s page 62 + + + 902:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 903:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void) + 904:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 905:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9)); + 906:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 907:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI9 */ + 908:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 909:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI10) + 910:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 911:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 10 interrupt occurred or not. + 912:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10 + 913:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 914:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 915:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void) + 916:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 917:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10)); + 918:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 919:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI10 */ + 920:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 921:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI11) + 922:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 923:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 11 interrupt occurred or not. + 924:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11 + 925:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 926:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 927:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void) + 928:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 929:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11)); + 930:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 931:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI11 */ + 932:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 933:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI12) + 934:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 935:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 12 interrupt occurred or not. + 936:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12 + 937:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 938:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 939:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void) + 940:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 941:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12)); + 942:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 943:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI12 */ + 944:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 945:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI13) + 946:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 947:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 13 interrupt occurred or not. + 948:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13 + 949:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 950:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 951:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void) + 952:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 953:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13)); + 954:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 955:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI13 */ + 956:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 957:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI14) + 958:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + ARM GAS /tmp/cctNXKqU.s page 63 + + + 959:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 14 interrupt occurred or not. + 960:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14 + 961:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 962:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 963:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void) + 964:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 965:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14)); + 966:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 967:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI14 */ + 968:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 969:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE7_SR_EXTI15) + 970:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 971:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if EXTI line 15 interrupt occurred or not. + 972:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15 + 973:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 974:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 975:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void) + 976:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 977:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15)); + 978:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 979:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE7_SR_EXTI15 */ + 980:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 981:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE8_SR_TSC_EOA) + 982:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 983:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Touch sensing controller end of acquisition interrupt occurred or not. + 984:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE8 SR_TSC_EOA LL_SYSCFG_IsActiveFlag_TSC_EOA + 985:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 986:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 987:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_EOA(void) + 988:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + 989:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_EOA) == (SYSCFG_ITLINE8_SR_TSC_EOA) + 990:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } + 991:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE8_SR_TSC_EOA */ + 992:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** + 993:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE8_SR_TSC_MCE) + 994:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + 995:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Touch sensing controller max counterror interrupt occurred or not. + 996:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE8 SR_TSC_MCE LL_SYSCFG_IsActiveFlag_TSC_MCE + 997:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + 998:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ + 999:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_MCE(void) +1000:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1001:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_MCE) == (SYSCFG_ITLINE8_SR_TSC_MCE) +1002:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1003:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE8_SR_TSC_MCE */ +1004:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1005:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE9_SR_DMA1_CH1) +1006:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1007:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA1 channel 1 interrupt occurred or not. +1008:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1 +1009:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1010:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1011:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void) +1012:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1013:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH +1014:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1015:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */ + ARM GAS /tmp/cctNXKqU.s page 64 + + +1016:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1017:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE10_SR_DMA1_CH2) +1018:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1019:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA1 channel 2 interrupt occurred or not. +1020:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2 +1021:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1022:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1023:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void) +1024:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1025:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1 +1026:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1027:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */ +1028:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1029:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE10_SR_DMA1_CH3) +1030:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1031:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA1 channel 3 interrupt occurred or not. +1032:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3 +1033:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1034:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1035:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void) +1036:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1037:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1 +1038:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1039:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */ +1040:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1041:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE10_SR_DMA2_CH1) +1042:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1043:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA2 channel 1 interrupt occurred or not. +1044:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH1 LL_SYSCFG_IsActiveFlag_DMA2_CH1 +1045:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1046:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1047:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void) +1048:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1049:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH1) == (SYSCFG_ITLINE10_SR_DMA2 +1050:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1051:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE10_SR_DMA2_CH1 */ +1052:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1053:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE10_SR_DMA2_CH2) +1054:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1055:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA2 channel 2 interrupt occurred or not. +1056:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH2 LL_SYSCFG_IsActiveFlag_DMA2_CH2 +1057:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1058:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1059:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void) +1060:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1061:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH2) == (SYSCFG_ITLINE10_SR_DMA2 +1062:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1063:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE10_SR_DMA2_CH2 */ +1064:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1065:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE11_SR_DMA1_CH4) +1066:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1067:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA1 channel 4 interrupt occurred or not. +1068:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4 +1069:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1070:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1071:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void) +1072:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + ARM GAS /tmp/cctNXKqU.s page 65 + + +1073:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1 +1074:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1075:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */ +1076:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1077:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE11_SR_DMA1_CH5) +1078:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1079:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA1 channel 5 interrupt occurred or not. +1080:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5 +1081:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1082:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1083:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void) +1084:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1085:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1 +1086:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1087:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */ +1088:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1089:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE11_SR_DMA1_CH6) +1090:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1091:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA1 channel 6 interrupt occurred or not. +1092:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6 +1093:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1094:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1095:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void) +1096:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1097:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1 +1098:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1099:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */ +1100:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1101:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE11_SR_DMA1_CH7) +1102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1103:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA1 channel 7 interrupt occurred or not. +1104:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7 +1105:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1106:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1107:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void) +1108:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1109:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1 +1110:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1111:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */ +1112:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1113:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE11_SR_DMA2_CH3) +1114:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1115:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA2 channel 3 interrupt occurred or not. +1116:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3 LL_SYSCFG_IsActiveFlag_DMA2_CH3 +1117:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1119:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void) +1120:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1121:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2 +1122:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1123:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE11_SR_DMA2_CH3 */ +1124:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1125:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE11_SR_DMA2_CH4) +1126:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1127:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA2 channel 4 interrupt occurred or not. +1128:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4 LL_SYSCFG_IsActiveFlag_DMA2_CH4 +1129:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + ARM GAS /tmp/cctNXKqU.s page 66 + + +1130:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1131:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void) +1132:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1133:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2 +1134:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1135:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE11_SR_DMA2_CH4 */ +1136:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1137:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE11_SR_DMA2_CH5) +1138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1139:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DMA2 channel 5 interrupt occurred or not. +1140:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5 LL_SYSCFG_IsActiveFlag_DMA2_CH5 +1141:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1142:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1143:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void) +1144:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1145:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2 +1146:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1147:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE11_SR_DMA2_CH5 */ +1148:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1149:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE12_SR_ADC) +1150:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1151:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if ADC interrupt occurred or not. +1152:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC +1153:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1155:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void) +1156:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1157:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC)); +1158:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1159:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE12_SR_ADC */ +1160:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1161:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE12_SR_COMP1) +1162:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1163:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Comparator 1 interrupt occurred or not (EXTI line 21). +1164:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1 +1165:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1166:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1167:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void) +1168:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1169:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1)) +1170:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1171:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE12_SR_COMP1 */ +1172:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE12_SR_COMP2) +1174:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1175:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Comparator 2 interrupt occurred or not (EXTI line 22). +1176:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2 +1177:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1178:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1179:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void) +1180:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1181:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2)) +1182:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1183:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE12_SR_COMP2 */ +1184:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1185:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE13_SR_TIM1_BRK) +1186:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + ARM GAS /tmp/cctNXKqU.s page 67 + + +1187:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 1 break interrupt occurred or not. +1188:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK +1189:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1190:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1191:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void) +1192:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1193:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1 +1194:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1195:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */ +1196:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1197:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE13_SR_TIM1_UPD) +1198:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1199:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 1 update interrupt occurred or not. +1200:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD +1201:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1202:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1203:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void) +1204:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1205:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1 +1206:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1207:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */ +1208:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1209:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE13_SR_TIM1_TRG) +1210:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1211:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 1 trigger interrupt occurred or not. +1212:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG +1213:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1214:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1215:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void) +1216:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1217:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1 +1218:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1219:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */ +1220:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1221:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE13_SR_TIM1_CCU) +1222:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1223:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 1 commutation interrupt occurred or not. +1224:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU +1225:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1226:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1227:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void) +1228:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1229:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1 +1230:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1231:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */ +1232:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1233:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE14_SR_TIM1_CC) +1234:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1235:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 1 capture compare interrupt occurred or not. +1236:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC +1237:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1238:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1239:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void) +1240:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1241:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_ +1242:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1243:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE14_SR_TIM1_CC */ + ARM GAS /tmp/cctNXKqU.s page 68 + + +1244:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1245:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE15_SR_TIM2_GLB) +1246:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1247:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 2 interrupt occurred or not. +1248:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2 +1249:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1250:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1251:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void) +1252:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1253:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2_GLB) == (SYSCFG_ITLINE15_SR_TIM2 +1254:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1255:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE15_SR_TIM2_GLB */ +1256:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1257:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE16_SR_TIM3_GLB) +1258:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1259:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 3 interrupt occurred or not. +1260:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3 +1261:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1262:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1263:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void) +1264:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1265:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3 +1266:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1267:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */ +1268:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1269:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE17_SR_DAC) +1270:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1271:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if DAC underrun interrupt occurred or not. +1272:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE17 SR_DAC LL_SYSCFG_IsActiveFlag_DAC +1273:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1274:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1275:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void) +1276:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1277:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC)); +1278:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1279:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE17_SR_DAC */ +1280:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1281:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE17_SR_TIM6_GLB) +1282:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1283:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 6 interrupt occurred or not. +1284:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB LL_SYSCFG_IsActiveFlag_TIM6 +1285:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1286:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1287:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void) +1288:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1289:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6_GLB) == (SYSCFG_ITLINE17_SR_TIM6 +1290:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1291:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE17_SR_TIM6_GLB */ +1292:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1293:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE18_SR_TIM7_GLB) +1294:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1295:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 7 interrupt occurred or not. +1296:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB LL_SYSCFG_IsActiveFlag_TIM7 +1297:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1298:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1299:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void) +1300:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { + ARM GAS /tmp/cctNXKqU.s page 69 + + +1301:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7_GLB) == (SYSCFG_ITLINE18_SR_TIM7 +1302:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1303:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE18_SR_TIM7_GLB */ +1304:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1305:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE19_SR_TIM14_GLB) +1306:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1307:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 14 interrupt occurred or not. +1308:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14 +1309:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1310:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1311:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void) +1312:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1313:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM +1314:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1315:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */ +1316:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1317:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE20_SR_TIM15_GLB) +1318:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1319:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 15 interrupt occurred or not. +1320:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15 +1321:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1322:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1323:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void) +1324:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1325:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == (SYSCFG_ITLINE20_SR_TIM +1326:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1327:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */ +1328:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1329:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE21_SR_TIM16_GLB) +1330:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1331:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 16 interrupt occurred or not. +1332:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16 +1333:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1334:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1335:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void) +1336:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1337:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM +1338:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1339:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */ +1340:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1341:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE22_SR_TIM17_GLB) +1342:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1343:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if Timer 17 interrupt occurred or not. +1344:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17 +1345:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1346:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1347:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void) +1348:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1349:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM +1350:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1351:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */ +1352:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1353:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE23_SR_I2C1_GLB) +1354:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1355:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23. +1356:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1 +1357:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). + ARM GAS /tmp/cctNXKqU.s page 70 + + +1358:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1359:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void) +1360:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1361:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1 +1362:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1363:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */ +1364:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1365:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE24_SR_I2C2_GLB) +1366:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1367:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if I2C2 interrupt occurred or not. +1368:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2 +1369:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1370:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1371:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void) +1372:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1373:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2 +1374:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1375:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */ +1376:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1377:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE25_SR_SPI1) +1378:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1379:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if SPI1 interrupt occurred or not. +1380:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1 +1381:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1382:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1383:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void) +1384:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1385:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1)); +1386:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1387:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE25_SR_SPI1 */ +1388:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1389:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE26_SR_SPI2) +1390:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1391:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if SPI2 interrupt occurred or not. +1392:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE26 SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2 +1393:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1394:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1395:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void) +1396:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1397:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2)); +1398:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1399:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE26_SR_SPI2 */ +1400:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1401:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE27_SR_USART1_GLB) +1402:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1403:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25. +1404:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1 +1405:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1406:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1407:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void) +1408:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1409:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_US +1410:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1411:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE27_SR_USART1_GLB */ +1412:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1413:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE28_SR_USART2_GLB) +1414:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + ARM GAS /tmp/cctNXKqU.s page 71 + + +1415:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26. +1416:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2 +1417:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1418:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1419:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void) +1420:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1421:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_US +1422:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1423:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE28_SR_USART2_GLB */ +1424:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1425:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE29_SR_USART3_GLB) +1426:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1427:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if USART3 interrupt occurred or not, combined with EXTI line 28. +1428:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3 +1429:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1430:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1431:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void) +1432:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1433:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == (SYSCFG_ITLINE29_SR_US +1434:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1435:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE29_SR_USART3_GLB */ +1436:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1437:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE29_SR_USART4_GLB) +1438:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1439:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if USART4 interrupt occurred or not. +1440:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4 +1441:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1442:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1443:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void) +1444:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1445:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == (SYSCFG_ITLINE29_SR_US +1446:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1447:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE29_SR_USART4_GLB */ +1448:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1449:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE29_SR_USART5_GLB) +1450:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1451:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if USART5 interrupt occurred or not. +1452:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE29 SR_USART5_GLB LL_SYSCFG_IsActiveFlag_USART5 +1453:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1454:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1455:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5(void) +1456:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1457:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART5_GLB) == (SYSCFG_ITLINE29_SR_US +1458:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1459:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE29_SR_USART5_GLB */ +1460:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1461:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE29_SR_USART6_GLB) +1462:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1463:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if USART6 interrupt occurred or not. +1464:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE29 SR_USART6_GLB LL_SYSCFG_IsActiveFlag_USART6 +1465:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1466:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1467:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6(void) +1468:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1469:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART6_GLB) == (SYSCFG_ITLINE29_SR_US +1470:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1471:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE29_SR_USART6_GLB */ + ARM GAS /tmp/cctNXKqU.s page 72 + + +1472:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1473:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE29_SR_USART7_GLB) +1474:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1475:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if USART7 interrupt occurred or not. +1476:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE29 SR_USART7_GLB LL_SYSCFG_IsActiveFlag_USART7 +1477:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1478:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1479:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART7(void) +1480:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1481:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART7_GLB) == (SYSCFG_ITLINE29_SR_US +1482:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1483:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE29_SR_USART7_GLB */ +1484:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1485:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE29_SR_USART8_GLB) +1486:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1487:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if USART8 interrupt occurred or not. +1488:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE29 SR_USART8_GLB LL_SYSCFG_IsActiveFlag_USART8 +1489:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1490:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1491:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART8(void) +1492:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1493:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART8_GLB) == (SYSCFG_ITLINE29_SR_US +1494:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1495:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE29_SR_USART8_GLB */ +1496:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1497:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE30_SR_CAN) +1498:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1499:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if CAN interrupt occurred or not. +1500:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE30 SR_CAN LL_SYSCFG_IsActiveFlag_CAN +1501:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1502:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1503:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CAN(void) +1504:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1505:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CAN) == (SYSCFG_ITLINE30_SR_CAN)); +1506:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1507:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE30_SR_CAN */ +1508:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1509:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_ITLINE30_SR_CEC) +1510:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1511:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if CEC interrupt occurred or not, combined with EXTI line 27. +1512:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_ITLINE30 SR_CEC LL_SYSCFG_IsActiveFlag_CEC +1513:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1514:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1515:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC(void) +1516:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1517:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CEC) == (SYSCFG_ITLINE30_SR_CEC)); +1518:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1519:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /* SYSCFG_ITLINE30_SR_CEC */ +1520:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1521:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1522:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set connections to TIMx Break inputs +1523:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n +1524:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n +1525:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs +1526:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Break This parameter can be a combination of the following values: +1527:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) +1528:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY + ARM GAS /tmp/cctNXKqU.s page 73 + + +1529:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP +1530:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * +1531:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices +1532:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1533:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1534:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +1535:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1536:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR2_PVD_LOCK) +1537:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2 +1538:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #else +1539:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK, Break); +1540:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR2_PVD_LOCK*/ +1541:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1542:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1543:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1544:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Get connections to TIMx Break inputs +1545:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n +1546:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n +1547:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs +1548:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval Returned value can be can be a combination of the following values: +1549:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) +1550:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY +1551:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP +1552:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * +1553:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices +1554:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1555:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +1556:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1557:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #if defined(SYSCFG_CFGR2_PVD_LOCK) +1558:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->CFGR2, +1559:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR +1560:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #else +1561:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOC +1562:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** #endif /*SYSCFG_CFGR2_PVD_LOCK*/ +1563:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1564:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1565:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1566:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Check if SRAM parity error detected +1567:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_IsActiveFlag_SP +1568:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval State of bit (1 or 0). +1569:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1570:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void) +1571:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1572:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF) == (SYSCFG_CFGR2_SRAM_PEF)); +1573:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1574:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1575:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1576:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Clear SRAM parity error flag +1577:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_ClearFlag_SP +1578:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1579:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1580:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) +1581:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1582:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF); +1583:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1584:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1585:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** + ARM GAS /tmp/cctNXKqU.s page 74 + + +1586:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} +1587:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1588:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1589:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU +1590:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ +1591:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1592:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1593:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1594:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Return the device identifier +1595:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @note For STM32F03x devices, the device ID is 0x444 +1596:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @note For STM32F04x devices, the device ID is 0x445. +1597:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @note For STM32F05x devices, the device ID is 0x440 +1598:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @note For STM32F07x devices, the device ID is 0x448 +1599:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @note For STM32F09x devices, the device ID is 0x442 +1600:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID +1601:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval Values between Min_Data=0x00 and Max_Data=0xFFF +1602:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1603:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +1604:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1605:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +1606:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1607:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1608:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1609:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Return the device revision identifier +1610:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @note This field indicates the revision of the device. +1611:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** For example, it is read as 0x1000 for Revision 1.0. +1612:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID +1613:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF +1614:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1615:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +1616:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1617:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +1618:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1619:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1620:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1621:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Enable the Debug Module during STOP mode +1622:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode +1623:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1624:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1625:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +1626:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1627:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +1628:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1629:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1630:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1631:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Disable the Debug Module during STOP mode +1632:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode +1633:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1634:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1635:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +1636:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1637:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +1638:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1639:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1640:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1641:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Enable the Debug Module during STANDBY mode +1642:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + ARM GAS /tmp/cctNXKqU.s page 75 + + +1643:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1644:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1645:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +1646:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1647:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +1648:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1649:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1650:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1651:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Disable the Debug Module during STANDBY mode +1652:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode +1653:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1654:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1655:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +1656:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1657:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +1658:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1659:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1660:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1661:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Freeze APB1 peripherals (group1 peripherals) +1662:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1663:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1664:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1665:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1666:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1667:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1668:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1669:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1670:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n +1671:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph +1672:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values: +1673:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) +1674:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP +1675:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) +1676:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) +1677:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP +1678:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP +1679:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP +1680:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP +1681:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP +1682:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) +1683:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * +1684:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices +1685:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1686:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1687:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +1688:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1689:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** SET_BIT(DBGMCU->APB1FZ, Periphs); +1690:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1691:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1692:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1693:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Unfreeze APB1 peripherals (group1 peripherals) +1694:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n +1695:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n +1696:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n +1697:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n +1698:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n +1699:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + ARM GAS /tmp/cctNXKqU.s page 76 + + +1700:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n +1701:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n +1702:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n +1703:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph +1704:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values: +1705:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) +1706:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP +1707:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) +1708:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) +1709:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP +1710:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP +1711:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP +1712:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP +1713:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP +1714:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) +1715:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * +1716:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices +1717:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1718:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1719:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +1720:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1721:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** CLEAR_BIT(DBGMCU->APB1FZ, Periphs); +1722:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1723:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1724:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1725:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Freeze APB1 peripherals (group2 peripherals) +1726:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n +1727:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n +1728:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n +1729:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph +1730:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values: +1731:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP +1732:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*) +1733:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP +1734:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP +1735:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * +1736:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices +1737:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1738:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1739:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +1740:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1741:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** SET_BIT(DBGMCU->APB2FZ, Periphs); +1742:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1743:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1744:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1745:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Unfreeze APB1 peripherals (group2 peripherals) +1746:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n +1747:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n +1748:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n +1749:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph +1750:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values: +1751:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP +1752:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*) +1753:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP +1754:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP +1755:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * +1756:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * (*) value not defined in all devices + ARM GAS /tmp/cctNXKqU.s page 77 + + +1757:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1758:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1759:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +1760:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1761:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** CLEAR_BIT(DBGMCU->APB2FZ, Periphs); +1762:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1763:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1764:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @} +1765:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1766:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1767:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_FLASH FLASH +1768:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @{ +1769:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1770:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1771:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1772:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Set FLASH Latency +1773:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency +1774:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @param Latency This parameter can be one of the following values: +1775:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_0 +1776:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_1 +1777:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval None +1778:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1779:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +1780:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1781:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); + 272 .loc 4 1781 0 + 273 000c 0D4A ldr r2, .L30+4 + 274 000e 1368 ldr r3, [r2] + 275 0010 0120 movs r0, #1 + 276 .LVL19: + 277 0012 8343 bics r3, r0 + 278 0014 0B43 orrs r3, r1 + 279 0016 1360 str r3, [r2] + 280 .LVL20: + 281 .LBE57: + 282 .LBE56: + 259:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** do + 283 .loc 1 259 0 + 284 0018 0222 movs r2, #2 + 285 .LVL21: + 286 .L26: + 287 .LBB58: + 288 .LBB59: +1782:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** } +1783:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** +1784:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** /** +1785:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @brief Get FLASH Latency +1786:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency +1787:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @retval Returned value can be one of the following values: +1788:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_0 +1789:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_1 +1790:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** */ +1791:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +1792:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** { +1793:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h **** return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); + 289 .loc 4 1793 0 discriminator 2 + 290 001a 0A4B ldr r3, .L30+4 + ARM GAS /tmp/cctNXKqU.s page 78 + + + 291 001c 1868 ldr r0, [r3] + 292 001e 0123 movs r3, #1 + 293 0020 0340 ands r3, r0 + 294 .LBE59: + 295 .LBE58: + 264:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } while ((getlatency != latency) && (timeout > 0)); + 296 .loc 1 264 0 discriminator 2 + 297 0022 013A subs r2, r2, #1 + 298 .LVL22: + 265:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 299 .loc 1 265 0 discriminator 2 + 300 0024 9942 cmp r1, r3 + 301 0026 01D0 beq .L25 + 265:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 302 .loc 1 265 0 is_stmt 0 discriminator 1 + 303 0028 002A cmp r2, #0 + 304 002a F6D1 bne .L26 + 305 .L25: + 267:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 306 .loc 1 267 0 is_stmt 1 + 307 002c 9942 cmp r1, r3 + 308 002e 05D0 beq .L29 + 269:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 309 .loc 1 269 0 + 310 0030 0120 movs r0, #1 + 311 0032 02E0 b .L23 + 312 .LVL23: + 313 .L28: + 251:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 314 .loc 1 251 0 + 315 0034 0021 movs r1, #0 + 316 0036 E9E7 b .L24 + 317 .L27: + 239:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 318 .loc 1 239 0 + 319 0038 0120 movs r0, #1 + 320 .LVL24: + 321 .L23: + 279:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #endif /* FLASH_ACR_LATENCY */ + 322 .loc 1 279 0 + 323 @ sp needed + 324 003a 7047 bx lr + 325 .LVL25: + 326 .L29: + 273:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 327 .loc 1 273 0 + 328 003c 0020 movs r0, #0 + 329 003e FCE7 b .L23 + 330 .L31: + 331 .align 2 + 332 .L30: + 333 0040 00366E01 .word 24000000 + 334 0044 00200240 .word 1073881088 + 335 .cfi_endproc + 336 .LFE189: + 338 .section .text.UTILS_EnablePLLAndSwitchSystem,"ax",%progbits + 339 .align 1 + ARM GAS /tmp/cctNXKqU.s page 79 + + + 340 .syntax unified + 341 .code 16 + 342 .thumb_func + 343 .fpu softvfp + 345 UTILS_EnablePLLAndSwitchSystem: + 346 .LFB195: + 544:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 545:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /** + 546:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @brief Function to enable PLL and switch system clock to PLL + 547:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @param SYSCLK_Frequency SYSCLK frequency + 548:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + 549:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * the configuration information for the BUS prescalers. + 550:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * @retval An ErrorStatus enumeration value: + 551:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - SUCCESS: No problem to switch system to PLL + 552:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** * - ERROR: Problem to switch system to PLL + 553:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** */ + 554:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDe + 555:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 347 .loc 1 555 0 + 348 .cfi_startproc + 349 @ args = 0, pretend = 0, frame = 0 + 350 @ frame_needed = 0, uses_anonymous_args = 0 + 351 .LVL26: + 352 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 353 .LCFI3: + 354 .cfi_def_cfa_offset 24 + 355 .cfi_offset 3, -24 + 356 .cfi_offset 4, -20 + 357 .cfi_offset 5, -16 + 358 .cfi_offset 6, -12 + 359 .cfi_offset 7, -8 + 360 .cfi_offset 14, -4 + 361 0002 0600 movs r6, r0 + 362 0004 0F00 movs r7, r1 + 363 .LVL27: + 556:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 557:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** uint32_t sysclk_frequency_current = 0U; + 558:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 559:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); + 560:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); + 561:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 562:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Calculate current SYSCLK frequency */ + 563:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSI + 364 .loc 1 563 0 + 365 0006 264B ldr r3, .L43 + 366 0008 1C68 ldr r4, [r3] + 367 .LBB60: + 368 .LBB61: +1173:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 369 .loc 2 1173 0 + 370 000a 264B ldr r3, .L43+4 + 371 000c 5A68 ldr r2, [r3, #4] + 372 .LBE61: + 373 .LBE60: + 374 .loc 1 563 0 + 375 000e 1209 lsrs r2, r2, #4 + 376 0010 0F23 movs r3, #15 + ARM GAS /tmp/cctNXKqU.s page 80 + + + 377 0012 1340 ands r3, r2 + 378 0014 244A ldr r2, .L43+8 + 379 0016 D35C ldrb r3, [r2, r3] + 380 0018 9C40 lsls r4, r4, r3 + 381 .LVL28: + 564:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 565:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Increasing the number of wait states because of higher CPU frequency */ + 566:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if (sysclk_frequency_current < SYSCLK_Frequency) + 382 .loc 1 566 0 + 383 001a 8442 cmp r4, r0 + 384 001c 2AD3 bcc .L40 + 556:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** uint32_t sysclk_frequency_current = 0U; + 385 .loc 1 556 0 + 386 001e 0025 movs r5, #0 + 387 .LVL29: + 388 .L33: + 389 .LBB62: + 390 .LBB63: +1509:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 391 .loc 2 1509 0 + 392 0020 204A ldr r2, .L43+4 + 393 0022 1168 ldr r1, [r2] + 394 0024 8023 movs r3, #128 + 395 0026 5B04 lsls r3, r3, #17 + 396 0028 0B43 orrs r3, r1 + 397 002a 1360 str r3, [r2] + 398 .L35: + 399 .LBE63: + 400 .LBE62: + 401 .LBB64: + 402 .LBB65: + 403 .loc 2 1530 0 discriminator 1 + 404 002c 1D4B ldr r3, .L43+4 + 405 002e 1B68 ldr r3, [r3] + 406 .LBE65: + 407 .LBE64: + 567:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 568:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Set FLASH latency to highest latency */ + 569:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** status = LL_SetFlashLatency(SYSCLK_Frequency); + 570:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 571:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 572:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Update system clock configuration */ + 573:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if (status == SUCCESS) + 574:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 575:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Enable PLL */ + 576:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_RCC_PLL_Enable(); + 577:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** while (LL_RCC_PLL_IsReady() != 1U) + 408 .loc 1 577 0 discriminator 1 + 409 0030 9B01 lsls r3, r3, #6 + 410 0032 FBD5 bpl .L35 + 411 .LVL30: + 412 .LBB66: + 413 .LBB67: +1138:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 414 .loc 2 1138 0 + 415 0034 1B4A ldr r2, .L43+4 + 416 0036 5368 ldr r3, [r2, #4] + ARM GAS /tmp/cctNXKqU.s page 81 + + + 417 0038 F021 movs r1, #240 + 418 003a 8B43 bics r3, r1 + 419 003c 3968 ldr r1, [r7] + 420 003e 0B43 orrs r3, r1 + 421 0040 5360 str r3, [r2, #4] + 422 .LVL31: + 423 .LBE67: + 424 .LBE66: + 425 .LBB68: + 426 .LBB69: +1102:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 427 .loc 2 1102 0 + 428 0042 5368 ldr r3, [r2, #4] + 429 0044 0321 movs r1, #3 + 430 0046 8B43 bics r3, r1 + 431 0048 0139 subs r1, r1, #1 + 432 004a 0B43 orrs r3, r1 + 433 004c 5360 str r3, [r2, #4] + 434 .L36: + 435 .LBE69: + 436 .LBE68: + 437 .LBB70: + 438 .LBB71: +1118:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 439 .loc 2 1118 0 discriminator 1 + 440 004e 154B ldr r3, .L43+4 + 441 0050 5A68 ldr r2, [r3, #4] + 442 0052 0C23 movs r3, #12 + 443 0054 1340 ands r3, r2 + 444 .LBE71: + 445 .LBE70: + 578:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 579:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Wait for PLL ready */ + 580:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 581:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 582:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Sysclk activation on the main PLL */ + 583:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + 584:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + 585:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + 446 .loc 1 585 0 discriminator 1 + 447 0056 082B cmp r3, #8 + 448 0058 F9D1 bne .L36 + 449 .LVL32: + 450 .LBB72: + 451 .LBB73: +1154:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 452 .loc 2 1154 0 + 453 005a 124A ldr r2, .L43+4 + 454 005c 5368 ldr r3, [r2, #4] + 455 005e 1349 ldr r1, .L43+12 + 456 0060 0B40 ands r3, r1 + 457 0062 7968 ldr r1, [r7, #4] + 458 0064 0B43 orrs r3, r1 + 459 0066 5360 str r3, [r2, #4] + 460 .LVL33: + 461 .L34: + 462 .LBE73: + ARM GAS /tmp/cctNXKqU.s page 82 + + + 463 .LBE72: + 586:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 587:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Wait for system clock switch to PLL */ + 588:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 589:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 590:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Set APB1 & APB2 prescaler*/ + 591:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); + 592:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 593:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 594:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Decreasing the number of wait states because of lower CPU frequency */ + 595:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if (sysclk_frequency_current > SYSCLK_Frequency) + 464 .loc 1 595 0 + 465 0068 B442 cmp r4, r6 + 466 006a 08D8 bhi .L41 + 467 .L37: + 468 .LVL34: + 596:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 597:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Set FLASH latency to lowest latency */ + 598:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** status = LL_SetFlashLatency(SYSCLK_Frequency); + 599:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 600:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 601:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** /* Update SystemCoreClock variable */ + 602:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** if (status == SUCCESS) + 469 .loc 1 602 0 + 470 006c 002D cmp r5, #0 + 471 006e 0BD0 beq .L42 + 472 .L38: + 603:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 604:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivi + 605:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 606:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 607:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** return status; + 608:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 473 .loc 1 608 0 + 474 0070 2800 movs r0, r5 + 475 @ sp needed + 476 .LVL35: + 477 .LVL36: + 478 .LVL37: + 479 .LVL38: + 480 0072 F8BD pop {r3, r4, r5, r6, r7, pc} + 481 .LVL39: + 482 .L40: + 569:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 483 .loc 1 569 0 + 484 0074 FFF7FEFF bl LL_SetFlashLatency + 485 .LVL40: + 486 0078 051E subs r5, r0, #0 + 487 .LVL41: + 573:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 488 .loc 1 573 0 + 489 007a F5D1 bne .L34 + 490 007c D0E7 b .L33 + 491 .LVL42: + 492 .L41: + 598:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 493 .loc 1 598 0 + ARM GAS /tmp/cctNXKqU.s page 83 + + + 494 007e 3000 movs r0, r6 + 495 0080 FFF7FEFF bl LL_SetFlashLatency + 496 .LVL43: + 497 0084 0500 movs r5, r0 + 498 .LVL44: + 499 0086 F1E7 b .L37 + 500 .LVL45: + 501 .L42: + 604:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 502 .loc 1 604 0 + 503 0088 3A68 ldr r2, [r7] + 504 008a 1209 lsrs r2, r2, #4 + 505 008c 0F23 movs r3, #15 + 506 008e 1340 ands r3, r2 + 507 0090 054A ldr r2, .L43+8 + 508 0092 D35C ldrb r3, [r2, r3] + 509 0094 3000 movs r0, r6 + 510 0096 D840 lsrs r0, r0, r3 + 511 0098 FFF7FEFF bl LL_SetSystemCoreClock + 512 .LVL46: + 513 009c E8E7 b .L38 + 514 .L44: + 515 009e C046 .align 2 + 516 .L43: + 517 00a0 00000000 .word SystemCoreClock + 518 00a4 00100240 .word 1073876992 + 519 00a8 00000000 .word AHBPrescTable + 520 00ac FFF8FFFF .word -1793 + 521 .cfi_endproc + 522 .LFE195: + 524 .section .text.LL_PLL_ConfigSystemClock_HSI,"ax",%progbits + 525 .align 1 + 526 .global LL_PLL_ConfigSystemClock_HSI + 527 .syntax unified + 528 .code 16 + 529 .thumb_func + 530 .fpu softvfp + 532 LL_PLL_ConfigSystemClock_HSI: + 533 .LFB190: + 301:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 534 .loc 1 301 0 + 535 .cfi_startproc + 536 @ args = 0, pretend = 0, frame = 0 + 537 @ frame_needed = 0, uses_anonymous_args = 0 + 538 .LVL47: + 539 0000 70B5 push {r4, r5, r6, lr} + 540 .LCFI4: + 541 .cfi_def_cfa_offset 16 + 542 .cfi_offset 4, -16 + 543 .cfi_offset 5, -12 + 544 .cfi_offset 6, -8 + 545 .cfi_offset 14, -4 + 546 0002 0500 movs r5, r0 + 547 0004 0C00 movs r4, r1 + 548 .LVL48: + 306:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 549 .loc 1 306 0 + ARM GAS /tmp/cctNXKqU.s page 84 + + + 550 0006 FFF7FEFF bl UTILS_PLL_IsBusy + 551 .LVL49: + 552 000a 0028 cmp r0, #0 + 553 000c 24D1 bne .L49 + 316:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 554 .loc 1 316 0 + 555 000e 2900 movs r1, r5 + 556 0010 1248 ldr r0, .L50 + 557 0012 FFF7FEFF bl UTILS_GetPLLOutputFrequency + 558 .LVL50: + 559 .LBB74: + 560 .LBB75: + 770:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 561 .loc 2 770 0 + 562 0016 124B ldr r3, .L50+4 + 563 0018 1B68 ldr r3, [r3] + 564 .LBE75: + 565 .LBE74: + 319:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 566 .loc 1 319 0 + 567 001a 9B07 lsls r3, r3, #30 + 568 001c 08D4 bmi .L47 + 569 .LBB76: + 570 .LBB77: + 750:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 571 .loc 2 750 0 + 572 001e 104A ldr r2, .L50+4 + 573 0020 1368 ldr r3, [r2] + 574 0022 0121 movs r1, #1 + 575 0024 0B43 orrs r3, r1 + 576 0026 1360 str r3, [r2] + 577 .L48: + 578 .LBE77: + 579 .LBE76: + 580 .LBB78: + 581 .LBB79: + 770:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 582 .loc 2 770 0 discriminator 1 + 583 0028 0D4B ldr r3, .L50+4 + 584 002a 1B68 ldr r3, [r3] + 585 .LBE79: + 586 .LBE78: + 322:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 587 .loc 1 322 0 discriminator 1 + 588 002c 9B07 lsls r3, r3, #30 + 589 002e FBD5 bpl .L48 + 590 .L47: + 330:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #else + 591 .loc 1 330 0 + 592 0030 2E68 ldr r6, [r5] + 593 0032 6968 ldr r1, [r5, #4] + 594 .LVL51: + 595 .LBB80: + 596 .LBB81: +1531:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } +1532:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** +1533:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + ARM GAS /tmp/cctNXKqU.s page 85 + + +1534:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** /** +1535:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @brief Configure PLL used for SYSCLK Domain +1536:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n +1537:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n +1538:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS +1539:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +1540:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +1541:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +1542:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) +1543:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * +1544:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * (*) value not defined in all devices +1545:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param PLLMul This parameter can be one of the following values: +1546:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_2 +1547:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3 +1548:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4 +1549:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_5 +1550:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6 +1551:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_7 +1552:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8 +1553:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_9 +1554:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_10 +1555:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_11 +1556:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12 +1557:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_13 +1558:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_14 +1559:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_15 +1560:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16 +1561:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @param PLLDiv This parameter can be one of the following values: +1562:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_1 +1563:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_2 +1564:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_3 +1565:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_4 +1566:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_5 +1567:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_6 +1568:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_7 +1569:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_8 +1570:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_9 +1571:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_10 +1572:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_11 +1573:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_12 +1574:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_13 +1575:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_14 +1576:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_15 +1577:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @arg @ref LL_RCC_PREDIV_DIV_16 +1578:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** * @retval None +1579:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** */ +1580:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) +1581:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** { +1582:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul); + 597 .loc 2 1582 0 + 598 0034 0A4A ldr r2, .L50+4 + 599 0036 5368 ldr r3, [r2, #4] + 600 0038 0A4D ldr r5, .L50+8 + 601 .LVL52: + 602 003a 2B40 ands r3, r5 + 603 003c 8025 movs r5, #128 + 604 003e 2D02 lsls r5, r5, #8 + ARM GAS /tmp/cctNXKqU.s page 86 + + + 605 0040 3543 orrs r5, r6 + 606 0042 2B43 orrs r3, r5 + 607 0044 5360 str r3, [r2, #4] +1583:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); + 608 .loc 2 1583 0 + 609 0046 D36A ldr r3, [r2, #44] + 610 0048 0F25 movs r5, #15 + 611 004a AB43 bics r3, r5 + 612 004c 0B43 orrs r3, r1 + 613 004e D362 str r3, [r2, #44] + 614 .LVL53: + 615 .LBE81: + 616 .LBE80: + 336:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 617 .loc 1 336 0 + 618 0050 2100 movs r1, r4 + 619 0052 FFF7FEFF bl UTILS_EnablePLLAndSwitchSystem + 620 .LVL54: + 621 .L46: + 345:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 622 .loc 1 345 0 + 623 @ sp needed + 624 .LVL55: + 625 0056 70BD pop {r4, r5, r6, pc} + 626 .LVL56: + 627 .L49: + 341:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 628 .loc 1 341 0 + 629 0058 0120 movs r0, #1 + 630 005a FCE7 b .L46 + 631 .L51: + 632 .align 2 + 633 .L50: + 634 005c 00127A00 .word 8000000 + 635 0060 00100240 .word 1073876992 + 636 0064 FF7FC2FF .word -4030465 + 637 .cfi_endproc + 638 .LFE190: + 640 .section .text.LL_PLL_ConfigSystemClock_HSI48,"ax",%progbits + 641 .align 1 + 642 .global LL_PLL_ConfigSystemClock_HSI48 + 643 .syntax unified + 644 .code 16 + 645 .thumb_func + 646 .fpu softvfp + 648 LL_PLL_ConfigSystemClock_HSI48: + 649 .LFB191: + 365:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 650 .loc 1 365 0 + 651 .cfi_startproc + 652 @ args = 0, pretend = 0, frame = 0 + 653 @ frame_needed = 0, uses_anonymous_args = 0 + 654 .LVL57: + 655 0000 70B5 push {r4, r5, r6, lr} + 656 .LCFI5: + 657 .cfi_def_cfa_offset 16 + 658 .cfi_offset 4, -16 + ARM GAS /tmp/cctNXKqU.s page 87 + + + 659 .cfi_offset 5, -12 + 660 .cfi_offset 6, -8 + 661 .cfi_offset 14, -4 + 662 0002 0500 movs r5, r0 + 663 0004 0C00 movs r4, r1 + 664 .LVL58: + 370:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 665 .loc 1 370 0 + 666 0006 FFF7FEFF bl UTILS_PLL_IsBusy + 667 .LVL59: + 668 000a 0028 cmp r0, #0 + 669 000c 25D1 bne .L56 + 376:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 670 .loc 1 376 0 + 671 000e 2900 movs r1, r5 + 672 0010 1348 ldr r0, .L57 + 673 0012 FFF7FEFF bl UTILS_GetPLLOutputFrequency + 674 .LVL60: + 675 .LBB82: + 676 .LBB83: + 845:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 677 .loc 2 845 0 + 678 0016 134B ldr r3, .L57+4 + 679 0018 5B6B ldr r3, [r3, #52] + 680 .LBE83: + 681 .LBE82: + 379:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 682 .loc 1 379 0 + 683 001a 9B03 lsls r3, r3, #14 + 684 001c 09D4 bmi .L54 + 685 .LBB84: + 686 .LBB85: + 825:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 687 .loc 2 825 0 + 688 001e 114A ldr r2, .L57+4 + 689 0020 516B ldr r1, [r2, #52] + 690 0022 8023 movs r3, #128 + 691 0024 5B02 lsls r3, r3, #9 + 692 0026 0B43 orrs r3, r1 + 693 0028 5363 str r3, [r2, #52] + 694 .L55: + 695 .LBE85: + 696 .LBE84: + 697 .LBB86: + 698 .LBB87: + 845:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 699 .loc 2 845 0 discriminator 1 + 700 002a 0E4B ldr r3, .L57+4 + 701 002c 5B6B ldr r3, [r3, #52] + 702 .LBE87: + 703 .LBE86: + 382:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 704 .loc 1 382 0 discriminator 1 + 705 002e 9B03 lsls r3, r3, #14 + 706 0030 FBD5 bpl .L55 + 707 .L54: + 389:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + ARM GAS /tmp/cctNXKqU.s page 88 + + + 708 .loc 1 389 0 + 709 0032 2E68 ldr r6, [r5] + 710 0034 6968 ldr r1, [r5, #4] + 711 .LVL61: + 712 .LBB88: + 713 .LBB89: +1582:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); + 714 .loc 2 1582 0 + 715 0036 0B4A ldr r2, .L57+4 + 716 0038 5368 ldr r3, [r2, #4] + 717 003a 0B4D ldr r5, .L57+8 + 718 .LVL62: + 719 003c 2B40 ands r3, r5 + 720 003e C025 movs r5, #192 + 721 0040 6D02 lsls r5, r5, #9 + 722 0042 3543 orrs r5, r6 + 723 0044 2B43 orrs r3, r5 + 724 0046 5360 str r3, [r2, #4] + 725 .loc 2 1583 0 + 726 0048 D36A ldr r3, [r2, #44] + 727 004a 0F25 movs r5, #15 + 728 004c AB43 bics r3, r5 + 729 004e 0B43 orrs r3, r1 + 730 0050 D362 str r3, [r2, #44] + 731 .LVL63: + 732 .LBE89: + 733 .LBE88: + 392:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 734 .loc 1 392 0 + 735 0052 2100 movs r1, r4 + 736 0054 FFF7FEFF bl UTILS_EnablePLLAndSwitchSystem + 737 .LVL64: + 738 .L53: + 401:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 739 .loc 1 401 0 + 740 @ sp needed + 741 .LVL65: + 742 0058 70BD pop {r4, r5, r6, pc} + 743 .LVL66: + 744 .L56: + 397:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 745 .loc 1 397 0 + 746 005a 0120 movs r0, #1 + 747 005c FCE7 b .L53 + 748 .L58: + 749 005e C046 .align 2 + 750 .L57: + 751 0060 006CDC02 .word 48000000 + 752 0064 00100240 .word 1073876992 + 753 0068 FF7FC2FF .word -4030465 + 754 .cfi_endproc + 755 .LFE191: + 757 .section .text.LL_PLL_ConfigSystemClock_HSE,"ax",%progbits + 758 .align 1 + 759 .global LL_PLL_ConfigSystemClock_HSE + 760 .syntax unified + 761 .code 16 + ARM GAS /tmp/cctNXKqU.s page 89 + + + 762 .thumb_func + 763 .fpu softvfp + 765 LL_PLL_ConfigSystemClock_HSE: + 766 .LFB192: + 426:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 767 .loc 1 426 0 + 768 .cfi_startproc + 769 @ args = 0, pretend = 0, frame = 0 + 770 @ frame_needed = 0, uses_anonymous_args = 0 + 771 .LVL67: + 772 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 773 .LCFI6: + 774 .cfi_def_cfa_offset 24 + 775 .cfi_offset 3, -24 + 776 .cfi_offset 4, -20 + 777 .cfi_offset 5, -16 + 778 .cfi_offset 6, -12 + 779 .cfi_offset 7, -8 + 780 .cfi_offset 14, -4 + 781 0002 0700 movs r7, r0 + 782 0004 0E00 movs r6, r1 + 783 0006 1500 movs r5, r2 + 784 0008 1C00 movs r4, r3 + 785 .LVL68: + 435:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 786 .loc 1 435 0 + 787 000a FFF7FEFF bl UTILS_PLL_IsBusy + 788 .LVL69: + 789 000e 0028 cmp r0, #0 + 790 0010 33D1 bne .L65 + 445:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 791 .loc 1 445 0 + 792 0012 2900 movs r1, r5 + 793 0014 3800 movs r0, r7 + 794 0016 FFF7FEFF bl UTILS_GetPLLOutputFrequency + 795 .LVL70: + 796 .LBB90: + 797 .LBB91: + 732:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 798 .loc 2 732 0 + 799 001a 194B ldr r3, .L67 + 800 001c 1B68 ldr r3, [r3] + 801 .LBE91: + 802 .LBE90: + 448:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 803 .loc 1 448 0 + 804 001e 9B03 lsls r3, r3, #14 + 805 0020 10D4 bmi .L61 + 451:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 806 .loc 1 451 0 + 807 0022 012E cmp r6, #1 + 808 0024 22D0 beq .L66 + 809 .LBB92: + 810 .LBB93: + 702:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 811 .loc 2 702 0 + 812 0026 164A ldr r2, .L67 + ARM GAS /tmp/cctNXKqU.s page 90 + + + 813 0028 1368 ldr r3, [r2] + 814 002a 1649 ldr r1, .L67+4 + 815 002c 0B40 ands r3, r1 + 816 002e 1360 str r3, [r2] + 817 .L63: + 818 .LBE93: + 819 .LBE92: + 820 .LBB94: + 821 .LBB95: + 712:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 822 .loc 2 712 0 + 823 0030 134A ldr r2, .L67 + 824 0032 1168 ldr r1, [r2] + 825 0034 8023 movs r3, #128 + 826 0036 5B02 lsls r3, r3, #9 + 827 0038 0B43 orrs r3, r1 + 828 003a 1360 str r3, [r2] + 829 .L64: + 830 .LBE95: + 831 .LBE94: + 832 .LBB96: + 833 .LBB97: + 732:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 834 .loc 2 732 0 discriminator 1 + 835 003c 104B ldr r3, .L67 + 836 003e 1B68 ldr r3, [r3] + 837 .LBE97: + 838 .LBE96: + 462:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** { + 839 .loc 1 462 0 discriminator 1 + 840 0040 9B03 lsls r3, r3, #14 + 841 0042 FBD5 bpl .L64 + 842 .L61: + 470:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** #else + 843 .loc 1 470 0 + 844 0044 2E68 ldr r6, [r5] + 845 .LVL71: + 846 0046 6968 ldr r1, [r5, #4] + 847 .LVL72: + 848 .LBB98: + 849 .LBB99: +1582:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); + 850 .loc 2 1582 0 + 851 0048 0D4A ldr r2, .L67 + 852 004a 5368 ldr r3, [r2, #4] + 853 004c 0E4D ldr r5, .L67+8 + 854 .LVL73: + 855 004e 2B40 ands r3, r5 + 856 0050 8025 movs r5, #128 + 857 0052 6D02 lsls r5, r5, #9 + 858 0054 3543 orrs r5, r6 + 859 0056 2B43 orrs r3, r5 + 860 0058 5360 str r3, [r2, #4] + 861 .loc 2 1583 0 + 862 005a D36A ldr r3, [r2, #44] + 863 005c 0F25 movs r5, #15 + 864 005e AB43 bics r3, r5 + ARM GAS /tmp/cctNXKqU.s page 91 + + + 865 0060 0B43 orrs r3, r1 + 866 0062 D362 str r3, [r2, #44] + 867 .LVL74: + 868 .LBE99: + 869 .LBE98: + 476:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 870 .loc 1 476 0 + 871 0064 2100 movs r1, r4 + 872 0066 FFF7FEFF bl UTILS_EnablePLLAndSwitchSystem + 873 .LVL75: + 874 .L60: + 485:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** + 875 .loc 1 485 0 + 876 @ sp needed + 877 .LVL76: + 878 .LVL77: + 879 006a F8BD pop {r3, r4, r5, r6, r7, pc} + 880 .LVL78: + 881 .L66: + 882 .LBB100: + 883 .LBB101: + 692:Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h **** } + 884 .loc 2 692 0 + 885 006c 044A ldr r2, .L67 + 886 006e 1168 ldr r1, [r2] + 887 0070 8023 movs r3, #128 + 888 0072 DB02 lsls r3, r3, #11 + 889 0074 0B43 orrs r3, r1 + 890 0076 1360 str r3, [r2] + 891 0078 DAE7 b .L63 + 892 .LVL79: + 893 .L65: + 894 .LBE101: + 895 .LBE100: + 481:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c **** } + 896 .loc 1 481 0 + 897 007a 0120 movs r0, #1 + 898 007c F5E7 b .L60 + 899 .L68: + 900 007e C046 .align 2 + 901 .L67: + 902 0080 00100240 .word 1073876992 + 903 0084 FFFFFBFF .word -262145 + 904 0088 FF7FC2FF .word -4030465 + 905 .cfi_endproc + 906 .LFE192: + 908 .text + 909 .Letext0: + 910 .file 5 "/usr/include/newlib/machine/_default_types.h" + 911 .file 6 "/usr/include/newlib/sys/_stdint.h" + 912 .file 7 "Drivers/CMSIS/Include/core_cm0.h" + 913 .file 8 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h" + 914 .file 9 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h" + 915 .file 10 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h" + ARM GAS /tmp/cctNXKqU.s page 92 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f0xx_ll_utils.c + /tmp/cctNXKqU.s:17 .text.UTILS_GetPLLOutputFrequency:0000000000000000 $t + /tmp/cctNXKqU.s:23 .text.UTILS_GetPLLOutputFrequency:0000000000000000 UTILS_GetPLLOutputFrequency + /tmp/cctNXKqU.s:62 .text.UTILS_PLL_IsBusy:0000000000000000 $t + /tmp/cctNXKqU.s:68 .text.UTILS_PLL_IsBusy:0000000000000000 UTILS_PLL_IsBusy + /tmp/cctNXKqU.s:102 .text.UTILS_PLL_IsBusy:0000000000000010 $d + /tmp/cctNXKqU.s:107 .text.LL_Init1msTick:0000000000000000 $t + /tmp/cctNXKqU.s:114 .text.LL_Init1msTick:0000000000000000 LL_Init1msTick + /tmp/cctNXKqU.s:153 .text.LL_Init1msTick:000000000000001c $d + /tmp/cctNXKqU.s:158 .text.LL_mDelay:0000000000000000 $t + /tmp/cctNXKqU.s:165 .text.LL_mDelay:0000000000000000 LL_mDelay + /tmp/cctNXKqU.s:209 .text.LL_mDelay:0000000000000024 $d + /tmp/cctNXKqU.s:214 .text.LL_SetSystemCoreClock:0000000000000000 $t + /tmp/cctNXKqU.s:221 .text.LL_SetSystemCoreClock:0000000000000000 LL_SetSystemCoreClock + /tmp/cctNXKqU.s:238 .text.LL_SetSystemCoreClock:0000000000000008 $d + /tmp/cctNXKqU.s:243 .text.LL_SetFlashLatency:0000000000000000 $t + /tmp/cctNXKqU.s:250 .text.LL_SetFlashLatency:0000000000000000 LL_SetFlashLatency + /tmp/cctNXKqU.s:333 .text.LL_SetFlashLatency:0000000000000040 $d + /tmp/cctNXKqU.s:339 .text.UTILS_EnablePLLAndSwitchSystem:0000000000000000 $t + /tmp/cctNXKqU.s:345 .text.UTILS_EnablePLLAndSwitchSystem:0000000000000000 UTILS_EnablePLLAndSwitchSystem + /tmp/cctNXKqU.s:517 .text.UTILS_EnablePLLAndSwitchSystem:00000000000000a0 $d + /tmp/cctNXKqU.s:525 .text.LL_PLL_ConfigSystemClock_HSI:0000000000000000 $t + /tmp/cctNXKqU.s:532 .text.LL_PLL_ConfigSystemClock_HSI:0000000000000000 LL_PLL_ConfigSystemClock_HSI + /tmp/cctNXKqU.s:634 .text.LL_PLL_ConfigSystemClock_HSI:000000000000005c $d + /tmp/cctNXKqU.s:641 .text.LL_PLL_ConfigSystemClock_HSI48:0000000000000000 $t + /tmp/cctNXKqU.s:648 .text.LL_PLL_ConfigSystemClock_HSI48:0000000000000000 LL_PLL_ConfigSystemClock_HSI48 + /tmp/cctNXKqU.s:751 .text.LL_PLL_ConfigSystemClock_HSI48:0000000000000060 $d + /tmp/cctNXKqU.s:758 .text.LL_PLL_ConfigSystemClock_HSE:0000000000000000 $t + /tmp/cctNXKqU.s:765 .text.LL_PLL_ConfigSystemClock_HSE:0000000000000000 LL_PLL_ConfigSystemClock_HSE + /tmp/cctNXKqU.s:902 .text.LL_PLL_ConfigSystemClock_HSE:0000000000000080 $d + +UNDEFINED SYMBOLS +__aeabi_uidiv +SystemCoreClock +AHBPrescTable diff --git a/bsl/makeLowLayer/build/system_stm32f0xx.lst b/bsl/makeLowLayer/build/system_stm32f0xx.lst new file mode 100644 index 0000000..42f7236 --- /dev/null +++ b/bsl/makeLowLayer/build/system_stm32f0xx.lst @@ -0,0 +1,520 @@ +ARM GAS /tmp/ccjISuh0.s page 1 + + + 1 .cpu cortex-m0 + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "system_stm32f0xx.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.SystemInit,"ax",%progbits + 16 .align 1 + 17 .global SystemInit + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 SystemInit: + 24 .LFB40: + 25 .file 1 "Src/system_stm32f0xx.c" + 1:Src/system_stm32f0xx.c **** /** + 2:Src/system_stm32f0xx.c **** ****************************************************************************** + 3:Src/system_stm32f0xx.c **** * @file system_stm32f0xx.c + 4:Src/system_stm32f0xx.c **** * @author MCD Application Team + 5:Src/system_stm32f0xx.c **** * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. + 6:Src/system_stm32f0xx.c **** * + 7:Src/system_stm32f0xx.c **** * 1. This file provides two functions and one global variable to be called from + 8:Src/system_stm32f0xx.c **** * user application: + 9:Src/system_stm32f0xx.c **** * - SystemInit(): This function is called at startup just after reset and + 10:Src/system_stm32f0xx.c **** * before branch to main program. This call is made inside + 11:Src/system_stm32f0xx.c **** * the "startup_stm32f0xx.s" file. + 12:Src/system_stm32f0xx.c **** * + 13:Src/system_stm32f0xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + 14:Src/system_stm32f0xx.c **** * by the user application to setup the SysTick + 15:Src/system_stm32f0xx.c **** * timer or configure other parameters. + 16:Src/system_stm32f0xx.c **** * + 17:Src/system_stm32f0xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + 18:Src/system_stm32f0xx.c **** * be called whenever the core clock is changed + 19:Src/system_stm32f0xx.c **** * during program execution. + 20:Src/system_stm32f0xx.c **** * + 21:Src/system_stm32f0xx.c **** * + 22:Src/system_stm32f0xx.c **** ****************************************************************************** + 23:Src/system_stm32f0xx.c **** * @attention + 24:Src/system_stm32f0xx.c **** * + 25:Src/system_stm32f0xx.c **** *

© Copyright (c) 2016 STMicroelectronics. + 26:Src/system_stm32f0xx.c **** * All rights reserved.

+ 27:Src/system_stm32f0xx.c **** * + 28:Src/system_stm32f0xx.c **** * This software component is licensed by ST under BSD 3-Clause license, + 29:Src/system_stm32f0xx.c **** * the "License"; You may not use this file except in compliance with the + 30:Src/system_stm32f0xx.c **** * License. You may obtain a copy of the License at: + 31:Src/system_stm32f0xx.c **** * opensource.org/licenses/BSD-3-Clause + 32:Src/system_stm32f0xx.c **** * + 33:Src/system_stm32f0xx.c **** ****************************************************************************** + ARM GAS /tmp/ccjISuh0.s page 2 + + + 34:Src/system_stm32f0xx.c **** */ + 35:Src/system_stm32f0xx.c **** + 36:Src/system_stm32f0xx.c **** /** @addtogroup CMSIS + 37:Src/system_stm32f0xx.c **** * @{ + 38:Src/system_stm32f0xx.c **** */ + 39:Src/system_stm32f0xx.c **** + 40:Src/system_stm32f0xx.c **** /** @addtogroup stm32f0xx_system + 41:Src/system_stm32f0xx.c **** * @{ + 42:Src/system_stm32f0xx.c **** */ + 43:Src/system_stm32f0xx.c **** + 44:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_Includes + 45:Src/system_stm32f0xx.c **** * @{ + 46:Src/system_stm32f0xx.c **** */ + 47:Src/system_stm32f0xx.c **** + 48:Src/system_stm32f0xx.c **** #include "stm32f0xx.h" + 49:Src/system_stm32f0xx.c **** + 50:Src/system_stm32f0xx.c **** /** + 51:Src/system_stm32f0xx.c **** * @} + 52:Src/system_stm32f0xx.c **** */ + 53:Src/system_stm32f0xx.c **** + 54:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_TypesDefinitions + 55:Src/system_stm32f0xx.c **** * @{ + 56:Src/system_stm32f0xx.c **** */ + 57:Src/system_stm32f0xx.c **** + 58:Src/system_stm32f0xx.c **** /** + 59:Src/system_stm32f0xx.c **** * @} + 60:Src/system_stm32f0xx.c **** */ + 61:Src/system_stm32f0xx.c **** + 62:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_Defines + 63:Src/system_stm32f0xx.c **** * @{ + 64:Src/system_stm32f0xx.c **** */ + 65:Src/system_stm32f0xx.c **** #if !defined (HSE_VALUE) + 66:Src/system_stm32f0xx.c **** #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + 67:Src/system_stm32f0xx.c **** This value can be provided and adapted by the user + 68:Src/system_stm32f0xx.c **** #endif /* HSE_VALUE */ + 69:Src/system_stm32f0xx.c **** + 70:Src/system_stm32f0xx.c **** #if !defined (HSI_VALUE) + 71:Src/system_stm32f0xx.c **** #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + 72:Src/system_stm32f0xx.c **** This value can be provided and adapted by the user + 73:Src/system_stm32f0xx.c **** #endif /* HSI_VALUE */ + 74:Src/system_stm32f0xx.c **** + 75:Src/system_stm32f0xx.c **** #if !defined (HSI48_VALUE) + 76:Src/system_stm32f0xx.c **** #define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in + 77:Src/system_stm32f0xx.c **** This value can be provided and adapted by the user + 78:Src/system_stm32f0xx.c **** #endif /* HSI48_VALUE */ + 79:Src/system_stm32f0xx.c **** /** + 80:Src/system_stm32f0xx.c **** * @} + 81:Src/system_stm32f0xx.c **** */ + 82:Src/system_stm32f0xx.c **** + 83:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_Macros + 84:Src/system_stm32f0xx.c **** * @{ + 85:Src/system_stm32f0xx.c **** */ + 86:Src/system_stm32f0xx.c **** + 87:Src/system_stm32f0xx.c **** /** + 88:Src/system_stm32f0xx.c **** * @} + 89:Src/system_stm32f0xx.c **** */ + 90:Src/system_stm32f0xx.c **** + ARM GAS /tmp/ccjISuh0.s page 3 + + + 91:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_Variables + 92:Src/system_stm32f0xx.c **** * @{ + 93:Src/system_stm32f0xx.c **** */ + 94:Src/system_stm32f0xx.c **** /* This variable is updated in three ways: + 95:Src/system_stm32f0xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate() + 96:Src/system_stm32f0xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 97:Src/system_stm32f0xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + 98:Src/system_stm32f0xx.c **** Note: If you use this function to configure the system clock; then there + 99:Src/system_stm32f0xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock + 100:Src/system_stm32f0xx.c **** variable is updated automatically. + 101:Src/system_stm32f0xx.c **** */ + 102:Src/system_stm32f0xx.c **** uint32_t SystemCoreClock = 8000000; + 103:Src/system_stm32f0xx.c **** + 104:Src/system_stm32f0xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + 105:Src/system_stm32f0xx.c **** const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + 106:Src/system_stm32f0xx.c **** + 107:Src/system_stm32f0xx.c **** /** + 108:Src/system_stm32f0xx.c **** * @} + 109:Src/system_stm32f0xx.c **** */ + 110:Src/system_stm32f0xx.c **** + 111:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes + 112:Src/system_stm32f0xx.c **** * @{ + 113:Src/system_stm32f0xx.c **** */ + 114:Src/system_stm32f0xx.c **** + 115:Src/system_stm32f0xx.c **** /** + 116:Src/system_stm32f0xx.c **** * @} + 117:Src/system_stm32f0xx.c **** */ + 118:Src/system_stm32f0xx.c **** + 119:Src/system_stm32f0xx.c **** /** @addtogroup STM32F0xx_System_Private_Functions + 120:Src/system_stm32f0xx.c **** * @{ + 121:Src/system_stm32f0xx.c **** */ + 122:Src/system_stm32f0xx.c **** + 123:Src/system_stm32f0xx.c **** /** + 124:Src/system_stm32f0xx.c **** * @brief Setup the microcontroller system + 125:Src/system_stm32f0xx.c **** * @param None + 126:Src/system_stm32f0xx.c **** * @retval None + 127:Src/system_stm32f0xx.c **** */ + 128:Src/system_stm32f0xx.c **** void SystemInit(void) + 129:Src/system_stm32f0xx.c **** { + 26 .loc 1 129 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 @ link register save eliminated. + 130:Src/system_stm32f0xx.c **** /* NOTE :SystemInit(): This function is called at startup just after reset and + 131:Src/system_stm32f0xx.c **** before branch to main program. This call is made inside + 132:Src/system_stm32f0xx.c **** the "startup_stm32f0xx.s" file. + 133:Src/system_stm32f0xx.c **** User can setups the default system clock (System clock source, PLL Multipl + 134:Src/system_stm32f0xx.c **** and Divider factors, AHB/APBx prescalers and Flash settings). + 135:Src/system_stm32f0xx.c **** */ + 136:Src/system_stm32f0xx.c **** } + 31 .loc 1 136 0 + 32 @ sp needed + 33 0000 7047 bx lr + 34 .cfi_endproc + 35 .LFE40: + 37 .global __aeabi_uidiv + ARM GAS /tmp/ccjISuh0.s page 4 + + + 38 .section .text.SystemCoreClockUpdate,"ax",%progbits + 39 .align 1 + 40 .global SystemCoreClockUpdate + 41 .syntax unified + 42 .code 16 + 43 .thumb_func + 44 .fpu softvfp + 46 SystemCoreClockUpdate: + 47 .LFB41: + 137:Src/system_stm32f0xx.c **** + 138:Src/system_stm32f0xx.c **** /** + 139:Src/system_stm32f0xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values. + 140:Src/system_stm32f0xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can + 141:Src/system_stm32f0xx.c **** * be used by the user application to setup the SysTick timer or configure + 142:Src/system_stm32f0xx.c **** * other parameters. + 143:Src/system_stm32f0xx.c **** * + 144:Src/system_stm32f0xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called + 145:Src/system_stm32f0xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration + 146:Src/system_stm32f0xx.c **** * based on this variable will be incorrect. + 147:Src/system_stm32f0xx.c **** * + 148:Src/system_stm32f0xx.c **** * @note - The system frequency computed by this function is not the real + 149:Src/system_stm32f0xx.c **** * frequency in the chip. It is calculated based on the predefined + 150:Src/system_stm32f0xx.c **** * constant and the selected clock source: + 151:Src/system_stm32f0xx.c **** * + 152:Src/system_stm32f0xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + 153:Src/system_stm32f0xx.c **** * + 154:Src/system_stm32f0xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + 155:Src/system_stm32f0xx.c **** * + 156:Src/system_stm32f0xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + 157:Src/system_stm32f0xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors. + 158:Src/system_stm32f0xx.c **** * + 159:Src/system_stm32f0xx.c **** * (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value + 160:Src/system_stm32f0xx.c **** * 8 MHz) but the real value may vary depending on the variations + 161:Src/system_stm32f0xx.c **** * in voltage and temperature. + 162:Src/system_stm32f0xx.c **** * + 163:Src/system_stm32f0xx.c **** * (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (its value + 164:Src/system_stm32f0xx.c **** * depends on the application requirements), user has to ensure that HSE_VALUE + 165:Src/system_stm32f0xx.c **** * is same as the real frequency of the crystal used. Otherwise, this function + 166:Src/system_stm32f0xx.c **** * may have wrong result. + 167:Src/system_stm32f0xx.c **** * + 168:Src/system_stm32f0xx.c **** * - The result of this function could be not correct when using fractional + 169:Src/system_stm32f0xx.c **** * value for HSE crystal. + 170:Src/system_stm32f0xx.c **** * + 171:Src/system_stm32f0xx.c **** * @param None + 172:Src/system_stm32f0xx.c **** * @retval None + 173:Src/system_stm32f0xx.c **** */ + 174:Src/system_stm32f0xx.c **** void SystemCoreClockUpdate (void) + 175:Src/system_stm32f0xx.c **** { + 48 .loc 1 175 0 + 49 .cfi_startproc + 50 @ args = 0, pretend = 0, frame = 0 + 51 @ frame_needed = 0, uses_anonymous_args = 0 + 52 0000 10B5 push {r4, lr} + 53 .LCFI0: + 54 .cfi_def_cfa_offset 8 + 55 .cfi_offset 4, -8 + 56 .cfi_offset 14, -4 + ARM GAS /tmp/ccjISuh0.s page 5 + + + 57 .LVL0: + 176:Src/system_stm32f0xx.c **** uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; + 177:Src/system_stm32f0xx.c **** + 178:Src/system_stm32f0xx.c **** /* Get SYSCLK source -------------------------------------------------------*/ + 179:Src/system_stm32f0xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS; + 58 .loc 1 179 0 + 59 0002 254B ldr r3, .L14 + 60 0004 5A68 ldr r2, [r3, #4] + 61 0006 0C23 movs r3, #12 + 62 0008 1340 ands r3, r2 + 63 .LVL1: + 180:Src/system_stm32f0xx.c **** + 181:Src/system_stm32f0xx.c **** switch (tmp) + 64 .loc 1 181 0 + 65 000a 042B cmp r3, #4 + 66 000c 16D0 beq .L4 + 67 000e 082B cmp r3, #8 + 68 0010 18D0 beq .L5 + 69 0012 002B cmp r3, #0 + 70 0014 03D0 beq .L11 + 182:Src/system_stm32f0xx.c **** { + 183:Src/system_stm32f0xx.c **** case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + 184:Src/system_stm32f0xx.c **** SystemCoreClock = HSI_VALUE; + 185:Src/system_stm32f0xx.c **** break; + 186:Src/system_stm32f0xx.c **** case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + 187:Src/system_stm32f0xx.c **** SystemCoreClock = HSE_VALUE; + 188:Src/system_stm32f0xx.c **** break; + 189:Src/system_stm32f0xx.c **** case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + 190:Src/system_stm32f0xx.c **** /* Get PLL clock source and multiplication factor ----------------------*/ + 191:Src/system_stm32f0xx.c **** pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + 192:Src/system_stm32f0xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + 193:Src/system_stm32f0xx.c **** pllmull = ( pllmull >> 18) + 2; + 194:Src/system_stm32f0xx.c **** predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + 195:Src/system_stm32f0xx.c **** + 196:Src/system_stm32f0xx.c **** if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + 197:Src/system_stm32f0xx.c **** { + 198:Src/system_stm32f0xx.c **** /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ + 199:Src/system_stm32f0xx.c **** SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; + 200:Src/system_stm32f0xx.c **** } + 201:Src/system_stm32f0xx.c **** #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || + 202:Src/system_stm32f0xx.c **** else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) + 203:Src/system_stm32f0xx.c **** { + 204:Src/system_stm32f0xx.c **** /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ + 205:Src/system_stm32f0xx.c **** SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; + 206:Src/system_stm32f0xx.c **** } + 207:Src/system_stm32f0xx.c **** #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + 208:Src/system_stm32f0xx.c **** else + 209:Src/system_stm32f0xx.c **** { + 210:Src/system_stm32f0xx.c **** #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ + 211:Src/system_stm32f0xx.c **** || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ + 212:Src/system_stm32f0xx.c **** || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + 213:Src/system_stm32f0xx.c **** /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ + 214:Src/system_stm32f0xx.c **** SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; + 215:Src/system_stm32f0xx.c **** #else + 216:Src/system_stm32f0xx.c **** /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ + 217:Src/system_stm32f0xx.c **** SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + 218:Src/system_stm32f0xx.c **** #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || + ARM GAS /tmp/ccjISuh0.s page 6 + + + 219:Src/system_stm32f0xx.c **** STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || + 220:Src/system_stm32f0xx.c **** STM32F091xC || STM32F098xx || STM32F030xC */ + 221:Src/system_stm32f0xx.c **** } + 222:Src/system_stm32f0xx.c **** break; + 223:Src/system_stm32f0xx.c **** default: /* HSI used as system clock */ + 224:Src/system_stm32f0xx.c **** SystemCoreClock = HSI_VALUE; + 71 .loc 1 224 0 + 72 0016 214B ldr r3, .L14+4 + 73 .LVL2: + 74 0018 214A ldr r2, .L14+8 + 75 .LVL3: + 76 001a 1A60 str r2, [r3] + 225:Src/system_stm32f0xx.c **** break; + 77 .loc 1 225 0 + 78 001c 02E0 b .L7 + 79 .LVL4: + 80 .L11: + 184:Src/system_stm32f0xx.c **** break; + 81 .loc 1 184 0 + 82 001e 1F4B ldr r3, .L14+4 + 83 .LVL5: + 84 0020 1F4A ldr r2, .L14+8 + 85 .LVL6: + 86 0022 1A60 str r2, [r3] + 87 .LVL7: + 88 .L7: + 226:Src/system_stm32f0xx.c **** } + 227:Src/system_stm32f0xx.c **** /* Compute HCLK clock frequency ----------------*/ + 228:Src/system_stm32f0xx.c **** /* Get HCLK prescaler */ + 229:Src/system_stm32f0xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + 89 .loc 1 229 0 + 90 0024 1C4B ldr r3, .L14 + 91 0026 5A68 ldr r2, [r3, #4] + 92 0028 1209 lsrs r2, r2, #4 + 93 002a 0F23 movs r3, #15 + 94 002c 1340 ands r3, r2 + 95 002e 1D4A ldr r2, .L14+12 + 96 0030 D35C ldrb r3, [r2, r3] + 97 .LVL8: + 230:Src/system_stm32f0xx.c **** /* HCLK clock frequency */ + 231:Src/system_stm32f0xx.c **** SystemCoreClock >>= tmp; + 98 .loc 1 231 0 + 99 0032 1A4A ldr r2, .L14+4 + 100 0034 1168 ldr r1, [r2] + 101 0036 D940 lsrs r1, r1, r3 + 102 0038 1160 str r1, [r2] + 232:Src/system_stm32f0xx.c **** } + 103 .loc 1 232 0 + 104 @ sp needed + 105 003a 10BD pop {r4, pc} + 106 .LVL9: + 107 .L4: + 187:Src/system_stm32f0xx.c **** break; + 108 .loc 1 187 0 + 109 003c 174B ldr r3, .L14+4 + 110 .LVL10: + 111 003e 184A ldr r2, .L14+8 + ARM GAS /tmp/ccjISuh0.s page 7 + + + 112 .LVL11: + 113 0040 1A60 str r2, [r3] + 188:Src/system_stm32f0xx.c **** case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + 114 .loc 1 188 0 + 115 0042 EFE7 b .L7 + 116 .LVL12: + 117 .L5: + 191:Src/system_stm32f0xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + 118 .loc 1 191 0 + 119 0044 144A ldr r2, .L14 + 120 0046 5068 ldr r0, [r2, #4] + 121 .LVL13: + 192:Src/system_stm32f0xx.c **** pllmull = ( pllmull >> 18) + 2; + 122 .loc 1 192 0 + 123 0048 5368 ldr r3, [r2, #4] + 124 .LVL14: + 125 004a C021 movs r1, #192 + 126 004c 4902 lsls r1, r1, #9 + 127 004e 0B40 ands r3, r1 + 128 .LVL15: + 193:Src/system_stm32f0xx.c **** predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + 129 .loc 1 193 0 + 130 0050 800C lsrs r0, r0, #18 + 131 .LVL16: + 132 0052 0F21 movs r1, #15 + 133 0054 0840 ands r0, r1 + 134 0056 841C adds r4, r0, #2 + 135 .LVL17: + 194:Src/system_stm32f0xx.c **** + 136 .loc 1 194 0 + 137 0058 D26A ldr r2, [r2, #44] + 138 005a 1140 ands r1, r2 + 139 005c 0131 adds r1, r1, #1 + 140 .LVL18: + 196:Src/system_stm32f0xx.c **** { + 141 .loc 1 196 0 + 142 005e 8022 movs r2, #128 + 143 0060 5202 lsls r2, r2, #9 + 144 0062 9342 cmp r3, r2 + 145 0064 0AD0 beq .L12 + 202:Src/system_stm32f0xx.c **** { + 146 .loc 1 202 0 + 147 0066 C022 movs r2, #192 + 148 0068 5202 lsls r2, r2, #9 + 149 006a 9342 cmp r3, r2 + 150 006c 0DD0 beq .L13 + 214:Src/system_stm32f0xx.c **** #else + 151 .loc 1 214 0 + 152 006e 0C48 ldr r0, .L14+8 + 153 0070 FFF7FEFF bl __aeabi_uidiv + 154 .LVL19: + 155 0074 6043 muls r0, r4 + 156 0076 094B ldr r3, .L14+4 + 157 0078 1860 str r0, [r3] + 158 007a D3E7 b .L7 + 159 .LVL20: + 160 .L12: + ARM GAS /tmp/ccjISuh0.s page 8 + + + 199:Src/system_stm32f0xx.c **** } + 161 .loc 1 199 0 + 162 007c 0848 ldr r0, .L14+8 + 163 007e FFF7FEFF bl __aeabi_uidiv + 164 .LVL21: + 165 0082 6043 muls r0, r4 + 166 0084 054B ldr r3, .L14+4 + 167 0086 1860 str r0, [r3] + 168 0088 CCE7 b .L7 + 169 .LVL22: + 170 .L13: + 205:Src/system_stm32f0xx.c **** } + 171 .loc 1 205 0 + 172 008a 0748 ldr r0, .L14+16 + 173 008c FFF7FEFF bl __aeabi_uidiv + 174 .LVL23: + 175 0090 6043 muls r0, r4 + 176 0092 024B ldr r3, .L14+4 + 177 0094 1860 str r0, [r3] + 178 0096 C5E7 b .L7 + 179 .L15: + 180 .align 2 + 181 .L14: + 182 0098 00100240 .word 1073876992 + 183 009c 00000000 .word .LANCHOR0 + 184 00a0 00127A00 .word 8000000 + 185 00a4 00000000 .word .LANCHOR1 + 186 00a8 006CDC02 .word 48000000 + 187 .cfi_endproc + 188 .LFE41: + 190 .global APBPrescTable + 191 .global AHBPrescTable + 192 .global SystemCoreClock + 193 .section .data.SystemCoreClock,"aw",%progbits + 194 .align 2 + 195 .set .LANCHOR0,. + 0 + 198 SystemCoreClock: + 199 0000 00127A00 .word 8000000 + 200 .section .rodata.AHBPrescTable,"a",%progbits + 201 .align 2 + 202 .set .LANCHOR1,. + 0 + 205 AHBPrescTable: + 206 0000 00 .byte 0 + 207 0001 00 .byte 0 + 208 0002 00 .byte 0 + 209 0003 00 .byte 0 + 210 0004 00 .byte 0 + 211 0005 00 .byte 0 + 212 0006 00 .byte 0 + 213 0007 00 .byte 0 + 214 0008 01 .byte 1 + 215 0009 02 .byte 2 + 216 000a 03 .byte 3 + 217 000b 04 .byte 4 + 218 000c 06 .byte 6 + 219 000d 07 .byte 7 + 220 000e 08 .byte 8 + ARM GAS /tmp/ccjISuh0.s page 9 + + + 221 000f 09 .byte 9 + 222 .section .rodata.APBPrescTable,"a",%progbits + 223 .align 2 + 226 APBPrescTable: + 227 0000 00 .byte 0 + 228 0001 00 .byte 0 + 229 0002 00 .byte 0 + 230 0003 00 .byte 0 + 231 0004 01 .byte 1 + 232 0005 02 .byte 2 + 233 0006 03 .byte 3 + 234 0007 04 .byte 4 + 235 .text + 236 .Letext0: + 237 .file 2 "/usr/include/newlib/machine/_default_types.h" + 238 .file 3 "/usr/include/newlib/sys/_stdint.h" + 239 .file 4 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h" + 240 .file 5 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h" + ARM GAS /tmp/ccjISuh0.s page 10 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 system_stm32f0xx.c + /tmp/ccjISuh0.s:16 .text.SystemInit:0000000000000000 $t + /tmp/ccjISuh0.s:23 .text.SystemInit:0000000000000000 SystemInit + /tmp/ccjISuh0.s:39 .text.SystemCoreClockUpdate:0000000000000000 $t + /tmp/ccjISuh0.s:46 .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate + /tmp/ccjISuh0.s:182 .text.SystemCoreClockUpdate:0000000000000098 $d + /tmp/ccjISuh0.s:226 .rodata.APBPrescTable:0000000000000000 APBPrescTable + /tmp/ccjISuh0.s:205 .rodata.AHBPrescTable:0000000000000000 AHBPrescTable + /tmp/ccjISuh0.s:198 .data.SystemCoreClock:0000000000000000 SystemCoreClock + /tmp/ccjISuh0.s:194 .data.SystemCoreClock:0000000000000000 $d + /tmp/ccjISuh0.s:201 .rodata.AHBPrescTable:0000000000000000 $d + /tmp/ccjISuh0.s:223 .rodata.APBPrescTable:0000000000000000 $d + +UNDEFINED SYMBOLS +__aeabi_uidiv diff --git a/bsl/makeLowLayer/cmakeLowLayer.ioc b/bsl/makeLowLayer/cmakeLowLayer.ioc new file mode 100644 index 0000000..6771ed3 --- /dev/null +++ b/bsl/makeLowLayer/cmakeLowLayer.ioc @@ -0,0 +1,69 @@ +#MicroXplorer Configuration settings - do not modify +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.Family=STM32F0 +Mcu.IP0=NVIC +Mcu.IP1=RCC +Mcu.IP2=SYS +Mcu.IPNb=3 +Mcu.Name=STM32F042K(4-6)Tx +Mcu.Package=LQFP32 +Mcu.Pin0=PB3 +Mcu.Pin1=VP_SYS_VS_Systick +Mcu.PinsNb=2 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F042K6Tx +MxCube.Version=6.3.0 +MxDb.Version=DB.6.0.30 +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:3\:0\:false\:false\:true\:false\:true +PB3.GPIOParameters=GPIO_Label +PB3.GPIO_Label=LED_G +PB3.Locked=true +PB3.Signal=GPIO_Output +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F042K6Tx +ProjectManager.FirmwarePackage=STM32Cube FW_F0 V1.11.3 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=cmakeLowLayer.ioc +ProjectManager.ProjectName=cmakeLowLayer +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=Makefile +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-LL-false,2-MX_GPIO_Init-GPIO-false-LL-true +RCC.CECFreq_Value=32786.88524590164 +RCC.FamilyName=M +RCC.HSICECFreq_Value=32786.88524590164 +RCC.IPParameters=CECFreq_Value,FamilyName,HSICECFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,TimSysFreq_Value,VCOOutput2Freq_Value +RCC.PLLCLKFreq_Value=16000000 +RCC.PLLMCOFreq_Value=16000000 +RCC.TimSysFreq_Value=8000000 +RCC.VCOOutput2Freq_Value=8000000 +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom diff --git a/bsl/makeLowLayer/startup_stm32f042x6.s b/bsl/makeLowLayer/startup_stm32f042x6.s new file mode 100644 index 0000000..7bf1334 --- /dev/null +++ b/bsl/makeLowLayer/startup_stm32f042x6.s @@ -0,0 +1,309 @@ +/** + ****************************************************************************** + * @file startup_stm32f042x6.s + * @author MCD Application Team + * @brief STM32F042x4/STM32F042x6 devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/*Check if boot space corresponds to test memory*/ + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + BNE ApplicationStart + + /*SYSCFG clock enable*/ + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + +/*Set CFGR1 register with flash memory remap at address 0*/ + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] + +ApplicationStart: +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_VDDIO2_IRQHandler /* PVD and VDDIO2 through EXTI Line detect */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_CRS_IRQHandler /* RCC and CRS */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word TSC_IRQHandler /* TSC */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* Reserved */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word 0 /* Reserved */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word CEC_CAN_IRQHandler /* CEC and CAN */ + .word USB_IRQHandler /* USB */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_VDDIO2_IRQHandler + .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak CEC_CAN_IRQHandler + .thumb_set CEC_CAN_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +