From c75ab77fd06a6934b82495d47642a9bf14a88c58 Mon Sep 17 00:00:00 2001 From: key Date: Wed, 10 Nov 2021 10:36:04 +0100 Subject: [PATCH] Implmentation of hardwareDefinition.h --- CMakeLists.txt | 5 +- bsl/csl/interfaces/pin.h | 39 +- .../Device/ST/STM32F0xx/Include/stm32f042x6.h | 0 .../Device/ST/STM32F0xx/Include/stm32f0xx.h | 0 .../ST/STM32F0xx/Include/system_stm32f0xx.h | 0 .../{Drivers => }/CMSIS/Include/cmsis_armcc.h | 0 .../CMSIS/Include/cmsis_armclang.h | 0 .../CMSIS/Include/cmsis_compiler.h | 0 .../{Drivers => }/CMSIS/Include/cmsis_gcc.h | 0 .../CMSIS/Include/cmsis_iccarm.h | 0 .../CMSIS/Include/cmsis_version.h | 0 .../CMSIS/Include/core_armv8mbl.h | 0 .../CMSIS/Include/core_armv8mml.h | 0 .../{Drivers => }/CMSIS/Include/core_cm0.h | 0 .../CMSIS/Include/core_cm0plus.h | 0 .../{Drivers => }/CMSIS/Include/core_cm1.h | 0 .../{Drivers => }/CMSIS/Include/core_cm23.h | 0 .../{Drivers => }/CMSIS/Include/core_cm3.h | 0 .../{Drivers => }/CMSIS/Include/core_cm33.h | 0 .../{Drivers => }/CMSIS/Include/core_cm4.h | 0 .../{Drivers => }/CMSIS/Include/core_cm7.h | 0 .../{Drivers => }/CMSIS/Include/core_sc000.h | 0 .../{Drivers => }/CMSIS/Include/core_sc300.h | 0 .../{Drivers => }/CMSIS/Include/mpu_armv7.h | 0 .../{Drivers => }/CMSIS/Include/mpu_armv8.h | 0 .../{Drivers => }/CMSIS/Include/tz_context.h | 0 bsl/csl/stm32f042/CMakeLists.txt | 2 - .../stm32f042/Device/hardwareDescription.h | 101 + bsl/csl/stm32f042/Device/stm32f042x6.h | 10677 ++++++++++++++++ bsl/csl/stm32f042/Device/stm32f0xx.h | 275 + bsl/csl/stm32f042/Device/system_stm32f0xx.h | 104 + bsl/csl/stm32f042/Src/CMakeLists.txt | 1 + bsl/csl/stm32f042/Src/usart.c | 4 +- .../{ => oldSTM}/Drivers/CMakeLists.txt | 0 .../Inc/stm32f0xx_ll_bus.h | 0 .../Inc/stm32f0xx_ll_cortex.h | 0 .../Inc/stm32f0xx_ll_crs.h | 0 .../Inc/stm32f0xx_ll_dma.h | 0 .../Inc/stm32f0xx_ll_exti.h | 0 .../Inc/stm32f0xx_ll_gpio.h | 0 .../Inc/stm32f0xx_ll_pwr.h | 0 .../Inc/stm32f0xx_ll_rcc.h | 0 .../Inc/stm32f0xx_ll_system.h | 0 .../Inc/stm32f0xx_ll_utils.h | 0 .../Src/stm32f0xx_ll_exti.c | 0 .../Src/stm32f0xx_ll_gpio.c | 0 .../Src/stm32f0xx_ll_pwr.c | 0 .../Src/stm32f0xx_ll_rcc.c | 0 .../Src/stm32f0xx_ll_utils.c | 0 bsl/nucleo_f042k6/CMakeLists.txt | 2 +- bsl/nucleo_f042k6/bslConfig.cmake | 8 +- bsl/nucleo_f042k6/bsl_nucleo_f042k6.hpp | 1 - main.cpp | 4 +- 53 files changed, 11172 insertions(+), 51 deletions(-) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/cmsis_armcc.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/cmsis_armclang.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/cmsis_compiler.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/cmsis_gcc.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/cmsis_iccarm.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/cmsis_version.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/core_armv8mbl.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/core_armv8mml.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/core_cm0.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/core_cm0plus.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/core_cm1.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/core_cm23.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/core_cm3.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/core_cm33.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/core_cm4.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/core_cm7.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/core_sc000.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/core_sc300.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/mpu_armv7.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/mpu_armv8.h (100%) rename bsl/csl/stm32f042/{Drivers => }/CMSIS/Include/tz_context.h (100%) create mode 100644 bsl/csl/stm32f042/Device/hardwareDescription.h create mode 100644 bsl/csl/stm32f042/Device/stm32f042x6.h create mode 100644 bsl/csl/stm32f042/Device/stm32f0xx.h create mode 100644 bsl/csl/stm32f042/Device/system_stm32f0xx.h rename bsl/csl/stm32f042/{ => oldSTM}/Drivers/CMakeLists.txt (100%) rename bsl/csl/stm32f042/{ => oldSTM}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h (100%) rename bsl/csl/stm32f042/{ => oldSTM}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h (100%) rename bsl/csl/stm32f042/{ => oldSTM}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h (100%) rename bsl/csl/stm32f042/{ => oldSTM}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h (100%) rename bsl/csl/stm32f042/{ => oldSTM}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h (100%) rename bsl/csl/stm32f042/{ => oldSTM}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h (100%) rename bsl/csl/stm32f042/{ => oldSTM}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h (100%) rename bsl/csl/stm32f042/{ => oldSTM}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h (100%) rename bsl/csl/stm32f042/{ => oldSTM}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h (100%) rename bsl/csl/stm32f042/{ => oldSTM}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h (100%) rename bsl/csl/stm32f042/{ => oldSTM}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c (100%) rename bsl/csl/stm32f042/{ => oldSTM}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c (100%) rename bsl/csl/stm32f042/{ => oldSTM}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c (100%) rename bsl/csl/stm32f042/{ => oldSTM}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c (100%) rename bsl/csl/stm32f042/{ => oldSTM}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c (100%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 3df1212..bd0d827 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -17,7 +17,7 @@ include(${COMPILER_DEFS}) project(${BSL_USED} ASM C CXX) #do this intead sf declaring languages in the beginning it will prevent loop errors. set(CMAKE_VERBOSE_MAKEFILE off) #Shoul make print everythign ?? -set(EXECUTABLE ${PROJECT_NAME}) #Create the executable +set(EXECUTABLE ${PROJECT_NAME}) #Create the executable #################################################################################################### #CONFIG FILE @@ -42,7 +42,7 @@ message("${Blue} |--> Libs used\t\t: ${EXTRA_LIBS} ${ColourReset}") #################################################################################################### #EXECUTABLE #################################################################################################### -add_executable(${EXECUTABLE} main.c) +add_executable(${EXECUTABLE} main.cpp) target_compile_options(${EXECUTABLE} PRIVATE ${CPP_FLAGS}) target_compile_definitions(${EXECUTABLE} PRIVATE ${CPP_DEFS}) target_include_directories(${EXECUTABLE} PUBLIC ${CPP_INCLUDES}) @@ -57,6 +57,7 @@ if(IS_NO_SYS) target_link_libraries(${EXECUTABLE} ${EXTRA_LIBS}) target_link_options(${EXECUTABLE} PRIVATE ${LINKER_FLAGS}) else () + message("${Cyan}Using systems linker ${ColourReset}") target_link_libraries(${EXECUTABLE} ${EXTRA_LIBS}) endif() diff --git a/bsl/csl/interfaces/pin.h b/bsl/csl/interfaces/pin.h index 9a6438c..76e7283 100644 --- a/bsl/csl/interfaces/pin.h +++ b/bsl/csl/interfaces/pin.h @@ -29,44 +29,7 @@ extern "C" { #endif #include - -#ifdef ARM_MCU - /*! Enum of the awailable pins for this package */ - - #include "stm32f042x6.h" - typedef enum - { - // NAME = BASE ADDR | PORT | PIN NO - pinA0 = GPIOA_BASE | 0x00 | 0, /*!< Port: A Pin: 0 -> GPIOA_BASE | Port A Mask | Pin Mask */ - pinA1 = GPIOA_BASE | 0x00 | 1, /*!< Port: A Pin: 1 -> GPIOA_BASE | Port A Mask | Pin Mask */ - pinA2 = GPIOA_BASE | 0x00 | 2, /*!< Port: A Pin: 2 -> GPIOA_BASE | Port A Mask | Pin Mask */ - pinA3 = GPIOA_BASE | 0x00 | 3, /*!< Port: A Pin: 3 -> GPIOA_BASE | Port A Mask | Pin Mask */ - pinA4 = GPIOA_BASE | 0x00 | 4, /*!< Port: A Pin: 4 -> GPIOA_BASE | Port A Mask | Pin Mask */ - pinA5 = GPIOA_BASE | 0x00 | 5, /*!< Port: A Pin: 5 -> GPIOA_BASE | Port A Mask | Pin Mask */ - pinA6 = GPIOA_BASE | 0x00 | 6, /*!< Port: A Pin: 6 -> GPIOA_BASE | Port A Mask | Pin Mask */ - pinA7 = GPIOA_BASE | 0x00 | 7, /*!< Port: A Pin: 7 -> GPIOA_BASE | Port A Mask | Pin Mask */ - pinA8 = GPIOA_BASE | 0x00 | 8, /*!< Port: A Pin: 8 -> GPIOA_BASE | Port A Mask | Pin Mask */ - pinA9 = GPIOA_BASE | 0x00 | 9, /*!< Port: A Pin: 9 -> GPIOA_BASE | Port A Mask | Pin Mask */ - pinA10 = GPIOA_BASE | 0x00 | 10,/*!< Port: A Pin: 10 -> GPIOA_BASE | Port A Mask | Pin Mask */ - pinA11 = GPIOA_BASE | 0x00 | 11,/*!< Port: A Pin: 11 -> GPIOA_BASE | Port A Mask | Pin Mask */ - pinA12 = GPIOA_BASE | 0x00 | 12,/*!< Port: A Pin: 12 -> GPIOA_BASE | Port A Mask | Pin Mask */ - pinA13 = GPIOA_BASE | 0x00 | 13,/*!< Port: A Pin: 13 -> GPIOA_BASE | Port A Mask | Pin Mask */ - pinA14 = GPIOA_BASE | 0x00 | 14,/*!< Port: A Pin: 14 -> GPIOA_BASE | Port A Mask | Pin Mask */ - pinA15 = GPIOA_BASE | 0x00 | 15,/*!< Port: A Pin: 15 -> GPIOA_BASE | Port A Mask | Pin Mask */ - - pinB0 = GPIOB_BASE | 0x10 | 0, /*!< Port: B Pin: 0 -> GPIOB_BASE | Port B Mask | Pin Mask */ - pinB1 = GPIOB_BASE | 0x10 | 1, /*!< Port: B Pin: 1 -> GPIOB_BASE | Port B Mask | Pin Mask */ - pinB3 = GPIOB_BASE | 0x10 | 3, /*!< Port: B Pin: 3 -> GPIOB_BASE | Port B Mask | Pin Mask */ - pinB4 = GPIOB_BASE | 0x10 | 4, /*!< Port: B Pin: 4 -> GPIOB_BASE | Port B Mask | Pin Mask */ - pinB5 = GPIOB_BASE | 0x10 | 5, /*!< Port: B Pin: 5 -> GPIOB_BASE | Port B Mask | Pin Mask */ - pinB6 = GPIOB_BASE | 0x10 | 6, /*!< Port: B Pin: 6 -> GPIOB_BASE | Port B Mask | Pin Mask */ - pinB7 = GPIOB_BASE | 0x10 | 7, /*!< Port: B Pin: 7 -> GPIOB_BASE | Port B Mask | Pin Mask */ - pinB8 = GPIOB_BASE | 0x10 | 8, /*!< Port: B Pin: 8 -> GPIOB_BASE | Port B Mask | Pin Mask */ - - pinF0 = GPIOF_BASE | 0x20 | 0, /*!< Port: F Pin: 0 -> GPIOF_BASE | Port F Mask | Pin Mask */ - pinF1 = GPIOF_BASE | 0x20 | 1 /*!< Port: F Pin: 1 -> GPIOF_BASE | Port F Mask | Pin Mask */ - }pinNo_t; -#endif +#include "hardwareDescription.h" #ifdef RASPBERRY #endif diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h b/bsl/csl/stm32f042/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h rename to bsl/csl/stm32f042/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h b/bsl/csl/stm32f042/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h rename to bsl/csl/stm32f042/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h b/bsl/csl/stm32f042/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h rename to bsl/csl/stm32f042/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/cmsis_armcc.h b/bsl/csl/stm32f042/CMSIS/Include/cmsis_armcc.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/cmsis_armcc.h rename to bsl/csl/stm32f042/CMSIS/Include/cmsis_armcc.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/cmsis_armclang.h b/bsl/csl/stm32f042/CMSIS/Include/cmsis_armclang.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/cmsis_armclang.h rename to bsl/csl/stm32f042/CMSIS/Include/cmsis_armclang.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/cmsis_compiler.h b/bsl/csl/stm32f042/CMSIS/Include/cmsis_compiler.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/cmsis_compiler.h rename to bsl/csl/stm32f042/CMSIS/Include/cmsis_compiler.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/cmsis_gcc.h b/bsl/csl/stm32f042/CMSIS/Include/cmsis_gcc.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/cmsis_gcc.h rename to bsl/csl/stm32f042/CMSIS/Include/cmsis_gcc.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/cmsis_iccarm.h b/bsl/csl/stm32f042/CMSIS/Include/cmsis_iccarm.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/cmsis_iccarm.h rename to bsl/csl/stm32f042/CMSIS/Include/cmsis_iccarm.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/cmsis_version.h b/bsl/csl/stm32f042/CMSIS/Include/cmsis_version.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/cmsis_version.h rename to bsl/csl/stm32f042/CMSIS/Include/cmsis_version.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/core_armv8mbl.h b/bsl/csl/stm32f042/CMSIS/Include/core_armv8mbl.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/core_armv8mbl.h rename to bsl/csl/stm32f042/CMSIS/Include/core_armv8mbl.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/core_armv8mml.h b/bsl/csl/stm32f042/CMSIS/Include/core_armv8mml.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/core_armv8mml.h rename to bsl/csl/stm32f042/CMSIS/Include/core_armv8mml.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/core_cm0.h b/bsl/csl/stm32f042/CMSIS/Include/core_cm0.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/core_cm0.h rename to bsl/csl/stm32f042/CMSIS/Include/core_cm0.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/core_cm0plus.h b/bsl/csl/stm32f042/CMSIS/Include/core_cm0plus.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/core_cm0plus.h rename to bsl/csl/stm32f042/CMSIS/Include/core_cm0plus.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/core_cm1.h b/bsl/csl/stm32f042/CMSIS/Include/core_cm1.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/core_cm1.h rename to bsl/csl/stm32f042/CMSIS/Include/core_cm1.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/core_cm23.h b/bsl/csl/stm32f042/CMSIS/Include/core_cm23.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/core_cm23.h rename to bsl/csl/stm32f042/CMSIS/Include/core_cm23.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/core_cm3.h b/bsl/csl/stm32f042/CMSIS/Include/core_cm3.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/core_cm3.h rename to bsl/csl/stm32f042/CMSIS/Include/core_cm3.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/core_cm33.h b/bsl/csl/stm32f042/CMSIS/Include/core_cm33.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/core_cm33.h rename to bsl/csl/stm32f042/CMSIS/Include/core_cm33.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/core_cm4.h b/bsl/csl/stm32f042/CMSIS/Include/core_cm4.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/core_cm4.h rename to bsl/csl/stm32f042/CMSIS/Include/core_cm4.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/core_cm7.h b/bsl/csl/stm32f042/CMSIS/Include/core_cm7.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/core_cm7.h rename to bsl/csl/stm32f042/CMSIS/Include/core_cm7.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/core_sc000.h b/bsl/csl/stm32f042/CMSIS/Include/core_sc000.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/core_sc000.h rename to bsl/csl/stm32f042/CMSIS/Include/core_sc000.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/core_sc300.h b/bsl/csl/stm32f042/CMSIS/Include/core_sc300.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/core_sc300.h rename to bsl/csl/stm32f042/CMSIS/Include/core_sc300.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/mpu_armv7.h b/bsl/csl/stm32f042/CMSIS/Include/mpu_armv7.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/mpu_armv7.h rename to bsl/csl/stm32f042/CMSIS/Include/mpu_armv7.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/mpu_armv8.h b/bsl/csl/stm32f042/CMSIS/Include/mpu_armv8.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/mpu_armv8.h rename to bsl/csl/stm32f042/CMSIS/Include/mpu_armv8.h diff --git a/bsl/csl/stm32f042/Drivers/CMSIS/Include/tz_context.h b/bsl/csl/stm32f042/CMSIS/Include/tz_context.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMSIS/Include/tz_context.h rename to bsl/csl/stm32f042/CMSIS/Include/tz_context.h diff --git a/bsl/csl/stm32f042/CMakeLists.txt b/bsl/csl/stm32f042/CMakeLists.txt index 26e056c..48a05bf 100644 --- a/bsl/csl/stm32f042/CMakeLists.txt +++ b/bsl/csl/stm32f042/CMakeLists.txt @@ -1,5 +1,3 @@ -project(Csl_Stm32f0xx ASM C CXX) # do this intead sf declaring languages in the beginning it will prevent loop errors. - #################################################################################################### #SUBDIRECTORIES #################################################################################################### diff --git a/bsl/csl/stm32f042/Device/hardwareDescription.h b/bsl/csl/stm32f042/Device/hardwareDescription.h new file mode 100644 index 0000000..6a9250e --- /dev/null +++ b/bsl/csl/stm32f042/Device/hardwareDescription.h @@ -0,0 +1,101 @@ +/*! Enum of the awailable pins for this package */ +#include "stm32f042x6.h" +typedef enum +{ +// NAME = BASE ADDR | PORT | PIN NO + pinA0 = GPIOA_BASE | 0x00 | 0, /*!< Port: A Pin: 0 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA1 = GPIOA_BASE | 0x00 | 1, /*!< Port: A Pin: 1 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA2 = GPIOA_BASE | 0x00 | 2, /*!< Port: A Pin: 2 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA3 = GPIOA_BASE | 0x00 | 3, /*!< Port: A Pin: 3 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA4 = GPIOA_BASE | 0x00 | 4, /*!< Port: A Pin: 4 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA5 = GPIOA_BASE | 0x00 | 5, /*!< Port: A Pin: 5 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA6 = GPIOA_BASE | 0x00 | 6, /*!< Port: A Pin: 6 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA7 = GPIOA_BASE | 0x00 | 7, /*!< Port: A Pin: 7 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA8 = GPIOA_BASE | 0x00 | 8, /*!< Port: A Pin: 8 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA9 = GPIOA_BASE | 0x00 | 9, /*!< Port: A Pin: 9 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA10 = GPIOA_BASE | 0x00 | 10,/*!< Port: A Pin: 10 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA11 = GPIOA_BASE | 0x00 | 11,/*!< Port: A Pin: 11 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA12 = GPIOA_BASE | 0x00 | 12,/*!< Port: A Pin: 12 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA13 = GPIOA_BASE | 0x00 | 13,/*!< Port: A Pin: 13 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA14 = GPIOA_BASE | 0x00 | 14,/*!< Port: A Pin: 14 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA15 = GPIOA_BASE | 0x00 | 15,/*!< Port: A Pin: 15 -> GPIOA_BASE | Port A Mask | Pin Mask */ + + pinB0 = GPIOB_BASE | 0x10 | 0, /*!< Port: B Pin: 0 -> GPIOB_BASE | Port B Mask | Pin Mask */ + pinB1 = GPIOB_BASE | 0x10 | 1, /*!< Port: B Pin: 1 -> GPIOB_BASE | Port B Mask | Pin Mask */ + pinB3 = GPIOB_BASE | 0x10 | 3, /*!< Port: B Pin: 3 -> GPIOB_BASE | Port B Mask | Pin Mask */ + pinB4 = GPIOB_BASE | 0x10 | 4, /*!< Port: B Pin: 4 -> GPIOB_BASE | Port B Mask | Pin Mask */ + pinB5 = GPIOB_BASE | 0x10 | 5, /*!< Port: B Pin: 5 -> GPIOB_BASE | Port B Mask | Pin Mask */ + pinB6 = GPIOB_BASE | 0x10 | 6, /*!< Port: B Pin: 6 -> GPIOB_BASE | Port B Mask | Pin Mask */ + pinB7 = GPIOB_BASE | 0x10 | 7, /*!< Port: B Pin: 7 -> GPIOB_BASE | Port B Mask | Pin Mask */ + pinB8 = GPIOB_BASE | 0x10 | 8, /*!< Port: B Pin: 8 -> GPIOB_BASE | Port B Mask | Pin Mask */ + + pinF0 = GPIOF_BASE | 0x20 | 0, /*!< Port: F Pin: 0 -> GPIOF_BASE | Port F Mask | Pin Mask */ + pinF1 = GPIOF_BASE | 0x20 | 1 /*!< Port: F Pin: 1 -> GPIOF_BASE | Port F Mask | Pin Mask */ +}pinNo_t; + +#ifdef something +typedef enum +{ +// NAME = | PORT | PIN NO + pinA0 = 0x00 | 0 , /*!< Port: A Pin: 0 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA1 = GPIOA_BASE | 0x00 | 1, /*!< Port: A Pin: 1 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA2 = GPIOA_BASE | 0x00 | 2, /*!< Port: A Pin: 2 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA3 = GPIOA_BASE | 0x00 | 3, /*!< Port: A Pin: 3 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA4 = GPIOA_BASE | 0x00 | 4, /*!< Port: A Pin: 4 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA5 = GPIOA_BASE | 0x00 | 5, /*!< Port: A Pin: 5 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA6 = GPIOA_BASE | 0x00 | 6, /*!< Port: A Pin: 6 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA7 = GPIOA_BASE | 0x00 | 7, /*!< Port: A Pin: 7 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA8 = GPIOA_BASE | 0x00 | 8, /*!< Port: A Pin: 8 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA9 = GPIOA_BASE | 0x00 | 9, /*!< Port: A Pin: 9 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA10 = GPIOA_BASE | 0x00 | 10,/*!< Port: A Pin: 10 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA11 = GPIOA_BASE | 0x00 | 11,/*!< Port: A Pin: 11 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA12 = GPIOA_BASE | 0x00 | 12,/*!< Port: A Pin: 12 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA13 = GPIOA_BASE | 0x00 | 13,/*!< Port: A Pin: 13 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA14 = GPIOA_BASE | 0x00 | 14,/*!< Port: A Pin: 14 -> GPIOA_BASE | Port A Mask | Pin Mask */ + pinA15 = GPIOA_BASE | 0x00 | 15,/*!< Port: A Pin: 15 -> GPIOA_BASE | Port A Mask | Pin Mask */ + + pinB0 = GPIOB_BASE | 0x10 | 0, /*!< Port: B Pin: 0 -> GPIOB_BASE | Port B Mask | Pin Mask */ + pinB1 = GPIOB_BASE | 0x10 | 1, /*!< Port: B Pin: 1 -> GPIOB_BASE | Port B Mask | Pin Mask */ + pinB3 = GPIOB_BASE | 0x10 | 3, /*!< Port: B Pin: 3 -> GPIOB_BASE | Port B Mask | Pin Mask */ + pinB4 = GPIOB_BASE | 0x10 | 4, /*!< Port: B Pin: 4 -> GPIOB_BASE | Port B Mask | Pin Mask */ + pinB5 = GPIOB_BASE | 0x10 | 5, /*!< Port: B Pin: 5 -> GPIOB_BASE | Port B Mask | Pin Mask */ + pinB6 = GPIOB_BASE | 0x10 | 6, /*!< Port: B Pin: 6 -> GPIOB_BASE | Port B Mask | Pin Mask */ + pinB7 = GPIOB_BASE | 0x10 | 7, /*!< Port: B Pin: 7 -> GPIOB_BASE | Port B Mask | Pin Mask */ + pinB8 = GPIOB_BASE | 0x10 | 8, /*!< Port: B Pin: 8 -> GPIOB_BASE | Port B Mask | Pin Mask */ + + pinF0 = GPIOF_BASE | 0x20 | 0, /*!< Port: F Pin: 0 -> GPIOF_BASE | Port F Mask | Pin Mask */ + pinF1 = GPIOF_BASE | 0x20 | 1 /*!< Port: F Pin: 1 -> GPIOF_BASE | Port F Mask | Pin Mask */ +}newpinNo_t; + + + +#define MAX_NO_ALT_PER_PIN 8 + +// 1 for available 0 for Prohibioted (blank) +static const uint8_t pinAltList[3][15] = { + {0b0111000, 0b11110000, }, + {...}, + {...} +}; + +static const uint32_t PortBase_Addr_List[3] = {GPIOA_BASE, GPIOB_BASE, GPIOF_BASE}; + +void setAlt(pin_no_t id, uint8_t af) +{ + // check for index overshoot + assert(MAX_NO_ALT_PER_PIN < af); + + // fail if list entry returns 0 + //assert(pinAltList[((id & 0xF0) >> 4)][id & 0x0F]) != 0); + + // setup alt function here... + + +} + +#endif + + + + + diff --git a/bsl/csl/stm32f042/Device/stm32f042x6.h b/bsl/csl/stm32f042/Device/stm32f042x6.h new file mode 100644 index 0000000..23e125c --- /dev/null +++ b/bsl/csl/stm32f042/Device/stm32f042x6.h @@ -0,0 +1,10677 @@ +/** + ****************************************************************************** + * @file stm32f042x6.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F0xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f042x6 + * @{ + */ + +#ifndef __STM32F042x6_H +#define __STM32F042x6_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M0 Processor and Core Peripherals + */ +#define __CM0_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ +#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F0xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** STM32F0 specific Interrupt Numbers ******************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupt through EXTI Lines 16 and 31 */ + RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */ + TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */ + ADC1_IRQn = 12, /*!< ADC1 Interrupt */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ + USART2_IRQn = 28, /*!< USART2 global Interrupt */ + CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */ + USB_IRQn = 31 /*!< USB global Interrupt & EXTI Line18 Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_stm32f0xx.h" /* STM32F0xx System Header */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +}CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +}CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +}CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[14]; /*!< CAN Filter Register, Address offset: 0x240-0x2AC */ +}CAN_TypeDef; + +/** + * @brief HDMI-CEC + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +}CRS_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx + * @{ + */ + +#ifndef __STM32F0xx_H +#define __STM32F0xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F0) +#define STM32F0 +#endif /* STM32F0 */ + +/** Uncomment the line below according to the target STM32 device used in your application. + * stm32f0xxxx.h file contains: + * - All the peripheral register's definitions, bits definitions and memory mapping for STM32F0xxxx devices + * - IRQ channel definition + * - Peripheral memory mapping and physical registers address definition + * - Peripheral pointer declaration and driver header file inclusion + * - Product miscellaneous configuration: assert macros… + * Note: These CMSIS drivers (stm32f0xxxx.h) are always supporting features of the sub-family’s superset. + */ + +#if !defined (STM32F030x6) && !defined (STM32F030x8) && \ + !defined (STM32F031x6) && !defined (STM32F038xx) && \ + !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \ + !defined (STM32F051x8) && !defined (STM32F058xx) && \ + !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \ + !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC) + /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */ + /* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */ + /* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F048xx */ /*!< STM32F048xx Devices (STM32F048xx microcontrollers where the Flash memory is 32 Kbytes) */ + /* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */ + /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */ + /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */ + /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */ + /* #define STM32F091xC */ /*!< STM32F091xB, STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory ranges between 128 and 256 Kbytes) */ + /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */ +#endif +/* Legacy aliases */ +#if defined (STM32F048x6) + #define STM32F048xx +#endif /* STM32F048x6 */ + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.3.6 + */ +#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x06) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ + |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ + |(__STM32F0_DEVICE_VERSION_SUB2 << 8 )\ + |(__STM32F0_DEVICE_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F030x6) + #include "stm32f030x6.h" +#elif defined(STM32F030x8) + #include "stm32f030x8.h" +#elif defined(STM32F031x6) + #include "stm32f031x6.h" +#elif defined(STM32F038xx) + #include "stm32f038xx.h" +#elif defined(STM32F042x6) + #include "stm32f042x6.h" +#elif defined(STM32F048xx) + #include "stm32f048xx.h" +#elif defined(STM32F051x8) + #include "stm32f051x8.h" +#elif defined(STM32F058xx) + #include "stm32f058xx.h" +#elif defined(STM32F070x6) + #include "stm32f070x6.h" +#elif defined(STM32F070xB) + #include "stm32f070xb.h" +#elif defined(STM32F071xB) + #include "stm32f071xb.h" +#elif defined(STM32F072xB) + #include "stm32f072xb.h" +#elif defined(STM32F078xx) + #include "stm32f078xx.h" +#elif defined(STM32F091xC) + #include "stm32f091xc.h" +#elif defined(STM32F098xx) + #include "stm32f098xx.h" +#elif defined(STM32F030xC) + #include "stm32f030xc.h" +#else + #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0U, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0U, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0U, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/* Use of interrupt control for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + SET_BIT((REG), (BIT)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + CLEAR_BIT((REG), (BIT)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \ + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \ + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f0xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F0xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/csl/stm32f042/Device/system_stm32f0xx.h b/bsl/csl/stm32f042/Device/system_stm32f0xx.h new file mode 100644 index 0000000..3d6afd2 --- /dev/null +++ b/bsl/csl/stm32f042/Device/system_stm32f0xx.h @@ -0,0 +1,104 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F0XX_H +#define __SYSTEM_STM32F0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F0xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 3) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) by calling HAL API function HAL_RCC_ClockConfig() + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F0XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsl/csl/stm32f042/Src/CMakeLists.txt b/bsl/csl/stm32f042/Src/CMakeLists.txt index e0962a8..e325d80 100644 --- a/bsl/csl/stm32f042/Src/CMakeLists.txt +++ b/bsl/csl/stm32f042/Src/CMakeLists.txt @@ -22,3 +22,4 @@ target_compile_options(stmInit PRIVATE ${C_FLAGS}) target_compile_definitions(stmInit PRIVATE ${C_DEFS}) target_include_directories(stmInit PUBLIC ${INTERFACES_DIR} ${CSL_INCLUDES}) add_library(sub::init ALIAS stmInit) + diff --git a/bsl/csl/stm32f042/Src/usart.c b/bsl/csl/stm32f042/Src/usart.c index de4e6d3..c86f12b 100644 --- a/bsl/csl/stm32f042/Src/usart.c +++ b/bsl/csl/stm32f042/Src/usart.c @@ -20,8 +20,8 @@ ************************************************************************************************** */ -#include"usart.h" -#include"pin.h" +#include "usart.h" +#include "pin.h" #include "stm32f042x6.h" diff --git a/bsl/csl/stm32f042/Drivers/CMakeLists.txt b/bsl/csl/stm32f042/oldSTM/Drivers/CMakeLists.txt similarity index 100% rename from bsl/csl/stm32f042/Drivers/CMakeLists.txt rename to bsl/csl/stm32f042/oldSTM/Drivers/CMakeLists.txt diff --git a/bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h b/bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h rename to bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h diff --git a/bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h b/bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h rename to bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h diff --git a/bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h b/bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h rename to bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h diff --git a/bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h b/bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h rename to bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h diff --git a/bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h b/bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h rename to bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h diff --git a/bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h b/bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h rename to bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h diff --git a/bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h b/bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h rename to bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h diff --git a/bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h b/bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h rename to bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h diff --git a/bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h b/bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h rename to bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h diff --git a/bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h b/bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h similarity index 100% rename from bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h rename to bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h diff --git a/bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c b/bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c similarity index 100% rename from bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c rename to bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c diff --git a/bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c b/bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c similarity index 100% rename from bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c rename to bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c diff --git a/bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c b/bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c similarity index 100% rename from bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c rename to bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c diff --git a/bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c b/bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c similarity index 100% rename from bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c rename to bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c diff --git a/bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c b/bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c similarity index 100% rename from bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c rename to bsl/csl/stm32f042/oldSTM/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c diff --git a/bsl/nucleo_f042k6/CMakeLists.txt b/bsl/nucleo_f042k6/CMakeLists.txt index c824001..5b23dd6 100644 --- a/bsl/nucleo_f042k6/CMakeLists.txt +++ b/bsl/nucleo_f042k6/CMakeLists.txt @@ -2,6 +2,6 @@ add_library(stmTranslator bsl_nucleo_f042k6.cpp) target_compile_options(stmTranslator PRIVATE ${C_FLAGS}) target_compile_definitions(stmTranslator PRIVATE ${C_DEFS}) -target_include_directories(stmTranslator PUBLIC ${CMAKE_CURRENT_SOURCE_DIR} ${CSL_INCLUDES}) +target_include_directories(stmTranslator PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}) add_library(sub::translator ALIAS stmTranslator) diff --git a/bsl/nucleo_f042k6/bslConfig.cmake b/bsl/nucleo_f042k6/bslConfig.cmake index 5d1d509..ed4a459 100644 --- a/bsl/nucleo_f042k6/bslConfig.cmake +++ b/bsl/nucleo_f042k6/bslConfig.cmake @@ -24,10 +24,10 @@ set(CLS_USED ${CMAKE_SOURCE_DIR}/bsl/csl/stm32f042) #################################################################################################### set(CSL_INCLUDES - ${CMAKE_SOURCE_DIR}/bsl/csl/stm32f042/Inc - ${CMAKE_SOURCE_DIR}/bsl/csl/stm32f042/Drivers/CMSIS/Include - ${CMAKE_SOURCE_DIR}/bsl/csl/stm32f042/Drivers/CMSIS/Device/ST/STM32F0xx/Include - ${CMAKE_SOURCE_DIR}/bsl/csl/stm32f042/Drivers/STM32F0xx_HAL_Driver/Inc) + # ${CMAKE_SOURCE_DIR}/bsl/csl/stm32f042/Inc + ${CMAKE_SOURCE_DIR}/bsl/csl/stm32f042/CMSIS/Include + #${CMAKE_SOURCE_DIR}/bsl/csl/stm32f042/Drivers/CMSIS/Device/ST/STM32F0xx/Include + ${CMAKE_SOURCE_DIR}/bsl/csl/stm32f042/Device) # For flags please check https://manned.org/arm-none-eabi-gcc/34fd6095 set(C_FLAGS diff --git a/bsl/nucleo_f042k6/bsl_nucleo_f042k6.hpp b/bsl/nucleo_f042k6/bsl_nucleo_f042k6.hpp index 3b5a050..de5e9b9 100644 --- a/bsl/nucleo_f042k6/bsl_nucleo_f042k6.hpp +++ b/bsl/nucleo_f042k6/bsl_nucleo_f042k6.hpp @@ -1,7 +1,6 @@ #ifndef BSL_NUCLEO_F042K6_H #define BSL_NUCLEO_F042K6_H -#include "../csl/interfaces/pin.h" class Nucleo_f042k6 { diff --git a/main.cpp b/main.cpp index 2b5c4c0..4b73425 100644 --- a/main.cpp +++ b/main.cpp @@ -29,7 +29,7 @@ int main(int argc, char *argv[]) noFlowControl); //clears screen and send the wellcome messgae - print_Usart(usart2, ASCII_clear); +// print_Usart(usart2, ASCII_clear); print_Usart(usart2, const_cast("Wellcome to our KED project\n\r")); @@ -68,6 +68,7 @@ int main(int argc, char *argv[]) //test if the gpio port works as an input +/* if(pinRead(pinA0) && !latch_old) { pinWrite(pinB3,1); @@ -76,6 +77,7 @@ int main(int argc, char *argv[]) { pinWrite(pinB3,0); } + */ delayMs(100); } return 1;