diff --git a/bsl/csl/interfaces/delay.h b/bsl/csl/interfaces/delay.h index 83d1812..6d40cc8 100644 --- a/bsl/csl/interfaces/delay.h +++ b/bsl/csl/interfaces/delay.h @@ -7,7 +7,6 @@ extern "C" { #include #include "../stm32f042/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h" -void delayInitMs(uint32_t clk, uint32_t ticks); void delayMs(uint16_t delay); diff --git a/bsl/csl/interfaces/deviceSetup.h b/bsl/csl/interfaces/deviceSetup.h new file mode 100644 index 0000000..2790d6c --- /dev/null +++ b/bsl/csl/interfaces/deviceSetup.h @@ -0,0 +1,22 @@ +#ifndef _DEVICE_SETUP_H_ +#define _DEVICE_SETUP_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +void setupInit(); +void setupClock(); +void setupBus(); +void setupPower(); +void setupMemory(); +void delayInitMs(uint32_t clk, uint32_t ticks); + + +#ifdef __cplusplus +} +#endif + +#endif /* _DEVICE_SETUP_H_ */ diff --git a/bsl/csl/stm32f042/Src/CMakeLists.txt b/bsl/csl/stm32f042/Src/CMakeLists.txt index b5fb86b..aaacca0 100644 --- a/bsl/csl/stm32f042/Src/CMakeLists.txt +++ b/bsl/csl/stm32f042/Src/CMakeLists.txt @@ -31,3 +31,9 @@ target_compile_options(stmUsart PRIVATE ${C_FLAGS}) target_compile_definitions(stmUsart PRIVATE ${C_DEFS}) target_include_directories(stmUsart PUBLIC ${INTERFACES_DIR} ${CSL_INCLUDES}) add_library(sub::usart ALIAS stmUsart) + +add_library(stmInit deviceSetup.c) +target_compile_options(stmInit PRIVATE ${C_FLAGS}) +target_compile_definitions(stmInit PRIVATE ${C_DEFS}) +target_include_directories(stmInit PUBLIC ${INTERFACES_DIR} ${CSL_INCLUDES}) +add_library(sub::init ALIAS stmInit) diff --git a/bsl/csl/stm32f042/Src/delay.c b/bsl/csl/stm32f042/Src/delay.c index fa4f7af..8181c14 100644 --- a/bsl/csl/stm32f042/Src/delay.c +++ b/bsl/csl/stm32f042/Src/delay.c @@ -1,12 +1,5 @@ #include "delay.h" -void delayInitMs(uint32_t clk, uint32_t ticks) -{ - /* Configure the SysTick to have interrupt in 1ms time base */ - SysTick->LOAD = (uint32_t)((clk / ticks) - 1UL); /* set reload register */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ -} void delayMs(uint16_t delay) { diff --git a/bsl/csl/stm32f042/Src/deviceSetup.c b/bsl/csl/stm32f042/Src/deviceSetup.c new file mode 100644 index 0000000..1909dcf --- /dev/null +++ b/bsl/csl/stm32f042/Src/deviceSetup.c @@ -0,0 +1,100 @@ +#include"deviceSetup.h" +#include "../stm32f042/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h" + + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) +#define READ_BIT(REG, BIT) ((REG) & (BIT)) +#define CLEAR_REG(REG) ((REG) = (0x0)) +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) +#define READ_REG(REG) ((REG)) +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) +// FLASH->ACR = (((FLASH->ACR) & (~(FLASH_ACR_LATENCY))) | 0) +#define SYS_CLK 8000000 + + +void setupInit() +{ + setupBus(); + setupMemory(); + setupClock(); + setupPower(); + delayInitMs(SYS_CLK, 1000); +} + +void setupClock() +{ + uint8_t check = 1; + /*Sets the clock source to internal clock*/ + RCC->CR |= RCC_CR_HSION; + + /* Wait till HSI is ready */ + while(check) + { + if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) + { + check = 0; + } + } + + /** + * @brief Set HSI Calibration trimming + * @note Default value is 16, which, when added to the HSICAL value, + * @param Value between Min_Data = 0x00 and Max_Data = 0x1F + */ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM_Msk, 16 << RCC_CR_HSITRIM_Pos) ; + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_CFGR_HPRE_DIV1); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_CFGR_PPRE_DIV1); + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_HSI); + + /* Wait till System clock is ready */ + while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI){} +} + +void setupBus() +{ + volatile uint32_t tmpreg; + /*Bit 0 SYSCFGCOMPEN: SYSCFG & COMP clock enable*/ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); + + /*Bit 28 PWREN: Power interface clock enable*/ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); + + (void)tmpreg; + +} + +void setupPower() +{ + +} + +void setupMemory() +{ + /* Bits 2:0 LATENCY[2:0]: Latency + * These bits represent the ratio of the SYSCLK (system clock) period to the Flash access time. + * 000: Zero wait state, if SYSCLK ≤ 24 MHz + * 001: One wait state, if 24 MHz < SYSCLK ≤ 48 MHz*/ + if(SYS_CLK <= 24000000) + { + FLASH->ACR = (((FLASH->ACR) & (~(FLASH_ACR_LATENCY_Msk))) | 0); + while( (FLASH->ACR) & (FLASH_ACR_LATENCY_Msk) != 0){} + } + else + { + FLASH->ACR = (((FLASH->ACR) & (~(FLASH_ACR_LATENCY_Msk))) | 1); + while( (FLASH->ACR) & (FLASH_ACR_LATENCY_Msk) != 1){} + } +} + +void delayInitMs(uint32_t clk, uint32_t ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((clk / ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} diff --git a/bsl/nucleo_f042k6/bslConfig.cmake b/bsl/nucleo_f042k6/bslConfig.cmake index 37186e5..b690af7 100644 --- a/bsl/nucleo_f042k6/bslConfig.cmake +++ b/bsl/nucleo_f042k6/bslConfig.cmake @@ -78,3 +78,4 @@ list(APPEND EXTRA_LIBS sub::sources) list(APPEND EXTRA_LIBS sub::delay) list(APPEND EXTRA_LIBS sub::pin) list(APPEND EXTRA_LIBS sub::usart) +list(APPEND EXTRA_LIBS sub::init) diff --git a/main.c b/main.c new file mode 100644 index 0000000..a8bd47f --- /dev/null +++ b/main.c @@ -0,0 +1,67 @@ +#include "main.h" +#include "delay.h" +#include "stm32f0xx_csl.h" +#include "usart.h" +#include "ascii.h" + +int main(int argc, char *argv[]) +{ + uint8_t i = 0; + uint8_t a = '0'; +// stmStart(); + + delayInitMs(8000000, 1000); + + pinConfig(pinB3, output, pushPull, def_res, def_speed); + pinConfig(pinA0, input, def_stage, pullDown, def_speed); + + usartInit( usart2, + pinA2, + pinA15, + 115200, + eight, + NO_PARITY_CTRL, + noFlowControl); + + //clears screen and send the wellcome messgae + print_Usart(usart2, ASCII_clear); + print_Usart(usart2, "Wellcome to our KED project\n\r"); + + + //blinks 10 times to indicate the sicsessfull init if the device + for(i = 0 ; i < 10 ; i++) + { + delayMs(100); + pinToggle(pinB3); + delayMs(100); + } + + pinWrite(pinB3,0); + + while(1) + { + //USART will rteturn what wou type and trun led on if you press "1" + a = usartGetChar(usart2); + usartSendChar(usart2, a); + if(a == '1') + { + pinWrite(pinB3,1); + } + else + { + pinWrite(pinB3,0); + } + + //test if the gpio port works as an input + if(pinRead(pinA0)) + { + pinWrite(pinB3,1); + } + else + { + pinWrite(pinB3,0); + } + delayMs(10); + } + return 1; +} diff --git a/main.cpp b/main.cpp index cff9c03..feab704 100644 --- a/main.cpp +++ b/main.cpp @@ -1,6 +1,7 @@ #include "main.hpp" #include "delay.h" -#include "stm32f0xx_csl.h" +//#include "stm32f0xx_csl.h" +#include "deviceSetup.h" #include "usart.h" #include "ascii.h" @@ -8,8 +9,9 @@ int main(int argc, char *argv[]) { uint8_t i = 0; uint8_t a = '0'; - stmStart(); + setupInit(); + delayInitMs(8000000, 1000); // FreeRTOS_Delay dly; // dly.wait(); @@ -32,9 +34,9 @@ int main(int argc, char *argv[]) //blinks 10 times to indicate the sicsessfull init if the device for(i = 0 ; i < 10 ; i++) { -// delayMs(100); + delayMs(100); pinToggle(pinB3); -// delayMs(100); + delayMs(100); } pinWrite(pinB3,0); @@ -62,7 +64,7 @@ int main(int argc, char *argv[]) { pinWrite(pinB3,0); } -// delayMs(100); + delayMs(100); } return 1; } diff --git a/main.h b/main.h new file mode 100644 index 0000000..83f7187 --- /dev/null +++ b/main.h @@ -0,0 +1,24 @@ +#ifndef MAIN_H +#define MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + + + +#ifdef RASPBERRY + #include "bsl/raspberry/bsl_raspberry.hpp" +#endif + +#ifdef ARM_MCU +// #include "bsl/nucleo_f042k6/bsl_nucleo_f042k6.hpp" +#endif + + + +#ifdef __cplusplus +} +#endif + +#endif /* MAIN_H */