diff --git a/ked/csl/stm32f042/Src/imp_spi.c b/ked/csl/stm32f042/Src/imp_spi.c index ca98bfd..55a21c2 100644 --- a/ked/csl/stm32f042/Src/imp_spi.c +++ b/ked/csl/stm32f042/Src/imp_spi.c @@ -38,7 +38,13 @@ void spiDissable(spiCH_t spi_hw_ch) void spiSetMode(spiCH_t spi_hw_ch, spi_mode_t mode) { SPI_BASE->CR1 &= ~(mode << SPI_CR1_MSTR_Pos); - SPI_BASE->CR1 |= mode << SPI_CR1_MSTR_Pos; + SPI_BASE->CR1 |= mode << SPI_CR1_MSTR_Pos; + + // TODO: find out if this is the correct place to set the SSOE bit + SPI_BASE->CR2 &= ~SPI_CR2_SSOE; + if(mode == SPI_MASTER) { + SPI_BASE->CR2 |= SPI_CR2_SSOE; + } } void spiSetPolarity(spiCH_t spi_hw_ch, spi_clkPol_t clkPol) diff --git a/ked/drivers/spi.c b/ked/drivers/spi.c index 942c863..c8d70c4 100644 --- a/ked/drivers/spi.c +++ b/ked/drivers/spi.c @@ -24,23 +24,17 @@ void spiInitMaster(spiCH_t spi_hw_ch, spiSetSoftwareSlaveManagement(spi_hw_ch,1); spiSetInternalSlaveSelect(spi_hw_ch,0); - //SPI1->CR1 &= ~(1<<10); // RXONLY = 0, full-duplex //SPI_BASE->CR1 &= ~(1<<10); spiSetComMode(spi_hw_ch, comMode); - - //TODO: test this for relevance of functionality. Leave it away, compilw it and run it - //SPI1->CR1 &= ~(1<<11); // CRCL =0, 8 bit data - //SPI_BASE->CR1 |= SPI_CR1_CRCL; - spiSetClockPrescaler(spi_hw_ch, prescaler); spiSetBitFrameLength(spi_hw_ch, SPI_FRAME_LENGTH_8BIT); // TODO: find out what SSOE does // TODO: find out what FRXTH does - SPI_BASE->CR2 |= SPI_CR2_SSOE;// | SPI_CR2_FRXTH;// | SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2; + //SPI_BASE->CR2 |= SPI_CR2_SSOE; } void spiSetupCH(spi_ch_t *ch, spiCH_t spi_hw_ch, pinNo_t chipselectPin)