From 6d77c554006f0d998f804ef497c0652b4bb919c3 Mon Sep 17 00:00:00 2001
From: polymurph <eddyed.k@gmail.com>
Date: Sun, 18 Sep 2022 16:47:54 +0200
Subject: [PATCH] updated hardware description with missing spi stuff
---
.../stm32f042/Device/hardwareDescription.h | 32 +++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/ked/csl/stm32f042/Device/hardwareDescription.h b/ked/csl/stm32f042/Device/hardwareDescription.h
index 7018153..f4a50c9 100644
--- a/ked/csl/stm32f042/Device/hardwareDescription.h
+++ b/ked/csl/stm32f042/Device/hardwareDescription.h
@@ -230,18 +230,46 @@ static const uint32_t timerRes_Prescaler[MAX_TIMER_CHANNEL_COUNT] = {
0xFFFF, /*!< Timer 17 Prescaler Max Value */
};
+/*!
+ * RCC Bus number index list connected to the SPI
+ * */
+static const uint8_t spiBus_No[MAX_SPI_CHANNEL_COUNT] = {
+ 2, /*!< SPI 1 is connected to bus 2 */
+ 1 /*!< SPI 2 is connected to bus 1 */
+};
+
+/*!
+ * RCC SPI clock enable bit position for the given register
+ *
+ */
+static const uint8_t spiBus_En_bitPos[MAX_SPI_CHANNEL_COUNT] = {
+ RCC_APB2ENR_SPI1EN_Pos,
+ RCC_APB1ENR_SPI2EN_Pos
+};
+
+/*!
+ * RCC SPI Reset Bit Position list
+ * */
+static const uint8_t spiBus_Rst_bitPos[MAX_SPI_CHANNEL_COUNT] = {
+ RCC_APB2RSTR_SPI1RST_Pos,
+ RCC_APB1RSTR_SPI2RST_Pos
+};
+/**
+ * Enumof available spi hardware channels
+ */
typedef enum{
SPI_CH_1,
SPI_CH_2
} spiCH_t;
-
+/**
+ * SPI base address list
+ */
static const uint32_t spiBase_Addr_List[MAX_SPI_CHANNEL_COUNT] = {
SPI1_BASE,
SPI2_BASE
};
-
#ifdef __cplusplus
}
#endif