From 206f119a123a52d2d93b3107b340e8bb04fffd41 Mon Sep 17 00:00:00 2001 From: key Date: Mon, 25 Jul 2022 14:04:19 +0200 Subject: [PATCH] Configurgnt the struture and typdefs for the i2c channel initilization --- ked/csl/interfaces/i2c.h | 75 ++++++++++++++----- .../stm32f042/Device/hardwareDescription.h | 14 +++- main.c | 1 + 3 files changed, 71 insertions(+), 19 deletions(-) diff --git a/ked/csl/interfaces/i2c.h b/ked/csl/interfaces/i2c.h index 500ce0e..d6b1bdf 100755 --- a/ked/csl/interfaces/i2c.h +++ b/ked/csl/interfaces/i2c.h @@ -38,24 +38,63 @@ extern "C" { #define I2C_STATE_TIMEOUT 8 // Timeout #define I2C_STATE_ERROR 9 // Error happened -#define I2C_SPEED_STANDART 1 // Sm 100 kbits/s This mode will be choosen for the constructor. -#define I2C_SPEED_FAST 2 // Fm 400 kbits/s -#define I2C_SPEED_FAST_PLUS 3 // Fm+ 1 Mbits/s -#define I2C_SPEED_HIGH_SPEED 4 // Hs 3.4 Mbits/s -#define I2C_SPEED_ULTRA_FAST 5 // UFm 5 Mbits/s -#define I2C_ADDRESS_7B 1 // 7 bits addressing mode -#define I2C_ADDRESS_10B 2 // 10 bits addressing mode +/*! Enum of possible I2C opperation modes */ +typedef enum{ + i2cModeMaster, /*!< Master mode : In Master mode, the I2C interface initiates a data transfer and generates the clock signal. */ + i2cModeMultyMaster, /*!< Multimaster Mode : In case if more than one master are present in one I2C bus, In such case each device needs to be able to cooperate with the fact that another device is currently talking and the bus is therefore busy (Arbirtation). For More information : https://www.i2c-bus.org/multimaster/ */ + i2cModeSlave /*!< Slave mode : A slave device has to always be ready to detect and process a start condition and to recognize its address */ +}i2cMode_t; + +/*! Enum of possible I2C speeds */ +typedef enum{ + i2cSpeedStandart, /*!< SM 100 kbits/s This is the stantrd spped for any standart i2c Applications */ + i2cSpeedFast, /*!< FM 400 kbits/s */ + i2cSpeedFastPlus, /*!< FM+ 1 Mbits/s */ + i2cSpeedHightSpeed, /*!< HS 3.4 Mbits/s */ + i2cSpeedUltraFast /*!< UFM 5 Mbits/s */ +}i2cSpeed_t; + +/*! Enum of possible I2C Adress sizes */ +typedef enum{ + i2cAddressSizeSevenBits, /*!< 7 Bits address size */ + i2cAddressSizeTenBits /*!< 10 Bits address size */ +}i2cAddressSize_t; + +/*! Enum of possible I2C Address count */ +typedef enum{ + i2cAddressCountSingle, /*!< Only one adress for communication */ + i2cAddressCountDual /*!< Dual adresses for one device respondng to two adresses */ +}i2cAddressCount_t; + +/*! Enum for clock strechning activation. Can only be implmented as Slave for more information : https://www.i2c-bus.org/clock-stretching/ */ +typedef enum{ + i2cClockStrechingEnable, /*!< In situations where an I2C slave is not able to co-operate with the clock speed given by the master and needs to slow down a little. This is done by a mechanism referred to as clock stretching. */ + i2cCLockStrechingDisable /*!< We assume that the master and slave have compatible Clock frequencies */ +}i2cClockStreching_t; + +typedef struct +{ + uint16_t adress; /*!< First and Main address of the device */ + i2cAddressSize_t adressSize; /*!< 10 or 7 bit adress size */ + i2cAddressCount_t addresCount; /*!< SIngle or multiple */ + i2cMode_t mode; /*!< Master, Slave or Multymaster Modes */ + i2cSpeed_t speed;/*!< Bus Speed */ + i2cClockStreching_t streching; /*!< Clock Streching enablede or disabled*/ + uint32_t timing; /*!< Specifies the I2C timing The timings must be configured + in order to guarantee a correct data hold and setup time, used in master + and slave modes. */ + uint16_t adressSecond; /*!< Second adress if dual adresse mode is configured*/ +}i2cChannelDefinition_t; -#define I2C_MODE_MASTER 1 // Single Master Mode -#define I2C_MODE_SLAVE 2 // Slave Mode -#define I2C_MODE_MULTI_MASTER 3 // Multy Master Mode - -/* Creator from the CPP Version PLease keep it to define the main init sequence.*/ -//ll_i2c(uint16_t address, uint8_t channel, uint8_t mode, uint8_t adressMode); // Creat i2c abject witha agiven channel address & mode speed is by default the slowest. +/** + * @brief Initilize the I2C Hardware + */ + +int8_t i2cInit(i2cCh_t i2cChannel); -void i2cRead(uint8_t *reg, uint8_t *buffer, uint8_t ®Lenght, uint8_t &bufferLenght); // Defined by me : Read a given number of bytes -void i2cWrite(uint8_t *reg, uint8_t *data, uint8_t ®Lenght, uint8_t &dataLenght); // Defined by me : Send a given number of bytes +void i2cRead(uint8_t *reg, uint8_t *buffer, uint8_t *regLenght, uint8_t *bufferLenght); // Defined by me : Read a given number of bytes +void i2cWrite(uint8_t *reg, uint8_t *data, uint8_t *regLenght, uint8_t *dataLenght); // Defined by me : Send a given number of bytes uint8_t i2cTestDeviceSpeed(); // Defined by me : Cycle trough different modes until device cnat't answer fast enought uint8_t i2cDiscoverDevices(); // Defined by me : Scan the awailable address range on standart mode to find devices @@ -73,15 +112,15 @@ void i2cSoftReset(); // I2C Standart : Software reset not supported by all hard void i2cBusClear(); // I2C Standart : in case if SCL is stuck void i2cSetSpeed(uint8_t speed); // I2C Standart -void i2cSetAddress(uint16_t &address); // I2C Standart +void i2cSetAddress(uint16_t address); // I2C Standart void i2cSetAddressMode(); // I2C Standart -void i2cSetTimeout(uint8_t &timeout); // Hardware specific +void i2cSetTimeout(uint8_t timeout); // Hardware specific void i2cSetInterrupt(); // Hardware Specific void i2cSetDma(); // Hardware specific void i2cThrowError(int16_t error); // Defined by me : Private error function for error handling -void i2cPointReg(uint8_t *reg); // Defined by me : Points to the register to be red from +void i2cPointReg(uint8_t reg); // Defined by me : Points to the register to be red from #ifdef __cplusplus } diff --git a/ked/csl/stm32f042/Device/hardwareDescription.h b/ked/csl/stm32f042/Device/hardwareDescription.h index b4fc107..9d4a61f 100644 --- a/ked/csl/stm32f042/Device/hardwareDescription.h +++ b/ked/csl/stm32f042/Device/hardwareDescription.h @@ -221,7 +221,7 @@ static const uint8_t timerBus_No[MAX_TIMER_CHANNEL_COUNT] = { /*! * Timer Prescaler resolution list TO BE DELETED IF NOT NEEDED * */ -static const uint32_t timerRes_Prescaler[MAX_TIMER_CHANNEL_COUNT] = { +static const uint32_t timerRes_Prescaler[MAX_TIMER_CHANNEL_COUNT] = { 0xFFFF, /*!< Timer 1 Prescaler Max Value */ 0xFFFF, /*!< Timer 2 Prescaler Max Value */ 0xFFFF, /*!< Timer 3 Prescaler Max Value */ @@ -242,14 +242,26 @@ static const uint32_t spiBase_Addr_List[MAX_SPI_CHANNEL_COUNT] = { }; +/*! + * Awailable I2C Channels + * Hadware dependent / + * Register independent ! + * */ typedef enum{ I2C_CH_1 }i2cCh_t; + +/*! + * I2C Channel Base adress + * Hadware dependent / + * Register dependent ! + * */ static const uint32_t i2cBase_Addr_List[MAX_I2C_CHANNEL_COUNT] = { I2C1_BASE }; + #ifdef __cplusplus } #endif diff --git a/main.c b/main.c index a290fdd..903f03c 100644 --- a/main.c +++ b/main.c @@ -5,6 +5,7 @@ #include "ascii.h" #include "timer.h" #include "spi.h" +#include "i2c.h" void timer_test(timerNo_t timer, pinNo_t pin) {