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new i2c.c is working but not optimal nad there are some questions concerning the datasheet (NBYTE counter)

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master
Kerem Yollu 2 years ago
parent 0ecc6496af
commit 0e22b6b379
3 changed files with 70 additions and 89 deletions
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49
csl/stm32f042/Src/imp_i2c.c
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@ -167,12 +167,17 @@ uint8_t i2c_is_perif_ready(i2c_t *i2c_dev)
return ((I2C_BASE->ISR & (I2C_ISR_BUSY))!=I2C_ISR_BUSY);
}
void i2c_set_tx_counter(i2c_t *i2c_dev, uint8_t count)
void i2c_set_transfer_counter(i2c_t *i2c_dev, uint8_t count)
{
I2C_BASE->CR2 &= ~(0xFF << I2C_CR2_NBYTES_Pos);
I2C_BASE->CR2 |= (count << I2C_CR2_NBYTES_Pos);
}
uint8_t i2c_get_transfer_counter(i2c_t *i2c_dev)
{
return (I2C_BASE->CR2 & I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos;
}
void i2c_init_write_command(i2c_t *i2c_dev)
{
I2C_BASE->CR2 &= ~I2C_CR2_RD_WRN;
@ -188,9 +193,6 @@ void i2c_init_read_command(i2c_t *i2c_dev)
void i2c_send_address_for_write(i2c_t *i2c_dev, uint16_t *slaveAddress)
{
// Arch nemesis ! We send only one byte of data which is the register adress.
i2c_set_tx_counter(i2c_dev,1);
// On This chip this shoudl be done before the start condition
i2c_init_write_command(i2c_dev);
@ -199,11 +201,7 @@ void i2c_send_address_for_write(i2c_t *i2c_dev, uint16_t *slaveAddress)
// This device places the salve address automaticaly in the output buffer before sending the star condition
i2c_send_start(i2c_dev);
i2c_dev->hardwareState = i2c_hw_out_buff_full;
while(i2c_is_output_buffer_full(i2c_dev));
i2c_dev->periferalState = i2c_perif_address_sent;
if(i2c_check_nack(i2c_dev))
{
@ -215,12 +213,6 @@ void i2c_send_address_for_write(i2c_t *i2c_dev, uint16_t *slaveAddress)
void i2c_send_address_for_read(i2c_t *i2c_dev, uint16_t *slaveAddress)
{
// Arch nemesis ! We only setn the address
// but the counter allso socunt the bits that we have recieved
// and we want to read one byte
// every transaction counts
i2c_set_tx_counter(i2c_dev,1);
// On This chip this shoudl be done before the start condition
i2c_init_read_command(i2c_dev);
@ -228,11 +220,7 @@ void i2c_send_address_for_read(i2c_t *i2c_dev, uint16_t *slaveAddress)
I2C_BASE->CR2 |= (*slaveAddress & 0xff) << 1; // The bit no 0 is not taken in concideration in 7bit mode
// This device places the salve address automaticaly in the output buffer before sending the star condition
i2c_send_start(i2c_dev);
i2c_dev->hardwareState = i2c_hw_out_buff_full;
while(i2c_is_output_buffer_full(i2c_dev));
i2c_dev->periferalState = i2c_perif_address_sent;
if(i2c_check_nack(i2c_dev))
{
@ -263,9 +251,25 @@ uint8_t i2c_is_output_buffer_full(i2c_t *i2c_dev)
}
}
uint8_t i2c_is_txis(i2c_t *i2c_dev)
{
if(I2C_BASE->ISR & I2C_ISR_TXIS)
{
i2c_dev->hardwareState = i2c_hw_out_buff_empty;
return 0;
}
else
{
i2c_dev->hardwareState = i2c_hw_out_buff_full;
return 1;
}
}
void i2c_send_reg_address(i2c_t *i2c_dev, uint8_t *registerAddress)
{
i2c_send_data(i2c_dev,registerAddress);
I2C_BASE->TXDR = *registerAddress;
i2c_dev->hardwareState = i2c_hw_out_buff_full;
while(i2c_is_output_buffer_full(i2c_dev));
}
void i2c_send_data(i2c_t *i2c_dev, uint8_t *data)
@ -275,7 +279,7 @@ void i2c_send_data(i2c_t *i2c_dev, uint8_t *data)
while(i2c_is_output_buffer_full(i2c_dev));
}
uint8_t i2c_is_tx_complete(i2c_t *i2c_dev)
uint8_t i2c_is_transfer_complete(i2c_t *i2c_dev)
{
/*
TC: Transfer Complete (master mode)
@ -283,15 +287,12 @@ uint8_t i2c_is_tx_complete(i2c_t *i2c_dev)
transferred. It is cleared by software when START bit or STOP bit is set.
Note: This bit is cleared by hardware when PE=0.
*/
if(I2C_BASE->ISR & I2C_ISR_TC)
{
i2c_dev->periferalState = i2c_perif_tx_done;
return 1;
}
else
{
i2c_dev->periferalState = i2c_perif_tx_ongoing;
return 0;
}
}
@ -312,7 +313,9 @@ uint8_t i2c_is_input_buffer_full(i2c_t *i2c_dev)
void i2c_get_input_register(i2c_t *i2c_dev, uint8_t *data)
{
while(!i2c_is_input_buffer_full(i2c_dev));
*data = I2C_BASE->RXDR;
while(!i2c_is_transfer_complete(i2c_dev));
}
void i2c_send_nack(i2c_t *i2c_dev)

93
peripherals/i2c.c
Unescape View File

@ -43,81 +43,50 @@ void i2c_init( i2c_t *i2c_dev, /*!< Pointer to I2C hardware Object */
void i2c_read(i2c_t *i2c_dev, uint16_t *slaveAddress, uint8_t *registerAddress, uint8_t *data, uint8_t *dataLenght)
{
i2c_dev->periferalState = i2c_perif_read;
// Arch nemesis ! We only setn the address
// but the counter allso socunt the bits that we have recieved
// and we want to read one byte
// every transaction counts
i2c_set_transfer_counter(i2c_dev,1);
i2c_send_address_for_write(i2c_dev, slaveAddress);
i2c_send_reg_address(i2c_dev, registerAddress);
while(!i2c_is_tx_complete(i2c_dev));
while(!i2c_is_transfer_complete(i2c_dev));
i2c_set_transfer_counter(i2c_dev,1);
i2c_send_address_for_read(i2c_dev, slaveAddress);
while(!i2c_is_input_buffer_full(i2c_dev));
i2c_get_input_register(i2c_dev, data);
while(!i2c_is_tx_complete(i2c_dev));
while(!i2c_is_transfer_complete(i2c_dev));
i2c_send_nack(i2c_dev);
i2c_send_stop(i2c_dev);
print_Usart(usart2, "I2C -> Read Done\n\r");
}
void i2c_write(i2c_t *i2c_dev, uint16_t *slaveAddress, uint8_t *registerAddress, uint8_t *data, uint8_t *dataLenght){}
/*
void i2cRead(i2c_t *i2c_dev, uint16_t *slaveAddress, uint8_t *registerAddress, uint8_t *data, uint8_t *dataLenght)
{
//
// Start
// Send Address
// Wait For ACK
//
uint8_t nbytes = 0;
i2c_dev->periferalState = i2cPerifTransmitting;
i2cSetTransferCounter(i2c_dev,1);
i2cSendSlaveAddressWrite(i2c_dev, slaveAddress);
i2cSendRegisterAddress(i2c_dev,registerAddress);
while(i2c_dev->periferalState != i2cPerifTransferComplete)
{
i2cIsTransferComplete(i2c_dev);
}
i2c_dev->periferalState = i2cPerifRecieving;
i2cSendSlaveAddressRead(i2c_dev, slaveAddress);
while(i2c_dev->periferalState != i2cPerifTransferComplete)
{
i2cIsTransferComplete(i2c_dev);
}
i2cGenerateNack(i2c_dev);
i2cGenerateStop(i2c_dev);
i2cReadInputRegister(i2c_dev, data);
while(!i2c_is_perif_ready(i2c_dev));
print_Usart(usart2, "I2C Ready afer read\n\r");
i2c_dev->periferalState = i2c_perif_ready;
}
void i2c_write(i2c_t *i2c_dev, uint16_t *slaveAddress, uint8_t *registerAddress, uint8_t *data, uint8_t *dataLenght)
{
i2c_dev->periferalState = i2c_perif_write;
print_Usart(usart2, "\n\rI2C Read completed\n\r");
i2c_set_transfer_counter(i2c_dev,2);
while(i2c_dev->periferalState != i2cPerifReady)
{
i2cIsPeriferalReady(i2c_dev);
}
i2c_dev->periferalState = i2cPerifReady;
i2c_dev->hardwareState = i2cHwIdle;
}
print_Usart(usart2, "I2C Transfer Counter: ");
usartSendChar(usart2, i2c_get_transfer_counter(i2c_dev) + 0x30);
print_Usart(usart2, "\n\r");
void i2cWrite(i2c_t *i2c_dev, uint16_t *slaveAddress, uint8_t *registerAddress, uint8_t *data, uint8_t *dataLenght)
{
i2cSetTransferCounter(i2c_dev,2);
i2cSendSlaveAddressWrite(i2c_dev, slaveAddress);
i2cSendRegisterAddress(i2c_dev,registerAddress);
while((i2c_dev->hardwareState =! i2cHwOutputBufferEmpty))
{
i2cIsOutputBufferEmpty(i2c_dev);
}
i2cSendData(i2c_dev,data);
i2c_send_address_for_write(i2c_dev, slaveAddress);
i2c_send_reg_address(i2c_dev, registerAddress);
i2c_send_data(i2c_dev, data);
while(!i2c_is_transfer_complete(i2c_dev));
i2c_send_stop(i2c_dev);
i2cGenerateStop(i2c_dev);
print_Usart(usart2, "\n\rI2C Transfer completed\n\r");
while(!i2c_is_perif_ready(i2c_dev));
print_Usart(usart2, "I2C Ready afer write\n\r");
i2c_dev->periferalState = i2c_perif_ready;
}
*/
void i2c_throw_error(i2c_t *i2c_dev, int16_t error)
{
print_Usart(usart2, "\n\r");

17
peripherals/i2c.h
Unescape View File

@ -115,8 +115,8 @@ typedef enum
i2c_perif_enabled, /*!< I2C CHannle is initilized but not neceserly ready */
i2c_perif_ready, /*!< Peripheral Initialized and ready for use */
i2c_perif_address_sent, /*!< The Salve Address Was Sent to the bus */
i2c_perif_tx_ongoing, /*!< A transfer to the bus is ongoing */
i2c_perif_tx_done, /*!< The transfer to the bus is finished */
i2c_perif_write, /*!< The prefiferal is configured for a write */
i2c_perif_read, /*!< The prefiferal is configured for a read */
i2c_perif_rx_ongoing, /*!< Recieving from the bus */
i2c_perif_rx_done, /*!< Recived everything from the bus */
i2c_perif_listening, /*!< Address Listen Mode is ongoing */
@ -455,14 +455,21 @@ void i2c_set_output_register(i2c_t *i2c_dev, uint8_t *data);
* @param data pointer to the data that need to be read and returned
* @return 1 when Transefer is complete | 0 When Transfer is ongoing
*/
uint8_t i2c_is_tx_complete(i2c_t *i2c_dev);
uint8_t i2c_is_transfer_complete(i2c_t *i2c_dev);
/**
* @brief Defines the amount of transfers to be made. Address exchange and start conditon does not count
* @param i2c_dev is the beforehand declared i2c channel with his opperation modes
* @param count amount o data to be transfered.
*/
void i2c_set_tx_counter(i2c_t *i2c_dev, uint8_t count);
void i2c_set_transfer_counter(i2c_t *i2c_dev, uint8_t count);
/**
* @brief Defines the amount of transfers to be made. Address exchange and start conditon does not count
* @param i2c_dev is the beforehand declared i2c channel with his opperation modes
* @param count amount o data to be transfered.
*/
uint8_t i2c_get_transfer_counter(i2c_t *i2c_dev);
/**************************************************************************************************
I2C Arbitration Functions for Multymaster mode and slaves clock stretching
@ -515,6 +522,8 @@ void i2c_sleep(i2c_t *i2c_dev);
*/
void i2c_throw_error(i2c_t *i2c_dev, int16_t error);
uint8_t i2c_is_txis(i2c_t *i2c_dev);
#ifdef __cplusplus
}
#endif

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