Layer Pairs Export File for PCB: C:\Users\eleazar.falco\Desktop\Motorsport Gate Driver\Reference Design (RD001)\PCB Layout Design Files\Altium Design Files\Variant B (1-side_2-Layer)\SiC_GD_PSU_VarB_rev20a.PcbDoc
LayersSetName=Top_Bot_Thru_Holes|DrillFile=sic_gd_psu_varb_rev20a-roundholes.txt|DrillLayers=gtl,gbl
