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dummy_reflow/Software/reflow_oven/Debug/reflow_oven.list

5307 lines
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reflow_oven.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000000c0 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00001c24 080000c0 080000c0 000100c0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000038 08001ce4 08001ce4 00011ce4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08001d1c 08001d1c 0002000c 2**0
CONTENTS
4 .ARM 00000000 08001d1c 08001d1c 0002000c 2**0
CONTENTS
5 .preinit_array 00000000 08001d1c 08001d1c 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08001d1c 08001d1c 00011d1c 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08001d20 08001d20 00011d20 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08001d24 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000000a8 2000000c 08001d30 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000604 200000b4 08001d30 000200b4 2**0
ALLOC
11 .ARM.attributes 00000028 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .comment 00000043 00000000 00000000 00020034 2**0
CONTENTS, READONLY
13 .debug_info 00007431 00000000 00000000 00020077 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_abbrev 00001688 00000000 00000000 000274a8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_aranges 00000630 00000000 00000000 00028b30 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_rnglists 000004aa 00000000 00000000 00029160 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_macro 0000f705 00000000 00000000 0002960a 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_line 000093c3 00000000 00000000 00038d0f 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .debug_str 0005adc5 00000000 00000000 000420d2 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .debug_frame 00001390 00000000 00000000 0009ce98 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 0000005e 00000000 00000000 0009e228 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080000c0 <__do_global_dtors_aux>:
80000c0: b510 push {r4, lr}
80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>)
80000c4: 7823 ldrb r3, [r4, #0]
80000c6: 2b00 cmp r3, #0
80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>)
80000cc: 2b00 cmp r3, #0
80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>)
80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
80000d4: bf00 nop
80000d6: 2301 movs r3, #1
80000d8: 7023 strb r3, [r4, #0]
80000da: bd10 pop {r4, pc}
80000dc: 2000000c .word 0x2000000c
80000e0: 00000000 .word 0x00000000
80000e4: 08001ccc .word 0x08001ccc
080000e8 <frame_dummy>:
80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc <frame_dummy+0x14>)
80000ea: b510 push {r4, lr}
80000ec: 2b00 cmp r3, #0
80000ee: d003 beq.n 80000f8 <frame_dummy+0x10>
80000f0: 4903 ldr r1, [pc, #12] ; (8000100 <frame_dummy+0x18>)
80000f2: 4804 ldr r0, [pc, #16] ; (8000104 <frame_dummy+0x1c>)
80000f4: e000 b.n 80000f8 <frame_dummy+0x10>
80000f6: bf00 nop
80000f8: bd10 pop {r4, pc}
80000fa: 46c0 nop ; (mov r8, r8)
80000fc: 00000000 .word 0x00000000
8000100: 20000010 .word 0x20000010
8000104: 08001ccc .word 0x08001ccc
08000108 <__udivsi3>:
8000108: 2200 movs r2, #0
800010a: 0843 lsrs r3, r0, #1
800010c: 428b cmp r3, r1
800010e: d374 bcc.n 80001fa <__udivsi3+0xf2>
8000110: 0903 lsrs r3, r0, #4
8000112: 428b cmp r3, r1
8000114: d35f bcc.n 80001d6 <__udivsi3+0xce>
8000116: 0a03 lsrs r3, r0, #8
8000118: 428b cmp r3, r1
800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e>
800011c: 0b03 lsrs r3, r0, #12
800011e: 428b cmp r3, r1
8000120: d328 bcc.n 8000174 <__udivsi3+0x6c>
8000122: 0c03 lsrs r3, r0, #16
8000124: 428b cmp r3, r1
8000126: d30d bcc.n 8000144 <__udivsi3+0x3c>
8000128: 22ff movs r2, #255 ; 0xff
800012a: 0209 lsls r1, r1, #8
800012c: ba12 rev r2, r2
800012e: 0c03 lsrs r3, r0, #16
8000130: 428b cmp r3, r1
8000132: d302 bcc.n 800013a <__udivsi3+0x32>
8000134: 1212 asrs r2, r2, #8
8000136: 0209 lsls r1, r1, #8
8000138: d065 beq.n 8000206 <__udivsi3+0xfe>
800013a: 0b03 lsrs r3, r0, #12
800013c: 428b cmp r3, r1
800013e: d319 bcc.n 8000174 <__udivsi3+0x6c>
8000140: e000 b.n 8000144 <__udivsi3+0x3c>
8000142: 0a09 lsrs r1, r1, #8
8000144: 0bc3 lsrs r3, r0, #15
8000146: 428b cmp r3, r1
8000148: d301 bcc.n 800014e <__udivsi3+0x46>
800014a: 03cb lsls r3, r1, #15
800014c: 1ac0 subs r0, r0, r3
800014e: 4152 adcs r2, r2
8000150: 0b83 lsrs r3, r0, #14
8000152: 428b cmp r3, r1
8000154: d301 bcc.n 800015a <__udivsi3+0x52>
8000156: 038b lsls r3, r1, #14
8000158: 1ac0 subs r0, r0, r3
800015a: 4152 adcs r2, r2
800015c: 0b43 lsrs r3, r0, #13
800015e: 428b cmp r3, r1
8000160: d301 bcc.n 8000166 <__udivsi3+0x5e>
8000162: 034b lsls r3, r1, #13
8000164: 1ac0 subs r0, r0, r3
8000166: 4152 adcs r2, r2
8000168: 0b03 lsrs r3, r0, #12
800016a: 428b cmp r3, r1
800016c: d301 bcc.n 8000172 <__udivsi3+0x6a>
800016e: 030b lsls r3, r1, #12
8000170: 1ac0 subs r0, r0, r3
8000172: 4152 adcs r2, r2
8000174: 0ac3 lsrs r3, r0, #11
8000176: 428b cmp r3, r1
8000178: d301 bcc.n 800017e <__udivsi3+0x76>
800017a: 02cb lsls r3, r1, #11
800017c: 1ac0 subs r0, r0, r3
800017e: 4152 adcs r2, r2
8000180: 0a83 lsrs r3, r0, #10
8000182: 428b cmp r3, r1
8000184: d301 bcc.n 800018a <__udivsi3+0x82>
8000186: 028b lsls r3, r1, #10
8000188: 1ac0 subs r0, r0, r3
800018a: 4152 adcs r2, r2
800018c: 0a43 lsrs r3, r0, #9
800018e: 428b cmp r3, r1
8000190: d301 bcc.n 8000196 <__udivsi3+0x8e>
8000192: 024b lsls r3, r1, #9
8000194: 1ac0 subs r0, r0, r3
8000196: 4152 adcs r2, r2
8000198: 0a03 lsrs r3, r0, #8
800019a: 428b cmp r3, r1
800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a>
800019e: 020b lsls r3, r1, #8
80001a0: 1ac0 subs r0, r0, r3
80001a2: 4152 adcs r2, r2
80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a>
80001a6: 09c3 lsrs r3, r0, #7
80001a8: 428b cmp r3, r1
80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8>
80001ac: 01cb lsls r3, r1, #7
80001ae: 1ac0 subs r0, r0, r3
80001b0: 4152 adcs r2, r2
80001b2: 0983 lsrs r3, r0, #6
80001b4: 428b cmp r3, r1
80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4>
80001b8: 018b lsls r3, r1, #6
80001ba: 1ac0 subs r0, r0, r3
80001bc: 4152 adcs r2, r2
80001be: 0943 lsrs r3, r0, #5
80001c0: 428b cmp r3, r1
80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0>
80001c4: 014b lsls r3, r1, #5
80001c6: 1ac0 subs r0, r0, r3
80001c8: 4152 adcs r2, r2
80001ca: 0903 lsrs r3, r0, #4
80001cc: 428b cmp r3, r1
80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc>
80001d0: 010b lsls r3, r1, #4
80001d2: 1ac0 subs r0, r0, r3
80001d4: 4152 adcs r2, r2
80001d6: 08c3 lsrs r3, r0, #3
80001d8: 428b cmp r3, r1
80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8>
80001dc: 00cb lsls r3, r1, #3
80001de: 1ac0 subs r0, r0, r3
80001e0: 4152 adcs r2, r2
80001e2: 0883 lsrs r3, r0, #2
80001e4: 428b cmp r3, r1
80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4>
80001e8: 008b lsls r3, r1, #2
80001ea: 1ac0 subs r0, r0, r3
80001ec: 4152 adcs r2, r2
80001ee: 0843 lsrs r3, r0, #1
80001f0: 428b cmp r3, r1
80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0>
80001f4: 004b lsls r3, r1, #1
80001f6: 1ac0 subs r0, r0, r3
80001f8: 4152 adcs r2, r2
80001fa: 1a41 subs r1, r0, r1
80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8>
80001fe: 4601 mov r1, r0
8000200: 4152 adcs r2, r2
8000202: 4610 mov r0, r2
8000204: 4770 bx lr
8000206: e7ff b.n 8000208 <__udivsi3+0x100>
8000208: b501 push {r0, lr}
800020a: 2000 movs r0, #0
800020c: f000 f806 bl 800021c <__aeabi_idiv0>
8000210: bd02 pop {r1, pc}
8000212: 46c0 nop ; (mov r8, r8)
08000214 <__aeabi_uidivmod>:
8000214: 2900 cmp r1, #0
8000216: d0f7 beq.n 8000208 <__udivsi3+0x100>
8000218: e776 b.n 8000108 <__udivsi3>
800021a: 4770 bx lr
0800021c <__aeabi_idiv0>:
800021c: 4770 bx lr
800021e: 46c0 nop ; (mov r8, r8)
08000220 <MX_GPIO_Init>:
* EXTI
* Free pins are configured automatically as Analog (this feature is enabled through
* the Code Generation settings)
*/
void MX_GPIO_Init(void)
{
8000220: b590 push {r4, r7, lr}
8000222: b089 sub sp, #36 ; 0x24
8000224: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000226: 240c movs r4, #12
8000228: 193b adds r3, r7, r4
800022a: 0018 movs r0, r3
800022c: 2314 movs r3, #20
800022e: 001a movs r2, r3
8000230: 2100 movs r1, #0
8000232: f001 fd1f bl 8001c74 <memset>
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOF_CLK_ENABLE();
8000236: 4b2e ldr r3, [pc, #184] ; (80002f0 <MX_GPIO_Init+0xd0>)
8000238: 695a ldr r2, [r3, #20]
800023a: 4b2d ldr r3, [pc, #180] ; (80002f0 <MX_GPIO_Init+0xd0>)
800023c: 2180 movs r1, #128 ; 0x80
800023e: 03c9 lsls r1, r1, #15
8000240: 430a orrs r2, r1
8000242: 615a str r2, [r3, #20]
8000244: 4b2a ldr r3, [pc, #168] ; (80002f0 <MX_GPIO_Init+0xd0>)
8000246: 695a ldr r2, [r3, #20]
8000248: 2380 movs r3, #128 ; 0x80
800024a: 03db lsls r3, r3, #15
800024c: 4013 ands r3, r2
800024e: 60bb str r3, [r7, #8]
8000250: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000252: 4b27 ldr r3, [pc, #156] ; (80002f0 <MX_GPIO_Init+0xd0>)
8000254: 695a ldr r2, [r3, #20]
8000256: 4b26 ldr r3, [pc, #152] ; (80002f0 <MX_GPIO_Init+0xd0>)
8000258: 2180 movs r1, #128 ; 0x80
800025a: 0289 lsls r1, r1, #10
800025c: 430a orrs r2, r1
800025e: 615a str r2, [r3, #20]
8000260: 4b23 ldr r3, [pc, #140] ; (80002f0 <MX_GPIO_Init+0xd0>)
8000262: 695a ldr r2, [r3, #20]
8000264: 2380 movs r3, #128 ; 0x80
8000266: 029b lsls r3, r3, #10
8000268: 4013 ands r3, r2
800026a: 607b str r3, [r7, #4]
800026c: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
800026e: 4b20 ldr r3, [pc, #128] ; (80002f0 <MX_GPIO_Init+0xd0>)
8000270: 695a ldr r2, [r3, #20]
8000272: 4b1f ldr r3, [pc, #124] ; (80002f0 <MX_GPIO_Init+0xd0>)
8000274: 2180 movs r1, #128 ; 0x80
8000276: 02c9 lsls r1, r1, #11
8000278: 430a orrs r2, r1
800027a: 615a str r2, [r3, #20]
800027c: 4b1c ldr r3, [pc, #112] ; (80002f0 <MX_GPIO_Init+0xd0>)
800027e: 695a ldr r2, [r3, #20]
8000280: 2380 movs r3, #128 ; 0x80
8000282: 02db lsls r3, r3, #11
8000284: 4013 ands r3, r2
8000286: 603b str r3, [r7, #0]
8000288: 683b ldr r3, [r7, #0]
/*Configure GPIO pin : PF1 */
GPIO_InitStruct.Pin = GPIO_PIN_1;
800028a: 193b adds r3, r7, r4
800028c: 2202 movs r2, #2
800028e: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000290: 193b adds r3, r7, r4
8000292: 2203 movs r2, #3
8000294: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000296: 193b adds r3, r7, r4
8000298: 2200 movs r2, #0
800029a: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
800029c: 193b adds r3, r7, r4
800029e: 4a15 ldr r2, [pc, #84] ; (80002f4 <MX_GPIO_Init+0xd4>)
80002a0: 0019 movs r1, r3
80002a2: 0010 movs r0, r2
80002a4: f000 faac bl 8000800 <HAL_GPIO_Init>
/*Configure GPIO pins : PA0 PA1 PA3 PA4
PA5 PA6 PA7 PA8
PA9 PA10 PA11 PA12 */
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_3|GPIO_PIN_4
80002a8: 193b adds r3, r7, r4
80002aa: 4a13 ldr r2, [pc, #76] ; (80002f8 <MX_GPIO_Init+0xd8>)
80002ac: 601a str r2, [r3, #0]
|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8
|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
80002ae: 193b adds r3, r7, r4
80002b0: 2203 movs r2, #3
80002b2: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80002b4: 193b adds r3, r7, r4
80002b6: 2200 movs r2, #0
80002b8: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80002ba: 193a adds r2, r7, r4
80002bc: 2390 movs r3, #144 ; 0x90
80002be: 05db lsls r3, r3, #23
80002c0: 0011 movs r1, r2
80002c2: 0018 movs r0, r3
80002c4: f000 fa9c bl 8000800 <HAL_GPIO_Init>
/*Configure GPIO pins : PB0 PB1 PB3 PB4
PB5 PB6 PB7 */
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_3|GPIO_PIN_4
80002c8: 193b adds r3, r7, r4
80002ca: 22fb movs r2, #251 ; 0xfb
80002cc: 601a str r2, [r3, #0]
|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
80002ce: 193b adds r3, r7, r4
80002d0: 2203 movs r2, #3
80002d2: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80002d4: 193b adds r3, r7, r4
80002d6: 2200 movs r2, #0
80002d8: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80002da: 193b adds r3, r7, r4
80002dc: 4a07 ldr r2, [pc, #28] ; (80002fc <MX_GPIO_Init+0xdc>)
80002de: 0019 movs r1, r3
80002e0: 0010 movs r0, r2
80002e2: f000 fa8d bl 8000800 <HAL_GPIO_Init>
}
80002e6: 46c0 nop ; (mov r8, r8)
80002e8: 46bd mov sp, r7
80002ea: b009 add sp, #36 ; 0x24
80002ec: bd90 pop {r4, r7, pc}
80002ee: 46c0 nop ; (mov r8, r8)
80002f0: 40021000 .word 0x40021000
80002f4: 48001400 .word 0x48001400
80002f8: 00001ffb .word 0x00001ffb
80002fc: 48000400 .word 0x48000400
08000300 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000300: b580 push {r7, lr}
8000302: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000304: f000 f964 bl 80005d0 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000308: f000 f807 bl 800031a <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
800030c: f7ff ff88 bl 8000220 <MX_GPIO_Init>
MX_USART1_UART_Init();
8000310: f000 f8a0 bl 8000454 <MX_USART1_UART_Init>
/* USER CODE BEGIN 2 */
reflow_main();
8000314: f000 f950 bl 80005b8 <reflow_main>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
8000318: e7fe b.n 8000318 <main+0x18>
0800031a <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
800031a: b590 push {r4, r7, lr}
800031c: b095 sub sp, #84 ; 0x54
800031e: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000320: 2420 movs r4, #32
8000322: 193b adds r3, r7, r4
8000324: 0018 movs r0, r3
8000326: 2330 movs r3, #48 ; 0x30
8000328: 001a movs r2, r3
800032a: 2100 movs r1, #0
800032c: f001 fca2 bl 8001c74 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000330: 2310 movs r3, #16
8000332: 18fb adds r3, r7, r3
8000334: 0018 movs r0, r3
8000336: 2310 movs r3, #16
8000338: 001a movs r2, r3
800033a: 2100 movs r1, #0
800033c: f001 fc9a bl 8001c74 <memset>
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8000340: 003b movs r3, r7
8000342: 0018 movs r0, r3
8000344: 2310 movs r3, #16
8000346: 001a movs r2, r3
8000348: 2100 movs r1, #0
800034a: f001 fc93 bl 8001c74 <memset>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
800034e: 0021 movs r1, r4
8000350: 187b adds r3, r7, r1
8000352: 2202 movs r2, #2
8000354: 601a str r2, [r3, #0]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000356: 187b adds r3, r7, r1
8000358: 2201 movs r2, #1
800035a: 60da str r2, [r3, #12]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
800035c: 187b adds r3, r7, r1
800035e: 2210 movs r2, #16
8000360: 611a str r2, [r3, #16]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
8000362: 187b adds r3, r7, r1
8000364: 2200 movs r2, #0
8000366: 621a str r2, [r3, #32]
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000368: 187b adds r3, r7, r1
800036a: 0018 movs r0, r3
800036c: f000 fbb0 bl 8000ad0 <HAL_RCC_OscConfig>
8000370: 1e03 subs r3, r0, #0
8000372: d001 beq.n 8000378 <SystemClock_Config+0x5e>
{
Error_Handler();
8000374: f000 f828 bl 80003c8 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000378: 2110 movs r1, #16
800037a: 187b adds r3, r7, r1
800037c: 2207 movs r2, #7
800037e: 601a str r2, [r3, #0]
|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
8000380: 187b adds r3, r7, r1
8000382: 2200 movs r2, #0
8000384: 605a str r2, [r3, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000386: 187b adds r3, r7, r1
8000388: 2200 movs r2, #0
800038a: 609a str r2, [r3, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
800038c: 187b adds r3, r7, r1
800038e: 2200 movs r2, #0
8000390: 60da str r2, [r3, #12]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
8000392: 187b adds r3, r7, r1
8000394: 2100 movs r1, #0
8000396: 0018 movs r0, r3
8000398: f000 feb4 bl 8001104 <HAL_RCC_ClockConfig>
800039c: 1e03 subs r3, r0, #0
800039e: d001 beq.n 80003a4 <SystemClock_Config+0x8a>
{
Error_Handler();
80003a0: f000 f812 bl 80003c8 <Error_Handler>
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
80003a4: 003b movs r3, r7
80003a6: 2201 movs r2, #1
80003a8: 601a str r2, [r3, #0]
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1;
80003aa: 003b movs r3, r7
80003ac: 2200 movs r2, #0
80003ae: 609a str r2, [r3, #8]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
80003b0: 003b movs r3, r7
80003b2: 0018 movs r0, r3
80003b4: f000 ffea bl 800138c <HAL_RCCEx_PeriphCLKConfig>
80003b8: 1e03 subs r3, r0, #0
80003ba: d001 beq.n 80003c0 <SystemClock_Config+0xa6>
{
Error_Handler();
80003bc: f000 f804 bl 80003c8 <Error_Handler>
}
}
80003c0: 46c0 nop ; (mov r8, r8)
80003c2: 46bd mov sp, r7
80003c4: b015 add sp, #84 ; 0x54
80003c6: bd90 pop {r4, r7, pc}
080003c8 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80003c8: b580 push {r7, lr}
80003ca: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80003cc: b672 cpsid i
}
80003ce: 46c0 nop ; (mov r8, r8)
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80003d0: e7fe b.n 80003d0 <Error_Handler+0x8>
...
080003d4 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80003d4: b580 push {r7, lr}
80003d6: b082 sub sp, #8
80003d8: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80003da: 4b0f ldr r3, [pc, #60] ; (8000418 <HAL_MspInit+0x44>)
80003dc: 699a ldr r2, [r3, #24]
80003de: 4b0e ldr r3, [pc, #56] ; (8000418 <HAL_MspInit+0x44>)
80003e0: 2101 movs r1, #1
80003e2: 430a orrs r2, r1
80003e4: 619a str r2, [r3, #24]
80003e6: 4b0c ldr r3, [pc, #48] ; (8000418 <HAL_MspInit+0x44>)
80003e8: 699b ldr r3, [r3, #24]
80003ea: 2201 movs r2, #1
80003ec: 4013 ands r3, r2
80003ee: 607b str r3, [r7, #4]
80003f0: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
80003f2: 4b09 ldr r3, [pc, #36] ; (8000418 <HAL_MspInit+0x44>)
80003f4: 69da ldr r2, [r3, #28]
80003f6: 4b08 ldr r3, [pc, #32] ; (8000418 <HAL_MspInit+0x44>)
80003f8: 2180 movs r1, #128 ; 0x80
80003fa: 0549 lsls r1, r1, #21
80003fc: 430a orrs r2, r1
80003fe: 61da str r2, [r3, #28]
8000400: 4b05 ldr r3, [pc, #20] ; (8000418 <HAL_MspInit+0x44>)
8000402: 69da ldr r2, [r3, #28]
8000404: 2380 movs r3, #128 ; 0x80
8000406: 055b lsls r3, r3, #21
8000408: 4013 ands r3, r2
800040a: 603b str r3, [r7, #0]
800040c: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800040e: 46c0 nop ; (mov r8, r8)
8000410: 46bd mov sp, r7
8000412: b002 add sp, #8
8000414: bd80 pop {r7, pc}
8000416: 46c0 nop ; (mov r8, r8)
8000418: 40021000 .word 0x40021000
0800041c <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
800041c: b580 push {r7, lr}
800041e: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000420: e7fe b.n 8000420 <NMI_Handler+0x4>
08000422 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000422: b580 push {r7, lr}
8000424: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000426: e7fe b.n 8000426 <HardFault_Handler+0x4>
08000428 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000428: b580 push {r7, lr}
800042a: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
800042c: 46c0 nop ; (mov r8, r8)
800042e: 46bd mov sp, r7
8000430: bd80 pop {r7, pc}
08000432 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000432: b580 push {r7, lr}
8000434: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000436: 46c0 nop ; (mov r8, r8)
8000438: 46bd mov sp, r7
800043a: bd80 pop {r7, pc}
0800043c <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
800043c: b580 push {r7, lr}
800043e: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000440: f000 f90e bl 8000660 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000444: 46c0 nop ; (mov r8, r8)
8000446: 46bd mov sp, r7
8000448: bd80 pop {r7, pc}
0800044a <SystemInit>:
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
800044a: b580 push {r7, lr}
800044c: af00 add r7, sp, #0
before branch to main program. This call is made inside
the "startup_stm32f0xx.s" file.
User can setups the default system clock (System clock source, PLL Multiplier
and Divider factors, AHB/APBx prescalers and Flash settings).
*/
}
800044e: 46c0 nop ; (mov r8, r8)
8000450: 46bd mov sp, r7
8000452: bd80 pop {r7, pc}
08000454 <MX_USART1_UART_Init>:
UART_HandleTypeDef huart1;
/* USART1 init function */
void MX_USART1_UART_Init(void)
{
8000454: b580 push {r7, lr}
8000456: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
8000458: 4b14 ldr r3, [pc, #80] ; (80004ac <MX_USART1_UART_Init+0x58>)
800045a: 4a15 ldr r2, [pc, #84] ; (80004b0 <MX_USART1_UART_Init+0x5c>)
800045c: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 38400;
800045e: 4b13 ldr r3, [pc, #76] ; (80004ac <MX_USART1_UART_Init+0x58>)
8000460: 2296 movs r2, #150 ; 0x96
8000462: 0212 lsls r2, r2, #8
8000464: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8000466: 4b11 ldr r3, [pc, #68] ; (80004ac <MX_USART1_UART_Init+0x58>)
8000468: 2200 movs r2, #0
800046a: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
800046c: 4b0f ldr r3, [pc, #60] ; (80004ac <MX_USART1_UART_Init+0x58>)
800046e: 2200 movs r2, #0
8000470: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
8000472: 4b0e ldr r3, [pc, #56] ; (80004ac <MX_USART1_UART_Init+0x58>)
8000474: 2200 movs r2, #0
8000476: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8000478: 4b0c ldr r3, [pc, #48] ; (80004ac <MX_USART1_UART_Init+0x58>)
800047a: 220c movs r2, #12
800047c: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
800047e: 4b0b ldr r3, [pc, #44] ; (80004ac <MX_USART1_UART_Init+0x58>)
8000480: 2200 movs r2, #0
8000482: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
8000484: 4b09 ldr r3, [pc, #36] ; (80004ac <MX_USART1_UART_Init+0x58>)
8000486: 2200 movs r2, #0
8000488: 61da str r2, [r3, #28]
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
800048a: 4b08 ldr r3, [pc, #32] ; (80004ac <MX_USART1_UART_Init+0x58>)
800048c: 2200 movs r2, #0
800048e: 621a str r2, [r3, #32]
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8000490: 4b06 ldr r3, [pc, #24] ; (80004ac <MX_USART1_UART_Init+0x58>)
8000492: 2200 movs r2, #0
8000494: 625a str r2, [r3, #36] ; 0x24
if (HAL_UART_Init(&huart1) != HAL_OK)
8000496: 4b05 ldr r3, [pc, #20] ; (80004ac <MX_USART1_UART_Init+0x58>)
8000498: 0018 movs r0, r3
800049a: f001 f845 bl 8001528 <HAL_UART_Init>
800049e: 1e03 subs r3, r0, #0
80004a0: d001 beq.n 80004a6 <MX_USART1_UART_Init+0x52>
{
Error_Handler();
80004a2: f7ff ff91 bl 80003c8 <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
80004a6: 46c0 nop ; (mov r8, r8)
80004a8: 46bd mov sp, r7
80004aa: bd80 pop {r7, pc}
80004ac: 20000028 .word 0x20000028
80004b0: 40013800 .word 0x40013800
080004b4 <HAL_UART_MspInit>:
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
{
80004b4: b590 push {r4, r7, lr}
80004b6: b08b sub sp, #44 ; 0x2c
80004b8: af00 add r7, sp, #0
80004ba: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80004bc: 2414 movs r4, #20
80004be: 193b adds r3, r7, r4
80004c0: 0018 movs r0, r3
80004c2: 2314 movs r3, #20
80004c4: 001a movs r2, r3
80004c6: 2100 movs r1, #0
80004c8: f001 fbd4 bl 8001c74 <memset>
if(uartHandle->Instance==USART1)
80004cc: 687b ldr r3, [r7, #4]
80004ce: 681b ldr r3, [r3, #0]
80004d0: 4a1c ldr r2, [pc, #112] ; (8000544 <HAL_UART_MspInit+0x90>)
80004d2: 4293 cmp r3, r2
80004d4: d132 bne.n 800053c <HAL_UART_MspInit+0x88>
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* USART1 clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
80004d6: 4b1c ldr r3, [pc, #112] ; (8000548 <HAL_UART_MspInit+0x94>)
80004d8: 699a ldr r2, [r3, #24]
80004da: 4b1b ldr r3, [pc, #108] ; (8000548 <HAL_UART_MspInit+0x94>)
80004dc: 2180 movs r1, #128 ; 0x80
80004de: 01c9 lsls r1, r1, #7
80004e0: 430a orrs r2, r1
80004e2: 619a str r2, [r3, #24]
80004e4: 4b18 ldr r3, [pc, #96] ; (8000548 <HAL_UART_MspInit+0x94>)
80004e6: 699a ldr r2, [r3, #24]
80004e8: 2380 movs r3, #128 ; 0x80
80004ea: 01db lsls r3, r3, #7
80004ec: 4013 ands r3, r2
80004ee: 613b str r3, [r7, #16]
80004f0: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
80004f2: 4b15 ldr r3, [pc, #84] ; (8000548 <HAL_UART_MspInit+0x94>)
80004f4: 695a ldr r2, [r3, #20]
80004f6: 4b14 ldr r3, [pc, #80] ; (8000548 <HAL_UART_MspInit+0x94>)
80004f8: 2180 movs r1, #128 ; 0x80
80004fa: 0289 lsls r1, r1, #10
80004fc: 430a orrs r2, r1
80004fe: 615a str r2, [r3, #20]
8000500: 4b11 ldr r3, [pc, #68] ; (8000548 <HAL_UART_MspInit+0x94>)
8000502: 695a ldr r2, [r3, #20]
8000504: 2380 movs r3, #128 ; 0x80
8000506: 029b lsls r3, r3, #10
8000508: 4013 ands r3, r2
800050a: 60fb str r3, [r7, #12]
800050c: 68fb ldr r3, [r7, #12]
/**USART1 GPIO Configuration
PA2 ------> USART1_TX
PA15 ------> USART1_RX
*/
GPIO_InitStruct.Pin = VCP_TX_Pin|VCP_RX_Pin;
800050e: 0021 movs r1, r4
8000510: 187b adds r3, r7, r1
8000512: 4a0e ldr r2, [pc, #56] ; (800054c <HAL_UART_MspInit+0x98>)
8000514: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000516: 187b adds r3, r7, r1
8000518: 2202 movs r2, #2
800051a: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800051c: 187b adds r3, r7, r1
800051e: 2200 movs r2, #0
8000520: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8000522: 187b adds r3, r7, r1
8000524: 2203 movs r2, #3
8000526: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF1_USART1;
8000528: 187b adds r3, r7, r1
800052a: 2201 movs r2, #1
800052c: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800052e: 187a adds r2, r7, r1
8000530: 2390 movs r3, #144 ; 0x90
8000532: 05db lsls r3, r3, #23
8000534: 0011 movs r1, r2
8000536: 0018 movs r0, r3
8000538: f000 f962 bl 8000800 <HAL_GPIO_Init>
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
}
800053c: 46c0 nop ; (mov r8, r8)
800053e: 46bd mov sp, r7
8000540: b00b add sp, #44 ; 0x2c
8000542: bd90 pop {r4, r7, pc}
8000544: 40013800 .word 0x40013800
8000548: 40021000 .word 0x40021000
800054c: 00008004 .word 0x00008004
08000550 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
8000550: 480d ldr r0, [pc, #52] ; (8000588 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
8000552: 4685 mov sp, r0
/* Call the clock system initialization function.*/
bl SystemInit
8000554: f7ff ff79 bl 800044a <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000558: 480c ldr r0, [pc, #48] ; (800058c <LoopForever+0x6>)
ldr r1, =_edata
800055a: 490d ldr r1, [pc, #52] ; (8000590 <LoopForever+0xa>)
ldr r2, =_sidata
800055c: 4a0d ldr r2, [pc, #52] ; (8000594 <LoopForever+0xe>)
movs r3, #0
800055e: 2300 movs r3, #0
b LoopCopyDataInit
8000560: e002 b.n 8000568 <LoopCopyDataInit>
08000562 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000562: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000564: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000566: 3304 adds r3, #4
08000568 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000568: 18c4 adds r4, r0, r3
cmp r4, r1
800056a: 428c cmp r4, r1
bcc CopyDataInit
800056c: d3f9 bcc.n 8000562 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
800056e: 4a0a ldr r2, [pc, #40] ; (8000598 <LoopForever+0x12>)
ldr r4, =_ebss
8000570: 4c0a ldr r4, [pc, #40] ; (800059c <LoopForever+0x16>)
movs r3, #0
8000572: 2300 movs r3, #0
b LoopFillZerobss
8000574: e001 b.n 800057a <LoopFillZerobss>
08000576 <FillZerobss>:
FillZerobss:
str r3, [r2]
8000576: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000578: 3204 adds r2, #4
0800057a <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
800057a: 42a2 cmp r2, r4
bcc FillZerobss
800057c: d3fb bcc.n 8000576 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
800057e: f001 fb81 bl 8001c84 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000582: f7ff febd bl 8000300 <main>
08000586 <LoopForever>:
LoopForever:
b LoopForever
8000586: e7fe b.n 8000586 <LoopForever>
ldr r0, =_estack
8000588: 20001000 .word 0x20001000
ldr r0, =_sdata
800058c: 20000000 .word 0x20000000
ldr r1, =_edata
8000590: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000594: 08001d24 .word 0x08001d24
ldr r2, =_sbss
8000598: 2000000c .word 0x2000000c
ldr r4, =_ebss
800059c: 200000b4 .word 0x200000b4
080005a0 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80005a0: e7fe b.n 80005a0 <ADC1_IRQHandler>
080005a2 <usartSendChar>:
#ifdef KED_STM
#include "../../../peripherals/uart.h"
void usartSendChar(void* obj, uint8_t ch)
{
80005a2: b580 push {r7, lr}
80005a4: b082 sub sp, #8
80005a6: af00 add r7, sp, #0
80005a8: 6078 str r0, [r7, #4]
80005aa: 000a movs r2, r1
80005ac: 1cfb adds r3, r7, #3
80005ae: 701a strb r2, [r3, #0]
}
80005b0: 46c0 nop ; (mov r8, r8)
80005b2: 46bd mov sp, r7
80005b4: b002 add sp, #8
80005b6: bd80 pop {r7, pc}
080005b8 <reflow_main>:
#include "ked/ked.h"
#include "../Inc/usart.h"
#include "ked/peripherals/uart.h"
void reflow_main()
{
80005b8: b580 push {r7, lr}
80005ba: af00 add r7, sp, #0
usartSendChar(&huart1, 'e');
80005bc: 4b03 ldr r3, [pc, #12] ; (80005cc <reflow_main+0x14>)
80005be: 2165 movs r1, #101 ; 0x65
80005c0: 0018 movs r0, r3
80005c2: f7ff ffee bl 80005a2 <usartSendChar>
}
80005c6: 46c0 nop ; (mov r8, r8)
80005c8: 46bd mov sp, r7
80005ca: bd80 pop {r7, pc}
80005cc: 20000028 .word 0x20000028
080005d0 <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* The tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80005d0: b580 push {r7, lr}
80005d2: af00 add r7, sp, #0
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
80005d4: 4b07 ldr r3, [pc, #28] ; (80005f4 <HAL_Init+0x24>)
80005d6: 681a ldr r2, [r3, #0]
80005d8: 4b06 ldr r3, [pc, #24] ; (80005f4 <HAL_Init+0x24>)
80005da: 2110 movs r1, #16
80005dc: 430a orrs r2, r1
80005de: 601a str r2, [r3, #0]
#endif /* PREFETCH_ENABLE */
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
80005e0: 2000 movs r0, #0
80005e2: f000 f809 bl 80005f8 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
80005e6: f7ff fef5 bl 80003d4 <HAL_MspInit>
/* Return function status */
return HAL_OK;
80005ea: 2300 movs r3, #0
}
80005ec: 0018 movs r0, r3
80005ee: 46bd mov sp, r7
80005f0: bd80 pop {r7, pc}
80005f2: 46c0 nop ; (mov r8, r8)
80005f4: 40022000 .word 0x40022000
080005f8 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80005f8: b590 push {r4, r7, lr}
80005fa: b083 sub sp, #12
80005fc: af00 add r7, sp, #0
80005fe: 6078 str r0, [r7, #4]
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000600: 4b14 ldr r3, [pc, #80] ; (8000654 <HAL_InitTick+0x5c>)
8000602: 681c ldr r4, [r3, #0]
8000604: 4b14 ldr r3, [pc, #80] ; (8000658 <HAL_InitTick+0x60>)
8000606: 781b ldrb r3, [r3, #0]
8000608: 0019 movs r1, r3
800060a: 23fa movs r3, #250 ; 0xfa
800060c: 0098 lsls r0, r3, #2
800060e: f7ff fd7b bl 8000108 <__udivsi3>
8000612: 0003 movs r3, r0
8000614: 0019 movs r1, r3
8000616: 0020 movs r0, r4
8000618: f7ff fd76 bl 8000108 <__udivsi3>
800061c: 0003 movs r3, r0
800061e: 0018 movs r0, r3
8000620: f000 f8e1 bl 80007e6 <HAL_SYSTICK_Config>
8000624: 1e03 subs r3, r0, #0
8000626: d001 beq.n 800062c <HAL_InitTick+0x34>
{
return HAL_ERROR;
8000628: 2301 movs r3, #1
800062a: e00f b.n 800064c <HAL_InitTick+0x54>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
800062c: 687b ldr r3, [r7, #4]
800062e: 2b03 cmp r3, #3
8000630: d80b bhi.n 800064a <HAL_InitTick+0x52>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000632: 6879 ldr r1, [r7, #4]
8000634: 2301 movs r3, #1
8000636: 425b negs r3, r3
8000638: 2200 movs r2, #0
800063a: 0018 movs r0, r3
800063c: f000 f8be bl 80007bc <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000640: 4b06 ldr r3, [pc, #24] ; (800065c <HAL_InitTick+0x64>)
8000642: 687a ldr r2, [r7, #4]
8000644: 601a str r2, [r3, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000646: 2300 movs r3, #0
8000648: e000 b.n 800064c <HAL_InitTick+0x54>
return HAL_ERROR;
800064a: 2301 movs r3, #1
}
800064c: 0018 movs r0, r3
800064e: 46bd mov sp, r7
8000650: b003 add sp, #12
8000652: bd90 pop {r4, r7, pc}
8000654: 20000000 .word 0x20000000
8000658: 20000008 .word 0x20000008
800065c: 20000004 .word 0x20000004
08000660 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000660: b580 push {r7, lr}
8000662: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000664: 4b05 ldr r3, [pc, #20] ; (800067c <HAL_IncTick+0x1c>)
8000666: 781b ldrb r3, [r3, #0]
8000668: 001a movs r2, r3
800066a: 4b05 ldr r3, [pc, #20] ; (8000680 <HAL_IncTick+0x20>)
800066c: 681b ldr r3, [r3, #0]
800066e: 18d2 adds r2, r2, r3
8000670: 4b03 ldr r3, [pc, #12] ; (8000680 <HAL_IncTick+0x20>)
8000672: 601a str r2, [r3, #0]
}
8000674: 46c0 nop ; (mov r8, r8)
8000676: 46bd mov sp, r7
8000678: bd80 pop {r7, pc}
800067a: 46c0 nop ; (mov r8, r8)
800067c: 20000008 .word 0x20000008
8000680: 200000b0 .word 0x200000b0
08000684 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000684: b580 push {r7, lr}
8000686: af00 add r7, sp, #0
return uwTick;
8000688: 4b02 ldr r3, [pc, #8] ; (8000694 <HAL_GetTick+0x10>)
800068a: 681b ldr r3, [r3, #0]
}
800068c: 0018 movs r0, r3
800068e: 46bd mov sp, r7
8000690: bd80 pop {r7, pc}
8000692: 46c0 nop ; (mov r8, r8)
8000694: 200000b0 .word 0x200000b0
08000698 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000698: b590 push {r4, r7, lr}
800069a: b083 sub sp, #12
800069c: af00 add r7, sp, #0
800069e: 0002 movs r2, r0
80006a0: 6039 str r1, [r7, #0]
80006a2: 1dfb adds r3, r7, #7
80006a4: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
80006a6: 1dfb adds r3, r7, #7
80006a8: 781b ldrb r3, [r3, #0]
80006aa: 2b7f cmp r3, #127 ; 0x7f
80006ac: d828 bhi.n 8000700 <__NVIC_SetPriority+0x68>
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80006ae: 4a2f ldr r2, [pc, #188] ; (800076c <__NVIC_SetPriority+0xd4>)
80006b0: 1dfb adds r3, r7, #7
80006b2: 781b ldrb r3, [r3, #0]
80006b4: b25b sxtb r3, r3
80006b6: 089b lsrs r3, r3, #2
80006b8: 33c0 adds r3, #192 ; 0xc0
80006ba: 009b lsls r3, r3, #2
80006bc: 589b ldr r3, [r3, r2]
80006be: 1dfa adds r2, r7, #7
80006c0: 7812 ldrb r2, [r2, #0]
80006c2: 0011 movs r1, r2
80006c4: 2203 movs r2, #3
80006c6: 400a ands r2, r1
80006c8: 00d2 lsls r2, r2, #3
80006ca: 21ff movs r1, #255 ; 0xff
80006cc: 4091 lsls r1, r2
80006ce: 000a movs r2, r1
80006d0: 43d2 mvns r2, r2
80006d2: 401a ands r2, r3
80006d4: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
80006d6: 683b ldr r3, [r7, #0]
80006d8: 019b lsls r3, r3, #6
80006da: 22ff movs r2, #255 ; 0xff
80006dc: 401a ands r2, r3
80006de: 1dfb adds r3, r7, #7
80006e0: 781b ldrb r3, [r3, #0]
80006e2: 0018 movs r0, r3
80006e4: 2303 movs r3, #3
80006e6: 4003 ands r3, r0
80006e8: 00db lsls r3, r3, #3
80006ea: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80006ec: 481f ldr r0, [pc, #124] ; (800076c <__NVIC_SetPriority+0xd4>)
80006ee: 1dfb adds r3, r7, #7
80006f0: 781b ldrb r3, [r3, #0]
80006f2: b25b sxtb r3, r3
80006f4: 089b lsrs r3, r3, #2
80006f6: 430a orrs r2, r1
80006f8: 33c0 adds r3, #192 ; 0xc0
80006fa: 009b lsls r3, r3, #2
80006fc: 501a str r2, [r3, r0]
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
80006fe: e031 b.n 8000764 <__NVIC_SetPriority+0xcc>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000700: 4a1b ldr r2, [pc, #108] ; (8000770 <__NVIC_SetPriority+0xd8>)
8000702: 1dfb adds r3, r7, #7
8000704: 781b ldrb r3, [r3, #0]
8000706: 0019 movs r1, r3
8000708: 230f movs r3, #15
800070a: 400b ands r3, r1
800070c: 3b08 subs r3, #8
800070e: 089b lsrs r3, r3, #2
8000710: 3306 adds r3, #6
8000712: 009b lsls r3, r3, #2
8000714: 18d3 adds r3, r2, r3
8000716: 3304 adds r3, #4
8000718: 681b ldr r3, [r3, #0]
800071a: 1dfa adds r2, r7, #7
800071c: 7812 ldrb r2, [r2, #0]
800071e: 0011 movs r1, r2
8000720: 2203 movs r2, #3
8000722: 400a ands r2, r1
8000724: 00d2 lsls r2, r2, #3
8000726: 21ff movs r1, #255 ; 0xff
8000728: 4091 lsls r1, r2
800072a: 000a movs r2, r1
800072c: 43d2 mvns r2, r2
800072e: 401a ands r2, r3
8000730: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8000732: 683b ldr r3, [r7, #0]
8000734: 019b lsls r3, r3, #6
8000736: 22ff movs r2, #255 ; 0xff
8000738: 401a ands r2, r3
800073a: 1dfb adds r3, r7, #7
800073c: 781b ldrb r3, [r3, #0]
800073e: 0018 movs r0, r3
8000740: 2303 movs r3, #3
8000742: 4003 ands r3, r0
8000744: 00db lsls r3, r3, #3
8000746: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000748: 4809 ldr r0, [pc, #36] ; (8000770 <__NVIC_SetPriority+0xd8>)
800074a: 1dfb adds r3, r7, #7
800074c: 781b ldrb r3, [r3, #0]
800074e: 001c movs r4, r3
8000750: 230f movs r3, #15
8000752: 4023 ands r3, r4
8000754: 3b08 subs r3, #8
8000756: 089b lsrs r3, r3, #2
8000758: 430a orrs r2, r1
800075a: 3306 adds r3, #6
800075c: 009b lsls r3, r3, #2
800075e: 18c3 adds r3, r0, r3
8000760: 3304 adds r3, #4
8000762: 601a str r2, [r3, #0]
}
8000764: 46c0 nop ; (mov r8, r8)
8000766: 46bd mov sp, r7
8000768: b003 add sp, #12
800076a: bd90 pop {r4, r7, pc}
800076c: e000e100 .word 0xe000e100
8000770: e000ed00 .word 0xe000ed00
08000774 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000774: b580 push {r7, lr}
8000776: b082 sub sp, #8
8000778: af00 add r7, sp, #0
800077a: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
800077c: 687b ldr r3, [r7, #4]
800077e: 1e5a subs r2, r3, #1
8000780: 2380 movs r3, #128 ; 0x80
8000782: 045b lsls r3, r3, #17
8000784: 429a cmp r2, r3
8000786: d301 bcc.n 800078c <SysTick_Config+0x18>
{
return (1UL); /* Reload value impossible */
8000788: 2301 movs r3, #1
800078a: e010 b.n 80007ae <SysTick_Config+0x3a>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
800078c: 4b0a ldr r3, [pc, #40] ; (80007b8 <SysTick_Config+0x44>)
800078e: 687a ldr r2, [r7, #4]
8000790: 3a01 subs r2, #1
8000792: 605a str r2, [r3, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000794: 2301 movs r3, #1
8000796: 425b negs r3, r3
8000798: 2103 movs r1, #3
800079a: 0018 movs r0, r3
800079c: f7ff ff7c bl 8000698 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80007a0: 4b05 ldr r3, [pc, #20] ; (80007b8 <SysTick_Config+0x44>)
80007a2: 2200 movs r2, #0
80007a4: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80007a6: 4b04 ldr r3, [pc, #16] ; (80007b8 <SysTick_Config+0x44>)
80007a8: 2207 movs r2, #7
80007aa: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
80007ac: 2300 movs r3, #0
}
80007ae: 0018 movs r0, r3
80007b0: 46bd mov sp, r7
80007b2: b002 add sp, #8
80007b4: bd80 pop {r7, pc}
80007b6: 46c0 nop ; (mov r8, r8)
80007b8: e000e010 .word 0xe000e010
080007bc <HAL_NVIC_SetPriority>:
* with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0 based products.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
80007bc: b580 push {r7, lr}
80007be: b084 sub sp, #16
80007c0: af00 add r7, sp, #0
80007c2: 60b9 str r1, [r7, #8]
80007c4: 607a str r2, [r7, #4]
80007c6: 210f movs r1, #15
80007c8: 187b adds r3, r7, r1
80007ca: 1c02 adds r2, r0, #0
80007cc: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NVIC_SetPriority(IRQn,PreemptPriority);
80007ce: 68ba ldr r2, [r7, #8]
80007d0: 187b adds r3, r7, r1
80007d2: 781b ldrb r3, [r3, #0]
80007d4: b25b sxtb r3, r3
80007d6: 0011 movs r1, r2
80007d8: 0018 movs r0, r3
80007da: f7ff ff5d bl 8000698 <__NVIC_SetPriority>
}
80007de: 46c0 nop ; (mov r8, r8)
80007e0: 46bd mov sp, r7
80007e2: b004 add sp, #16
80007e4: bd80 pop {r7, pc}
080007e6 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80007e6: b580 push {r7, lr}
80007e8: b082 sub sp, #8
80007ea: af00 add r7, sp, #0
80007ec: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80007ee: 687b ldr r3, [r7, #4]
80007f0: 0018 movs r0, r3
80007f2: f7ff ffbf bl 8000774 <SysTick_Config>
80007f6: 0003 movs r3, r0
}
80007f8: 0018 movs r0, r3
80007fa: 46bd mov sp, r7
80007fc: b002 add sp, #8
80007fe: bd80 pop {r7, pc}
08000800 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000800: b580 push {r7, lr}
8000802: b086 sub sp, #24
8000804: af00 add r7, sp, #0
8000806: 6078 str r0, [r7, #4]
8000808: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
800080a: 2300 movs r3, #0
800080c: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
800080e: e149 b.n 8000aa4 <HAL_GPIO_Init+0x2a4>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
8000810: 683b ldr r3, [r7, #0]
8000812: 681b ldr r3, [r3, #0]
8000814: 2101 movs r1, #1
8000816: 697a ldr r2, [r7, #20]
8000818: 4091 lsls r1, r2
800081a: 000a movs r2, r1
800081c: 4013 ands r3, r2
800081e: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8000820: 68fb ldr r3, [r7, #12]
8000822: 2b00 cmp r3, #0
8000824: d100 bne.n 8000828 <HAL_GPIO_Init+0x28>
8000826: e13a b.n 8000a9e <HAL_GPIO_Init+0x29e>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8000828: 683b ldr r3, [r7, #0]
800082a: 685b ldr r3, [r3, #4]
800082c: 2203 movs r2, #3
800082e: 4013 ands r3, r2
8000830: 2b01 cmp r3, #1
8000832: d005 beq.n 8000840 <HAL_GPIO_Init+0x40>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8000834: 683b ldr r3, [r7, #0]
8000836: 685b ldr r3, [r3, #4]
8000838: 2203 movs r2, #3
800083a: 4013 ands r3, r2
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
800083c: 2b02 cmp r3, #2
800083e: d130 bne.n 80008a2 <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8000840: 687b ldr r3, [r7, #4]
8000842: 689b ldr r3, [r3, #8]
8000844: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
8000846: 697b ldr r3, [r7, #20]
8000848: 005b lsls r3, r3, #1
800084a: 2203 movs r2, #3
800084c: 409a lsls r2, r3
800084e: 0013 movs r3, r2
8000850: 43da mvns r2, r3
8000852: 693b ldr r3, [r7, #16]
8000854: 4013 ands r3, r2
8000856: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8000858: 683b ldr r3, [r7, #0]
800085a: 68da ldr r2, [r3, #12]
800085c: 697b ldr r3, [r7, #20]
800085e: 005b lsls r3, r3, #1
8000860: 409a lsls r2, r3
8000862: 0013 movs r3, r2
8000864: 693a ldr r2, [r7, #16]
8000866: 4313 orrs r3, r2
8000868: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
800086a: 687b ldr r3, [r7, #4]
800086c: 693a ldr r2, [r7, #16]
800086e: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8000870: 687b ldr r3, [r7, #4]
8000872: 685b ldr r3, [r3, #4]
8000874: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8000876: 2201 movs r2, #1
8000878: 697b ldr r3, [r7, #20]
800087a: 409a lsls r2, r3
800087c: 0013 movs r3, r2
800087e: 43da mvns r2, r3
8000880: 693b ldr r3, [r7, #16]
8000882: 4013 ands r3, r2
8000884: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8000886: 683b ldr r3, [r7, #0]
8000888: 685b ldr r3, [r3, #4]
800088a: 091b lsrs r3, r3, #4
800088c: 2201 movs r2, #1
800088e: 401a ands r2, r3
8000890: 697b ldr r3, [r7, #20]
8000892: 409a lsls r2, r3
8000894: 0013 movs r3, r2
8000896: 693a ldr r2, [r7, #16]
8000898: 4313 orrs r3, r2
800089a: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
800089c: 687b ldr r3, [r7, #4]
800089e: 693a ldr r2, [r7, #16]
80008a0: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
80008a2: 683b ldr r3, [r7, #0]
80008a4: 685b ldr r3, [r3, #4]
80008a6: 2203 movs r2, #3
80008a8: 4013 ands r3, r2
80008aa: 2b03 cmp r3, #3
80008ac: d017 beq.n 80008de <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80008ae: 687b ldr r3, [r7, #4]
80008b0: 68db ldr r3, [r3, #12]
80008b2: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
80008b4: 697b ldr r3, [r7, #20]
80008b6: 005b lsls r3, r3, #1
80008b8: 2203 movs r2, #3
80008ba: 409a lsls r2, r3
80008bc: 0013 movs r3, r2
80008be: 43da mvns r2, r3
80008c0: 693b ldr r3, [r7, #16]
80008c2: 4013 ands r3, r2
80008c4: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
80008c6: 683b ldr r3, [r7, #0]
80008c8: 689a ldr r2, [r3, #8]
80008ca: 697b ldr r3, [r7, #20]
80008cc: 005b lsls r3, r3, #1
80008ce: 409a lsls r2, r3
80008d0: 0013 movs r3, r2
80008d2: 693a ldr r2, [r7, #16]
80008d4: 4313 orrs r3, r2
80008d6: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
80008d8: 687b ldr r3, [r7, #4]
80008da: 693a ldr r2, [r7, #16]
80008dc: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80008de: 683b ldr r3, [r7, #0]
80008e0: 685b ldr r3, [r3, #4]
80008e2: 2203 movs r2, #3
80008e4: 4013 ands r3, r2
80008e6: 2b02 cmp r3, #2
80008e8: d123 bne.n 8000932 <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
80008ea: 697b ldr r3, [r7, #20]
80008ec: 08da lsrs r2, r3, #3
80008ee: 687b ldr r3, [r7, #4]
80008f0: 3208 adds r2, #8
80008f2: 0092 lsls r2, r2, #2
80008f4: 58d3 ldr r3, [r2, r3]
80008f6: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
80008f8: 697b ldr r3, [r7, #20]
80008fa: 2207 movs r2, #7
80008fc: 4013 ands r3, r2
80008fe: 009b lsls r3, r3, #2
8000900: 220f movs r2, #15
8000902: 409a lsls r2, r3
8000904: 0013 movs r3, r2
8000906: 43da mvns r2, r3
8000908: 693b ldr r3, [r7, #16]
800090a: 4013 ands r3, r2
800090c: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
800090e: 683b ldr r3, [r7, #0]
8000910: 691a ldr r2, [r3, #16]
8000912: 697b ldr r3, [r7, #20]
8000914: 2107 movs r1, #7
8000916: 400b ands r3, r1
8000918: 009b lsls r3, r3, #2
800091a: 409a lsls r2, r3
800091c: 0013 movs r3, r2
800091e: 693a ldr r2, [r7, #16]
8000920: 4313 orrs r3, r2
8000922: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8000924: 697b ldr r3, [r7, #20]
8000926: 08da lsrs r2, r3, #3
8000928: 687b ldr r3, [r7, #4]
800092a: 3208 adds r2, #8
800092c: 0092 lsls r2, r2, #2
800092e: 6939 ldr r1, [r7, #16]
8000930: 50d1 str r1, [r2, r3]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8000932: 687b ldr r3, [r7, #4]
8000934: 681b ldr r3, [r3, #0]
8000936: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
8000938: 697b ldr r3, [r7, #20]
800093a: 005b lsls r3, r3, #1
800093c: 2203 movs r2, #3
800093e: 409a lsls r2, r3
8000940: 0013 movs r3, r2
8000942: 43da mvns r2, r3
8000944: 693b ldr r3, [r7, #16]
8000946: 4013 ands r3, r2
8000948: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
800094a: 683b ldr r3, [r7, #0]
800094c: 685b ldr r3, [r3, #4]
800094e: 2203 movs r2, #3
8000950: 401a ands r2, r3
8000952: 697b ldr r3, [r7, #20]
8000954: 005b lsls r3, r3, #1
8000956: 409a lsls r2, r3
8000958: 0013 movs r3, r2
800095a: 693a ldr r2, [r7, #16]
800095c: 4313 orrs r3, r2
800095e: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8000960: 687b ldr r3, [r7, #4]
8000962: 693a ldr r2, [r7, #16]
8000964: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8000966: 683b ldr r3, [r7, #0]
8000968: 685a ldr r2, [r3, #4]
800096a: 23c0 movs r3, #192 ; 0xc0
800096c: 029b lsls r3, r3, #10
800096e: 4013 ands r3, r2
8000970: d100 bne.n 8000974 <HAL_GPIO_Init+0x174>
8000972: e094 b.n 8000a9e <HAL_GPIO_Init+0x29e>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000974: 4b51 ldr r3, [pc, #324] ; (8000abc <HAL_GPIO_Init+0x2bc>)
8000976: 699a ldr r2, [r3, #24]
8000978: 4b50 ldr r3, [pc, #320] ; (8000abc <HAL_GPIO_Init+0x2bc>)
800097a: 2101 movs r1, #1
800097c: 430a orrs r2, r1
800097e: 619a str r2, [r3, #24]
8000980: 4b4e ldr r3, [pc, #312] ; (8000abc <HAL_GPIO_Init+0x2bc>)
8000982: 699b ldr r3, [r3, #24]
8000984: 2201 movs r2, #1
8000986: 4013 ands r3, r2
8000988: 60bb str r3, [r7, #8]
800098a: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
800098c: 4a4c ldr r2, [pc, #304] ; (8000ac0 <HAL_GPIO_Init+0x2c0>)
800098e: 697b ldr r3, [r7, #20]
8000990: 089b lsrs r3, r3, #2
8000992: 3302 adds r3, #2
8000994: 009b lsls r3, r3, #2
8000996: 589b ldr r3, [r3, r2]
8000998: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
800099a: 697b ldr r3, [r7, #20]
800099c: 2203 movs r2, #3
800099e: 4013 ands r3, r2
80009a0: 009b lsls r3, r3, #2
80009a2: 220f movs r2, #15
80009a4: 409a lsls r2, r3
80009a6: 0013 movs r3, r2
80009a8: 43da mvns r2, r3
80009aa: 693b ldr r3, [r7, #16]
80009ac: 4013 ands r3, r2
80009ae: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
80009b0: 687a ldr r2, [r7, #4]
80009b2: 2390 movs r3, #144 ; 0x90
80009b4: 05db lsls r3, r3, #23
80009b6: 429a cmp r2, r3
80009b8: d00d beq.n 80009d6 <HAL_GPIO_Init+0x1d6>
80009ba: 687b ldr r3, [r7, #4]
80009bc: 4a41 ldr r2, [pc, #260] ; (8000ac4 <HAL_GPIO_Init+0x2c4>)
80009be: 4293 cmp r3, r2
80009c0: d007 beq.n 80009d2 <HAL_GPIO_Init+0x1d2>
80009c2: 687b ldr r3, [r7, #4]
80009c4: 4a40 ldr r2, [pc, #256] ; (8000ac8 <HAL_GPIO_Init+0x2c8>)
80009c6: 4293 cmp r3, r2
80009c8: d101 bne.n 80009ce <HAL_GPIO_Init+0x1ce>
80009ca: 2302 movs r3, #2
80009cc: e004 b.n 80009d8 <HAL_GPIO_Init+0x1d8>
80009ce: 2305 movs r3, #5
80009d0: e002 b.n 80009d8 <HAL_GPIO_Init+0x1d8>
80009d2: 2301 movs r3, #1
80009d4: e000 b.n 80009d8 <HAL_GPIO_Init+0x1d8>
80009d6: 2300 movs r3, #0
80009d8: 697a ldr r2, [r7, #20]
80009da: 2103 movs r1, #3
80009dc: 400a ands r2, r1
80009de: 0092 lsls r2, r2, #2
80009e0: 4093 lsls r3, r2
80009e2: 693a ldr r2, [r7, #16]
80009e4: 4313 orrs r3, r2
80009e6: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
80009e8: 4935 ldr r1, [pc, #212] ; (8000ac0 <HAL_GPIO_Init+0x2c0>)
80009ea: 697b ldr r3, [r7, #20]
80009ec: 089b lsrs r3, r3, #2
80009ee: 3302 adds r3, #2
80009f0: 009b lsls r3, r3, #2
80009f2: 693a ldr r2, [r7, #16]
80009f4: 505a str r2, [r3, r1]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
80009f6: 4b35 ldr r3, [pc, #212] ; (8000acc <HAL_GPIO_Init+0x2cc>)
80009f8: 689b ldr r3, [r3, #8]
80009fa: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80009fc: 68fb ldr r3, [r7, #12]
80009fe: 43da mvns r2, r3
8000a00: 693b ldr r3, [r7, #16]
8000a02: 4013 ands r3, r2
8000a04: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8000a06: 683b ldr r3, [r7, #0]
8000a08: 685a ldr r2, [r3, #4]
8000a0a: 2380 movs r3, #128 ; 0x80
8000a0c: 035b lsls r3, r3, #13
8000a0e: 4013 ands r3, r2
8000a10: d003 beq.n 8000a1a <HAL_GPIO_Init+0x21a>
{
temp |= iocurrent;
8000a12: 693a ldr r2, [r7, #16]
8000a14: 68fb ldr r3, [r7, #12]
8000a16: 4313 orrs r3, r2
8000a18: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
8000a1a: 4b2c ldr r3, [pc, #176] ; (8000acc <HAL_GPIO_Init+0x2cc>)
8000a1c: 693a ldr r2, [r7, #16]
8000a1e: 609a str r2, [r3, #8]
temp = EXTI->FTSR;
8000a20: 4b2a ldr r3, [pc, #168] ; (8000acc <HAL_GPIO_Init+0x2cc>)
8000a22: 68db ldr r3, [r3, #12]
8000a24: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000a26: 68fb ldr r3, [r7, #12]
8000a28: 43da mvns r2, r3
8000a2a: 693b ldr r3, [r7, #16]
8000a2c: 4013 ands r3, r2
8000a2e: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8000a30: 683b ldr r3, [r7, #0]
8000a32: 685a ldr r2, [r3, #4]
8000a34: 2380 movs r3, #128 ; 0x80
8000a36: 039b lsls r3, r3, #14
8000a38: 4013 ands r3, r2
8000a3a: d003 beq.n 8000a44 <HAL_GPIO_Init+0x244>
{
temp |= iocurrent;
8000a3c: 693a ldr r2, [r7, #16]
8000a3e: 68fb ldr r3, [r7, #12]
8000a40: 4313 orrs r3, r2
8000a42: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
8000a44: 4b21 ldr r3, [pc, #132] ; (8000acc <HAL_GPIO_Init+0x2cc>)
8000a46: 693a ldr r2, [r7, #16]
8000a48: 60da str r2, [r3, #12]
/* Clear EXTI line configuration */
temp = EXTI->EMR;
8000a4a: 4b20 ldr r3, [pc, #128] ; (8000acc <HAL_GPIO_Init+0x2cc>)
8000a4c: 685b ldr r3, [r3, #4]
8000a4e: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000a50: 68fb ldr r3, [r7, #12]
8000a52: 43da mvns r2, r3
8000a54: 693b ldr r3, [r7, #16]
8000a56: 4013 ands r3, r2
8000a58: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8000a5a: 683b ldr r3, [r7, #0]
8000a5c: 685a ldr r2, [r3, #4]
8000a5e: 2380 movs r3, #128 ; 0x80
8000a60: 029b lsls r3, r3, #10
8000a62: 4013 ands r3, r2
8000a64: d003 beq.n 8000a6e <HAL_GPIO_Init+0x26e>
{
temp |= iocurrent;
8000a66: 693a ldr r2, [r7, #16]
8000a68: 68fb ldr r3, [r7, #12]
8000a6a: 4313 orrs r3, r2
8000a6c: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
8000a6e: 4b17 ldr r3, [pc, #92] ; (8000acc <HAL_GPIO_Init+0x2cc>)
8000a70: 693a ldr r2, [r7, #16]
8000a72: 605a str r2, [r3, #4]
temp = EXTI->IMR;
8000a74: 4b15 ldr r3, [pc, #84] ; (8000acc <HAL_GPIO_Init+0x2cc>)
8000a76: 681b ldr r3, [r3, #0]
8000a78: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000a7a: 68fb ldr r3, [r7, #12]
8000a7c: 43da mvns r2, r3
8000a7e: 693b ldr r3, [r7, #16]
8000a80: 4013 ands r3, r2
8000a82: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8000a84: 683b ldr r3, [r7, #0]
8000a86: 685a ldr r2, [r3, #4]
8000a88: 2380 movs r3, #128 ; 0x80
8000a8a: 025b lsls r3, r3, #9
8000a8c: 4013 ands r3, r2
8000a8e: d003 beq.n 8000a98 <HAL_GPIO_Init+0x298>
{
temp |= iocurrent;
8000a90: 693a ldr r2, [r7, #16]
8000a92: 68fb ldr r3, [r7, #12]
8000a94: 4313 orrs r3, r2
8000a96: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
8000a98: 4b0c ldr r3, [pc, #48] ; (8000acc <HAL_GPIO_Init+0x2cc>)
8000a9a: 693a ldr r2, [r7, #16]
8000a9c: 601a str r2, [r3, #0]
}
}
position++;
8000a9e: 697b ldr r3, [r7, #20]
8000aa0: 3301 adds r3, #1
8000aa2: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000aa4: 683b ldr r3, [r7, #0]
8000aa6: 681a ldr r2, [r3, #0]
8000aa8: 697b ldr r3, [r7, #20]
8000aaa: 40da lsrs r2, r3
8000aac: 1e13 subs r3, r2, #0
8000aae: d000 beq.n 8000ab2 <HAL_GPIO_Init+0x2b2>
8000ab0: e6ae b.n 8000810 <HAL_GPIO_Init+0x10>
}
}
8000ab2: 46c0 nop ; (mov r8, r8)
8000ab4: 46c0 nop ; (mov r8, r8)
8000ab6: 46bd mov sp, r7
8000ab8: b006 add sp, #24
8000aba: bd80 pop {r7, pc}
8000abc: 40021000 .word 0x40021000
8000ac0: 40010000 .word 0x40010000
8000ac4: 48000400 .word 0x48000400
8000ac8: 48000800 .word 0x48000800
8000acc: 40010400 .word 0x40010400
08000ad0 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8000ad0: b580 push {r7, lr}
8000ad2: b088 sub sp, #32
8000ad4: af00 add r7, sp, #0
8000ad6: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
uint32_t pll_config2;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8000ad8: 687b ldr r3, [r7, #4]
8000ada: 2b00 cmp r3, #0
8000adc: d101 bne.n 8000ae2 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8000ade: 2301 movs r3, #1
8000ae0: e301 b.n 80010e6 <HAL_RCC_OscConfig+0x616>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8000ae2: 687b ldr r3, [r7, #4]
8000ae4: 681b ldr r3, [r3, #0]
8000ae6: 2201 movs r2, #1
8000ae8: 4013 ands r3, r2
8000aea: d100 bne.n 8000aee <HAL_RCC_OscConfig+0x1e>
8000aec: e08d b.n 8000c0a <HAL_RCC_OscConfig+0x13a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8000aee: 4bc3 ldr r3, [pc, #780] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000af0: 685b ldr r3, [r3, #4]
8000af2: 220c movs r2, #12
8000af4: 4013 ands r3, r2
8000af6: 2b04 cmp r3, #4
8000af8: d00e beq.n 8000b18 <HAL_RCC_OscConfig+0x48>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8000afa: 4bc0 ldr r3, [pc, #768] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000afc: 685b ldr r3, [r3, #4]
8000afe: 220c movs r2, #12
8000b00: 4013 ands r3, r2
8000b02: 2b08 cmp r3, #8
8000b04: d116 bne.n 8000b34 <HAL_RCC_OscConfig+0x64>
8000b06: 4bbd ldr r3, [pc, #756] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000b08: 685a ldr r2, [r3, #4]
8000b0a: 2380 movs r3, #128 ; 0x80
8000b0c: 025b lsls r3, r3, #9
8000b0e: 401a ands r2, r3
8000b10: 2380 movs r3, #128 ; 0x80
8000b12: 025b lsls r3, r3, #9
8000b14: 429a cmp r2, r3
8000b16: d10d bne.n 8000b34 <HAL_RCC_OscConfig+0x64>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000b18: 4bb8 ldr r3, [pc, #736] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000b1a: 681a ldr r2, [r3, #0]
8000b1c: 2380 movs r3, #128 ; 0x80
8000b1e: 029b lsls r3, r3, #10
8000b20: 4013 ands r3, r2
8000b22: d100 bne.n 8000b26 <HAL_RCC_OscConfig+0x56>
8000b24: e070 b.n 8000c08 <HAL_RCC_OscConfig+0x138>
8000b26: 687b ldr r3, [r7, #4]
8000b28: 685b ldr r3, [r3, #4]
8000b2a: 2b00 cmp r3, #0
8000b2c: d000 beq.n 8000b30 <HAL_RCC_OscConfig+0x60>
8000b2e: e06b b.n 8000c08 <HAL_RCC_OscConfig+0x138>
{
return HAL_ERROR;
8000b30: 2301 movs r3, #1
8000b32: e2d8 b.n 80010e6 <HAL_RCC_OscConfig+0x616>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8000b34: 687b ldr r3, [r7, #4]
8000b36: 685b ldr r3, [r3, #4]
8000b38: 2b01 cmp r3, #1
8000b3a: d107 bne.n 8000b4c <HAL_RCC_OscConfig+0x7c>
8000b3c: 4baf ldr r3, [pc, #700] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000b3e: 681a ldr r2, [r3, #0]
8000b40: 4bae ldr r3, [pc, #696] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000b42: 2180 movs r1, #128 ; 0x80
8000b44: 0249 lsls r1, r1, #9
8000b46: 430a orrs r2, r1
8000b48: 601a str r2, [r3, #0]
8000b4a: e02f b.n 8000bac <HAL_RCC_OscConfig+0xdc>
8000b4c: 687b ldr r3, [r7, #4]
8000b4e: 685b ldr r3, [r3, #4]
8000b50: 2b00 cmp r3, #0
8000b52: d10c bne.n 8000b6e <HAL_RCC_OscConfig+0x9e>
8000b54: 4ba9 ldr r3, [pc, #676] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000b56: 681a ldr r2, [r3, #0]
8000b58: 4ba8 ldr r3, [pc, #672] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000b5a: 49a9 ldr r1, [pc, #676] ; (8000e00 <HAL_RCC_OscConfig+0x330>)
8000b5c: 400a ands r2, r1
8000b5e: 601a str r2, [r3, #0]
8000b60: 4ba6 ldr r3, [pc, #664] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000b62: 681a ldr r2, [r3, #0]
8000b64: 4ba5 ldr r3, [pc, #660] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000b66: 49a7 ldr r1, [pc, #668] ; (8000e04 <HAL_RCC_OscConfig+0x334>)
8000b68: 400a ands r2, r1
8000b6a: 601a str r2, [r3, #0]
8000b6c: e01e b.n 8000bac <HAL_RCC_OscConfig+0xdc>
8000b6e: 687b ldr r3, [r7, #4]
8000b70: 685b ldr r3, [r3, #4]
8000b72: 2b05 cmp r3, #5
8000b74: d10e bne.n 8000b94 <HAL_RCC_OscConfig+0xc4>
8000b76: 4ba1 ldr r3, [pc, #644] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000b78: 681a ldr r2, [r3, #0]
8000b7a: 4ba0 ldr r3, [pc, #640] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000b7c: 2180 movs r1, #128 ; 0x80
8000b7e: 02c9 lsls r1, r1, #11
8000b80: 430a orrs r2, r1
8000b82: 601a str r2, [r3, #0]
8000b84: 4b9d ldr r3, [pc, #628] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000b86: 681a ldr r2, [r3, #0]
8000b88: 4b9c ldr r3, [pc, #624] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000b8a: 2180 movs r1, #128 ; 0x80
8000b8c: 0249 lsls r1, r1, #9
8000b8e: 430a orrs r2, r1
8000b90: 601a str r2, [r3, #0]
8000b92: e00b b.n 8000bac <HAL_RCC_OscConfig+0xdc>
8000b94: 4b99 ldr r3, [pc, #612] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000b96: 681a ldr r2, [r3, #0]
8000b98: 4b98 ldr r3, [pc, #608] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000b9a: 4999 ldr r1, [pc, #612] ; (8000e00 <HAL_RCC_OscConfig+0x330>)
8000b9c: 400a ands r2, r1
8000b9e: 601a str r2, [r3, #0]
8000ba0: 4b96 ldr r3, [pc, #600] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000ba2: 681a ldr r2, [r3, #0]
8000ba4: 4b95 ldr r3, [pc, #596] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000ba6: 4997 ldr r1, [pc, #604] ; (8000e04 <HAL_RCC_OscConfig+0x334>)
8000ba8: 400a ands r2, r1
8000baa: 601a str r2, [r3, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8000bac: 687b ldr r3, [r7, #4]
8000bae: 685b ldr r3, [r3, #4]
8000bb0: 2b00 cmp r3, #0
8000bb2: d014 beq.n 8000bde <HAL_RCC_OscConfig+0x10e>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000bb4: f7ff fd66 bl 8000684 <HAL_GetTick>
8000bb8: 0003 movs r3, r0
8000bba: 61bb str r3, [r7, #24]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000bbc: e008 b.n 8000bd0 <HAL_RCC_OscConfig+0x100>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8000bbe: f7ff fd61 bl 8000684 <HAL_GetTick>
8000bc2: 0002 movs r2, r0
8000bc4: 69bb ldr r3, [r7, #24]
8000bc6: 1ad3 subs r3, r2, r3
8000bc8: 2b64 cmp r3, #100 ; 0x64
8000bca: d901 bls.n 8000bd0 <HAL_RCC_OscConfig+0x100>
{
return HAL_TIMEOUT;
8000bcc: 2303 movs r3, #3
8000bce: e28a b.n 80010e6 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000bd0: 4b8a ldr r3, [pc, #552] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000bd2: 681a ldr r2, [r3, #0]
8000bd4: 2380 movs r3, #128 ; 0x80
8000bd6: 029b lsls r3, r3, #10
8000bd8: 4013 ands r3, r2
8000bda: d0f0 beq.n 8000bbe <HAL_RCC_OscConfig+0xee>
8000bdc: e015 b.n 8000c0a <HAL_RCC_OscConfig+0x13a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000bde: f7ff fd51 bl 8000684 <HAL_GetTick>
8000be2: 0003 movs r3, r0
8000be4: 61bb str r3, [r7, #24]
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000be6: e008 b.n 8000bfa <HAL_RCC_OscConfig+0x12a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8000be8: f7ff fd4c bl 8000684 <HAL_GetTick>
8000bec: 0002 movs r2, r0
8000bee: 69bb ldr r3, [r7, #24]
8000bf0: 1ad3 subs r3, r2, r3
8000bf2: 2b64 cmp r3, #100 ; 0x64
8000bf4: d901 bls.n 8000bfa <HAL_RCC_OscConfig+0x12a>
{
return HAL_TIMEOUT;
8000bf6: 2303 movs r3, #3
8000bf8: e275 b.n 80010e6 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000bfa: 4b80 ldr r3, [pc, #512] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000bfc: 681a ldr r2, [r3, #0]
8000bfe: 2380 movs r3, #128 ; 0x80
8000c00: 029b lsls r3, r3, #10
8000c02: 4013 ands r3, r2
8000c04: d1f0 bne.n 8000be8 <HAL_RCC_OscConfig+0x118>
8000c06: e000 b.n 8000c0a <HAL_RCC_OscConfig+0x13a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000c08: 46c0 nop ; (mov r8, r8)
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8000c0a: 687b ldr r3, [r7, #4]
8000c0c: 681b ldr r3, [r3, #0]
8000c0e: 2202 movs r2, #2
8000c10: 4013 ands r3, r2
8000c12: d100 bne.n 8000c16 <HAL_RCC_OscConfig+0x146>
8000c14: e069 b.n 8000cea <HAL_RCC_OscConfig+0x21a>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8000c16: 4b79 ldr r3, [pc, #484] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000c18: 685b ldr r3, [r3, #4]
8000c1a: 220c movs r2, #12
8000c1c: 4013 ands r3, r2
8000c1e: d00b beq.n 8000c38 <HAL_RCC_OscConfig+0x168>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
8000c20: 4b76 ldr r3, [pc, #472] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000c22: 685b ldr r3, [r3, #4]
8000c24: 220c movs r2, #12
8000c26: 4013 ands r3, r2
8000c28: 2b08 cmp r3, #8
8000c2a: d11c bne.n 8000c66 <HAL_RCC_OscConfig+0x196>
8000c2c: 4b73 ldr r3, [pc, #460] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000c2e: 685a ldr r2, [r3, #4]
8000c30: 2380 movs r3, #128 ; 0x80
8000c32: 025b lsls r3, r3, #9
8000c34: 4013 ands r3, r2
8000c36: d116 bne.n 8000c66 <HAL_RCC_OscConfig+0x196>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000c38: 4b70 ldr r3, [pc, #448] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000c3a: 681b ldr r3, [r3, #0]
8000c3c: 2202 movs r2, #2
8000c3e: 4013 ands r3, r2
8000c40: d005 beq.n 8000c4e <HAL_RCC_OscConfig+0x17e>
8000c42: 687b ldr r3, [r7, #4]
8000c44: 68db ldr r3, [r3, #12]
8000c46: 2b01 cmp r3, #1
8000c48: d001 beq.n 8000c4e <HAL_RCC_OscConfig+0x17e>
{
return HAL_ERROR;
8000c4a: 2301 movs r3, #1
8000c4c: e24b b.n 80010e6 <HAL_RCC_OscConfig+0x616>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000c4e: 4b6b ldr r3, [pc, #428] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000c50: 681b ldr r3, [r3, #0]
8000c52: 22f8 movs r2, #248 ; 0xf8
8000c54: 4393 bics r3, r2
8000c56: 0019 movs r1, r3
8000c58: 687b ldr r3, [r7, #4]
8000c5a: 691b ldr r3, [r3, #16]
8000c5c: 00da lsls r2, r3, #3
8000c5e: 4b67 ldr r3, [pc, #412] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000c60: 430a orrs r2, r1
8000c62: 601a str r2, [r3, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000c64: e041 b.n 8000cea <HAL_RCC_OscConfig+0x21a>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8000c66: 687b ldr r3, [r7, #4]
8000c68: 68db ldr r3, [r3, #12]
8000c6a: 2b00 cmp r3, #0
8000c6c: d024 beq.n 8000cb8 <HAL_RCC_OscConfig+0x1e8>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8000c6e: 4b63 ldr r3, [pc, #396] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000c70: 681a ldr r2, [r3, #0]
8000c72: 4b62 ldr r3, [pc, #392] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000c74: 2101 movs r1, #1
8000c76: 430a orrs r2, r1
8000c78: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000c7a: f7ff fd03 bl 8000684 <HAL_GetTick>
8000c7e: 0003 movs r3, r0
8000c80: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000c82: e008 b.n 8000c96 <HAL_RCC_OscConfig+0x1c6>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8000c84: f7ff fcfe bl 8000684 <HAL_GetTick>
8000c88: 0002 movs r2, r0
8000c8a: 69bb ldr r3, [r7, #24]
8000c8c: 1ad3 subs r3, r2, r3
8000c8e: 2b02 cmp r3, #2
8000c90: d901 bls.n 8000c96 <HAL_RCC_OscConfig+0x1c6>
{
return HAL_TIMEOUT;
8000c92: 2303 movs r3, #3
8000c94: e227 b.n 80010e6 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000c96: 4b59 ldr r3, [pc, #356] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000c98: 681b ldr r3, [r3, #0]
8000c9a: 2202 movs r2, #2
8000c9c: 4013 ands r3, r2
8000c9e: d0f1 beq.n 8000c84 <HAL_RCC_OscConfig+0x1b4>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000ca0: 4b56 ldr r3, [pc, #344] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000ca2: 681b ldr r3, [r3, #0]
8000ca4: 22f8 movs r2, #248 ; 0xf8
8000ca6: 4393 bics r3, r2
8000ca8: 0019 movs r1, r3
8000caa: 687b ldr r3, [r7, #4]
8000cac: 691b ldr r3, [r3, #16]
8000cae: 00da lsls r2, r3, #3
8000cb0: 4b52 ldr r3, [pc, #328] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000cb2: 430a orrs r2, r1
8000cb4: 601a str r2, [r3, #0]
8000cb6: e018 b.n 8000cea <HAL_RCC_OscConfig+0x21a>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8000cb8: 4b50 ldr r3, [pc, #320] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000cba: 681a ldr r2, [r3, #0]
8000cbc: 4b4f ldr r3, [pc, #316] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000cbe: 2101 movs r1, #1
8000cc0: 438a bics r2, r1
8000cc2: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000cc4: f7ff fcde bl 8000684 <HAL_GetTick>
8000cc8: 0003 movs r3, r0
8000cca: 61bb str r3, [r7, #24]
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000ccc: e008 b.n 8000ce0 <HAL_RCC_OscConfig+0x210>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8000cce: f7ff fcd9 bl 8000684 <HAL_GetTick>
8000cd2: 0002 movs r2, r0
8000cd4: 69bb ldr r3, [r7, #24]
8000cd6: 1ad3 subs r3, r2, r3
8000cd8: 2b02 cmp r3, #2
8000cda: d901 bls.n 8000ce0 <HAL_RCC_OscConfig+0x210>
{
return HAL_TIMEOUT;
8000cdc: 2303 movs r3, #3
8000cde: e202 b.n 80010e6 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000ce0: 4b46 ldr r3, [pc, #280] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000ce2: 681b ldr r3, [r3, #0]
8000ce4: 2202 movs r2, #2
8000ce6: 4013 ands r3, r2
8000ce8: d1f1 bne.n 8000cce <HAL_RCC_OscConfig+0x1fe>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8000cea: 687b ldr r3, [r7, #4]
8000cec: 681b ldr r3, [r3, #0]
8000cee: 2208 movs r2, #8
8000cf0: 4013 ands r3, r2
8000cf2: d036 beq.n 8000d62 <HAL_RCC_OscConfig+0x292>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8000cf4: 687b ldr r3, [r7, #4]
8000cf6: 69db ldr r3, [r3, #28]
8000cf8: 2b00 cmp r3, #0
8000cfa: d019 beq.n 8000d30 <HAL_RCC_OscConfig+0x260>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8000cfc: 4b3f ldr r3, [pc, #252] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000cfe: 6a5a ldr r2, [r3, #36] ; 0x24
8000d00: 4b3e ldr r3, [pc, #248] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000d02: 2101 movs r1, #1
8000d04: 430a orrs r2, r1
8000d06: 625a str r2, [r3, #36] ; 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
8000d08: f7ff fcbc bl 8000684 <HAL_GetTick>
8000d0c: 0003 movs r3, r0
8000d0e: 61bb str r3, [r7, #24]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000d10: e008 b.n 8000d24 <HAL_RCC_OscConfig+0x254>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8000d12: f7ff fcb7 bl 8000684 <HAL_GetTick>
8000d16: 0002 movs r2, r0
8000d18: 69bb ldr r3, [r7, #24]
8000d1a: 1ad3 subs r3, r2, r3
8000d1c: 2b02 cmp r3, #2
8000d1e: d901 bls.n 8000d24 <HAL_RCC_OscConfig+0x254>
{
return HAL_TIMEOUT;
8000d20: 2303 movs r3, #3
8000d22: e1e0 b.n 80010e6 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000d24: 4b35 ldr r3, [pc, #212] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000d26: 6a5b ldr r3, [r3, #36] ; 0x24
8000d28: 2202 movs r2, #2
8000d2a: 4013 ands r3, r2
8000d2c: d0f1 beq.n 8000d12 <HAL_RCC_OscConfig+0x242>
8000d2e: e018 b.n 8000d62 <HAL_RCC_OscConfig+0x292>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8000d30: 4b32 ldr r3, [pc, #200] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000d32: 6a5a ldr r2, [r3, #36] ; 0x24
8000d34: 4b31 ldr r3, [pc, #196] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000d36: 2101 movs r1, #1
8000d38: 438a bics r2, r1
8000d3a: 625a str r2, [r3, #36] ; 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
8000d3c: f7ff fca2 bl 8000684 <HAL_GetTick>
8000d40: 0003 movs r3, r0
8000d42: 61bb str r3, [r7, #24]
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000d44: e008 b.n 8000d58 <HAL_RCC_OscConfig+0x288>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8000d46: f7ff fc9d bl 8000684 <HAL_GetTick>
8000d4a: 0002 movs r2, r0
8000d4c: 69bb ldr r3, [r7, #24]
8000d4e: 1ad3 subs r3, r2, r3
8000d50: 2b02 cmp r3, #2
8000d52: d901 bls.n 8000d58 <HAL_RCC_OscConfig+0x288>
{
return HAL_TIMEOUT;
8000d54: 2303 movs r3, #3
8000d56: e1c6 b.n 80010e6 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000d58: 4b28 ldr r3, [pc, #160] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000d5a: 6a5b ldr r3, [r3, #36] ; 0x24
8000d5c: 2202 movs r2, #2
8000d5e: 4013 ands r3, r2
8000d60: d1f1 bne.n 8000d46 <HAL_RCC_OscConfig+0x276>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8000d62: 687b ldr r3, [r7, #4]
8000d64: 681b ldr r3, [r3, #0]
8000d66: 2204 movs r2, #4
8000d68: 4013 ands r3, r2
8000d6a: d100 bne.n 8000d6e <HAL_RCC_OscConfig+0x29e>
8000d6c: e0b4 b.n 8000ed8 <HAL_RCC_OscConfig+0x408>
{
FlagStatus pwrclkchanged = RESET;
8000d6e: 201f movs r0, #31
8000d70: 183b adds r3, r7, r0
8000d72: 2200 movs r2, #0
8000d74: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8000d76: 4b21 ldr r3, [pc, #132] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000d78: 69da ldr r2, [r3, #28]
8000d7a: 2380 movs r3, #128 ; 0x80
8000d7c: 055b lsls r3, r3, #21
8000d7e: 4013 ands r3, r2
8000d80: d110 bne.n 8000da4 <HAL_RCC_OscConfig+0x2d4>
{
__HAL_RCC_PWR_CLK_ENABLE();
8000d82: 4b1e ldr r3, [pc, #120] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000d84: 69da ldr r2, [r3, #28]
8000d86: 4b1d ldr r3, [pc, #116] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000d88: 2180 movs r1, #128 ; 0x80
8000d8a: 0549 lsls r1, r1, #21
8000d8c: 430a orrs r2, r1
8000d8e: 61da str r2, [r3, #28]
8000d90: 4b1a ldr r3, [pc, #104] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000d92: 69da ldr r2, [r3, #28]
8000d94: 2380 movs r3, #128 ; 0x80
8000d96: 055b lsls r3, r3, #21
8000d98: 4013 ands r3, r2
8000d9a: 60fb str r3, [r7, #12]
8000d9c: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
8000d9e: 183b adds r3, r7, r0
8000da0: 2201 movs r2, #1
8000da2: 701a strb r2, [r3, #0]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000da4: 4b18 ldr r3, [pc, #96] ; (8000e08 <HAL_RCC_OscConfig+0x338>)
8000da6: 681a ldr r2, [r3, #0]
8000da8: 2380 movs r3, #128 ; 0x80
8000daa: 005b lsls r3, r3, #1
8000dac: 4013 ands r3, r2
8000dae: d11a bne.n 8000de6 <HAL_RCC_OscConfig+0x316>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8000db0: 4b15 ldr r3, [pc, #84] ; (8000e08 <HAL_RCC_OscConfig+0x338>)
8000db2: 681a ldr r2, [r3, #0]
8000db4: 4b14 ldr r3, [pc, #80] ; (8000e08 <HAL_RCC_OscConfig+0x338>)
8000db6: 2180 movs r1, #128 ; 0x80
8000db8: 0049 lsls r1, r1, #1
8000dba: 430a orrs r2, r1
8000dbc: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8000dbe: f7ff fc61 bl 8000684 <HAL_GetTick>
8000dc2: 0003 movs r3, r0
8000dc4: 61bb str r3, [r7, #24]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000dc6: e008 b.n 8000dda <HAL_RCC_OscConfig+0x30a>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8000dc8: f7ff fc5c bl 8000684 <HAL_GetTick>
8000dcc: 0002 movs r2, r0
8000dce: 69bb ldr r3, [r7, #24]
8000dd0: 1ad3 subs r3, r2, r3
8000dd2: 2b64 cmp r3, #100 ; 0x64
8000dd4: d901 bls.n 8000dda <HAL_RCC_OscConfig+0x30a>
{
return HAL_TIMEOUT;
8000dd6: 2303 movs r3, #3
8000dd8: e185 b.n 80010e6 <HAL_RCC_OscConfig+0x616>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000dda: 4b0b ldr r3, [pc, #44] ; (8000e08 <HAL_RCC_OscConfig+0x338>)
8000ddc: 681a ldr r2, [r3, #0]
8000dde: 2380 movs r3, #128 ; 0x80
8000de0: 005b lsls r3, r3, #1
8000de2: 4013 ands r3, r2
8000de4: d0f0 beq.n 8000dc8 <HAL_RCC_OscConfig+0x2f8>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8000de6: 687b ldr r3, [r7, #4]
8000de8: 689b ldr r3, [r3, #8]
8000dea: 2b01 cmp r3, #1
8000dec: d10e bne.n 8000e0c <HAL_RCC_OscConfig+0x33c>
8000dee: 4b03 ldr r3, [pc, #12] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000df0: 6a1a ldr r2, [r3, #32]
8000df2: 4b02 ldr r3, [pc, #8] ; (8000dfc <HAL_RCC_OscConfig+0x32c>)
8000df4: 2101 movs r1, #1
8000df6: 430a orrs r2, r1
8000df8: 621a str r2, [r3, #32]
8000dfa: e035 b.n 8000e68 <HAL_RCC_OscConfig+0x398>
8000dfc: 40021000 .word 0x40021000
8000e00: fffeffff .word 0xfffeffff
8000e04: fffbffff .word 0xfffbffff
8000e08: 40007000 .word 0x40007000
8000e0c: 687b ldr r3, [r7, #4]
8000e0e: 689b ldr r3, [r3, #8]
8000e10: 2b00 cmp r3, #0
8000e12: d10c bne.n 8000e2e <HAL_RCC_OscConfig+0x35e>
8000e14: 4bb6 ldr r3, [pc, #728] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000e16: 6a1a ldr r2, [r3, #32]
8000e18: 4bb5 ldr r3, [pc, #724] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000e1a: 2101 movs r1, #1
8000e1c: 438a bics r2, r1
8000e1e: 621a str r2, [r3, #32]
8000e20: 4bb3 ldr r3, [pc, #716] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000e22: 6a1a ldr r2, [r3, #32]
8000e24: 4bb2 ldr r3, [pc, #712] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000e26: 2104 movs r1, #4
8000e28: 438a bics r2, r1
8000e2a: 621a str r2, [r3, #32]
8000e2c: e01c b.n 8000e68 <HAL_RCC_OscConfig+0x398>
8000e2e: 687b ldr r3, [r7, #4]
8000e30: 689b ldr r3, [r3, #8]
8000e32: 2b05 cmp r3, #5
8000e34: d10c bne.n 8000e50 <HAL_RCC_OscConfig+0x380>
8000e36: 4bae ldr r3, [pc, #696] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000e38: 6a1a ldr r2, [r3, #32]
8000e3a: 4bad ldr r3, [pc, #692] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000e3c: 2104 movs r1, #4
8000e3e: 430a orrs r2, r1
8000e40: 621a str r2, [r3, #32]
8000e42: 4bab ldr r3, [pc, #684] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000e44: 6a1a ldr r2, [r3, #32]
8000e46: 4baa ldr r3, [pc, #680] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000e48: 2101 movs r1, #1
8000e4a: 430a orrs r2, r1
8000e4c: 621a str r2, [r3, #32]
8000e4e: e00b b.n 8000e68 <HAL_RCC_OscConfig+0x398>
8000e50: 4ba7 ldr r3, [pc, #668] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000e52: 6a1a ldr r2, [r3, #32]
8000e54: 4ba6 ldr r3, [pc, #664] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000e56: 2101 movs r1, #1
8000e58: 438a bics r2, r1
8000e5a: 621a str r2, [r3, #32]
8000e5c: 4ba4 ldr r3, [pc, #656] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000e5e: 6a1a ldr r2, [r3, #32]
8000e60: 4ba3 ldr r3, [pc, #652] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000e62: 2104 movs r1, #4
8000e64: 438a bics r2, r1
8000e66: 621a str r2, [r3, #32]
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8000e68: 687b ldr r3, [r7, #4]
8000e6a: 689b ldr r3, [r3, #8]
8000e6c: 2b00 cmp r3, #0
8000e6e: d014 beq.n 8000e9a <HAL_RCC_OscConfig+0x3ca>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000e70: f7ff fc08 bl 8000684 <HAL_GetTick>
8000e74: 0003 movs r3, r0
8000e76: 61bb str r3, [r7, #24]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000e78: e009 b.n 8000e8e <HAL_RCC_OscConfig+0x3be>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8000e7a: f7ff fc03 bl 8000684 <HAL_GetTick>
8000e7e: 0002 movs r2, r0
8000e80: 69bb ldr r3, [r7, #24]
8000e82: 1ad3 subs r3, r2, r3
8000e84: 4a9b ldr r2, [pc, #620] ; (80010f4 <HAL_RCC_OscConfig+0x624>)
8000e86: 4293 cmp r3, r2
8000e88: d901 bls.n 8000e8e <HAL_RCC_OscConfig+0x3be>
{
return HAL_TIMEOUT;
8000e8a: 2303 movs r3, #3
8000e8c: e12b b.n 80010e6 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000e8e: 4b98 ldr r3, [pc, #608] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000e90: 6a1b ldr r3, [r3, #32]
8000e92: 2202 movs r2, #2
8000e94: 4013 ands r3, r2
8000e96: d0f0 beq.n 8000e7a <HAL_RCC_OscConfig+0x3aa>
8000e98: e013 b.n 8000ec2 <HAL_RCC_OscConfig+0x3f2>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000e9a: f7ff fbf3 bl 8000684 <HAL_GetTick>
8000e9e: 0003 movs r3, r0
8000ea0: 61bb str r3, [r7, #24]
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000ea2: e009 b.n 8000eb8 <HAL_RCC_OscConfig+0x3e8>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8000ea4: f7ff fbee bl 8000684 <HAL_GetTick>
8000ea8: 0002 movs r2, r0
8000eaa: 69bb ldr r3, [r7, #24]
8000eac: 1ad3 subs r3, r2, r3
8000eae: 4a91 ldr r2, [pc, #580] ; (80010f4 <HAL_RCC_OscConfig+0x624>)
8000eb0: 4293 cmp r3, r2
8000eb2: d901 bls.n 8000eb8 <HAL_RCC_OscConfig+0x3e8>
{
return HAL_TIMEOUT;
8000eb4: 2303 movs r3, #3
8000eb6: e116 b.n 80010e6 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000eb8: 4b8d ldr r3, [pc, #564] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000eba: 6a1b ldr r3, [r3, #32]
8000ebc: 2202 movs r2, #2
8000ebe: 4013 ands r3, r2
8000ec0: d1f0 bne.n 8000ea4 <HAL_RCC_OscConfig+0x3d4>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
8000ec2: 231f movs r3, #31
8000ec4: 18fb adds r3, r7, r3
8000ec6: 781b ldrb r3, [r3, #0]
8000ec8: 2b01 cmp r3, #1
8000eca: d105 bne.n 8000ed8 <HAL_RCC_OscConfig+0x408>
{
__HAL_RCC_PWR_CLK_DISABLE();
8000ecc: 4b88 ldr r3, [pc, #544] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000ece: 69da ldr r2, [r3, #28]
8000ed0: 4b87 ldr r3, [pc, #540] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000ed2: 4989 ldr r1, [pc, #548] ; (80010f8 <HAL_RCC_OscConfig+0x628>)
8000ed4: 400a ands r2, r1
8000ed6: 61da str r2, [r3, #28]
}
}
/*----------------------------- HSI14 Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
8000ed8: 687b ldr r3, [r7, #4]
8000eda: 681b ldr r3, [r3, #0]
8000edc: 2210 movs r2, #16
8000ede: 4013 ands r3, r2
8000ee0: d063 beq.n 8000faa <HAL_RCC_OscConfig+0x4da>
/* Check the parameters */
assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
/* Check the HSI14 State */
if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
8000ee2: 687b ldr r3, [r7, #4]
8000ee4: 695b ldr r3, [r3, #20]
8000ee6: 2b01 cmp r3, #1
8000ee8: d12a bne.n 8000f40 <HAL_RCC_OscConfig+0x470>
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
8000eea: 4b81 ldr r3, [pc, #516] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000eec: 6b5a ldr r2, [r3, #52] ; 0x34
8000eee: 4b80 ldr r3, [pc, #512] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000ef0: 2104 movs r1, #4
8000ef2: 430a orrs r2, r1
8000ef4: 635a str r2, [r3, #52] ; 0x34
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_ENABLE();
8000ef6: 4b7e ldr r3, [pc, #504] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000ef8: 6b5a ldr r2, [r3, #52] ; 0x34
8000efa: 4b7d ldr r3, [pc, #500] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000efc: 2101 movs r1, #1
8000efe: 430a orrs r2, r1
8000f00: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f02: f7ff fbbf bl 8000684 <HAL_GetTick>
8000f06: 0003 movs r3, r0
8000f08: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
8000f0a: e008 b.n 8000f1e <HAL_RCC_OscConfig+0x44e>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8000f0c: f7ff fbba bl 8000684 <HAL_GetTick>
8000f10: 0002 movs r2, r0
8000f12: 69bb ldr r3, [r7, #24]
8000f14: 1ad3 subs r3, r2, r3
8000f16: 2b02 cmp r3, #2
8000f18: d901 bls.n 8000f1e <HAL_RCC_OscConfig+0x44e>
{
return HAL_TIMEOUT;
8000f1a: 2303 movs r3, #3
8000f1c: e0e3 b.n 80010e6 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
8000f1e: 4b74 ldr r3, [pc, #464] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000f20: 6b5b ldr r3, [r3, #52] ; 0x34
8000f22: 2202 movs r2, #2
8000f24: 4013 ands r3, r2
8000f26: d0f1 beq.n 8000f0c <HAL_RCC_OscConfig+0x43c>
}
}
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
8000f28: 4b71 ldr r3, [pc, #452] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000f2a: 6b5b ldr r3, [r3, #52] ; 0x34
8000f2c: 22f8 movs r2, #248 ; 0xf8
8000f2e: 4393 bics r3, r2
8000f30: 0019 movs r1, r3
8000f32: 687b ldr r3, [r7, #4]
8000f34: 699b ldr r3, [r3, #24]
8000f36: 00da lsls r2, r3, #3
8000f38: 4b6d ldr r3, [pc, #436] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000f3a: 430a orrs r2, r1
8000f3c: 635a str r2, [r3, #52] ; 0x34
8000f3e: e034 b.n 8000faa <HAL_RCC_OscConfig+0x4da>
}
else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
8000f40: 687b ldr r3, [r7, #4]
8000f42: 695b ldr r3, [r3, #20]
8000f44: 3305 adds r3, #5
8000f46: d111 bne.n 8000f6c <HAL_RCC_OscConfig+0x49c>
{
/* Enable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_ENABLE();
8000f48: 4b69 ldr r3, [pc, #420] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000f4a: 6b5a ldr r2, [r3, #52] ; 0x34
8000f4c: 4b68 ldr r3, [pc, #416] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000f4e: 2104 movs r1, #4
8000f50: 438a bics r2, r1
8000f52: 635a str r2, [r3, #52] ; 0x34
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
8000f54: 4b66 ldr r3, [pc, #408] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000f56: 6b5b ldr r3, [r3, #52] ; 0x34
8000f58: 22f8 movs r2, #248 ; 0xf8
8000f5a: 4393 bics r3, r2
8000f5c: 0019 movs r1, r3
8000f5e: 687b ldr r3, [r7, #4]
8000f60: 699b ldr r3, [r3, #24]
8000f62: 00da lsls r2, r3, #3
8000f64: 4b62 ldr r3, [pc, #392] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000f66: 430a orrs r2, r1
8000f68: 635a str r2, [r3, #52] ; 0x34
8000f6a: e01e b.n 8000faa <HAL_RCC_OscConfig+0x4da>
}
else
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
8000f6c: 4b60 ldr r3, [pc, #384] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000f6e: 6b5a ldr r2, [r3, #52] ; 0x34
8000f70: 4b5f ldr r3, [pc, #380] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000f72: 2104 movs r1, #4
8000f74: 430a orrs r2, r1
8000f76: 635a str r2, [r3, #52] ; 0x34
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_DISABLE();
8000f78: 4b5d ldr r3, [pc, #372] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000f7a: 6b5a ldr r2, [r3, #52] ; 0x34
8000f7c: 4b5c ldr r3, [pc, #368] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000f7e: 2101 movs r1, #1
8000f80: 438a bics r2, r1
8000f82: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f84: f7ff fb7e bl 8000684 <HAL_GetTick>
8000f88: 0003 movs r3, r0
8000f8a: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8000f8c: e008 b.n 8000fa0 <HAL_RCC_OscConfig+0x4d0>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8000f8e: f7ff fb79 bl 8000684 <HAL_GetTick>
8000f92: 0002 movs r2, r0
8000f94: 69bb ldr r3, [r7, #24]
8000f96: 1ad3 subs r3, r2, r3
8000f98: 2b02 cmp r3, #2
8000f9a: d901 bls.n 8000fa0 <HAL_RCC_OscConfig+0x4d0>
{
return HAL_TIMEOUT;
8000f9c: 2303 movs r3, #3
8000f9e: e0a2 b.n 80010e6 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8000fa0: 4b53 ldr r3, [pc, #332] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000fa2: 6b5b ldr r3, [r3, #52] ; 0x34
8000fa4: 2202 movs r2, #2
8000fa6: 4013 ands r3, r2
8000fa8: d1f1 bne.n 8000f8e <HAL_RCC_OscConfig+0x4be>
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8000faa: 687b ldr r3, [r7, #4]
8000fac: 6a1b ldr r3, [r3, #32]
8000fae: 2b00 cmp r3, #0
8000fb0: d100 bne.n 8000fb4 <HAL_RCC_OscConfig+0x4e4>
8000fb2: e097 b.n 80010e4 <HAL_RCC_OscConfig+0x614>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8000fb4: 4b4e ldr r3, [pc, #312] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000fb6: 685b ldr r3, [r3, #4]
8000fb8: 220c movs r2, #12
8000fba: 4013 ands r3, r2
8000fbc: 2b08 cmp r3, #8
8000fbe: d100 bne.n 8000fc2 <HAL_RCC_OscConfig+0x4f2>
8000fc0: e06b b.n 800109a <HAL_RCC_OscConfig+0x5ca>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8000fc2: 687b ldr r3, [r7, #4]
8000fc4: 6a1b ldr r3, [r3, #32]
8000fc6: 2b02 cmp r3, #2
8000fc8: d14c bne.n 8001064 <HAL_RCC_OscConfig+0x594>
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8000fca: 4b49 ldr r3, [pc, #292] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000fcc: 681a ldr r2, [r3, #0]
8000fce: 4b48 ldr r3, [pc, #288] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000fd0: 494a ldr r1, [pc, #296] ; (80010fc <HAL_RCC_OscConfig+0x62c>)
8000fd2: 400a ands r2, r1
8000fd4: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000fd6: f7ff fb55 bl 8000684 <HAL_GetTick>
8000fda: 0003 movs r3, r0
8000fdc: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000fde: e008 b.n 8000ff2 <HAL_RCC_OscConfig+0x522>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8000fe0: f7ff fb50 bl 8000684 <HAL_GetTick>
8000fe4: 0002 movs r2, r0
8000fe6: 69bb ldr r3, [r7, #24]
8000fe8: 1ad3 subs r3, r2, r3
8000fea: 2b02 cmp r3, #2
8000fec: d901 bls.n 8000ff2 <HAL_RCC_OscConfig+0x522>
{
return HAL_TIMEOUT;
8000fee: 2303 movs r3, #3
8000ff0: e079 b.n 80010e6 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000ff2: 4b3f ldr r3, [pc, #252] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8000ff4: 681a ldr r2, [r3, #0]
8000ff6: 2380 movs r3, #128 ; 0x80
8000ff8: 049b lsls r3, r3, #18
8000ffa: 4013 ands r3, r2
8000ffc: d1f0 bne.n 8000fe0 <HAL_RCC_OscConfig+0x510>
}
}
/* Configure the main PLL clock source, predivider and multiplication factor. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8000ffe: 4b3c ldr r3, [pc, #240] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8001000: 6adb ldr r3, [r3, #44] ; 0x2c
8001002: 220f movs r2, #15
8001004: 4393 bics r3, r2
8001006: 0019 movs r1, r3
8001008: 687b ldr r3, [r7, #4]
800100a: 6ada ldr r2, [r3, #44] ; 0x2c
800100c: 4b38 ldr r3, [pc, #224] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
800100e: 430a orrs r2, r1
8001010: 62da str r2, [r3, #44] ; 0x2c
8001012: 4b37 ldr r3, [pc, #220] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8001014: 685b ldr r3, [r3, #4]
8001016: 4a3a ldr r2, [pc, #232] ; (8001100 <HAL_RCC_OscConfig+0x630>)
8001018: 4013 ands r3, r2
800101a: 0019 movs r1, r3
800101c: 687b ldr r3, [r7, #4]
800101e: 6a9a ldr r2, [r3, #40] ; 0x28
8001020: 687b ldr r3, [r7, #4]
8001022: 6a5b ldr r3, [r3, #36] ; 0x24
8001024: 431a orrs r2, r3
8001026: 4b32 ldr r3, [pc, #200] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8001028: 430a orrs r2, r1
800102a: 605a str r2, [r3, #4]
RCC_OscInitStruct->PLL.PREDIV,
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
800102c: 4b30 ldr r3, [pc, #192] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
800102e: 681a ldr r2, [r3, #0]
8001030: 4b2f ldr r3, [pc, #188] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8001032: 2180 movs r1, #128 ; 0x80
8001034: 0449 lsls r1, r1, #17
8001036: 430a orrs r2, r1
8001038: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800103a: f7ff fb23 bl 8000684 <HAL_GetTick>
800103e: 0003 movs r3, r0
8001040: 61bb str r3, [r7, #24]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001042: e008 b.n 8001056 <HAL_RCC_OscConfig+0x586>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001044: f7ff fb1e bl 8000684 <HAL_GetTick>
8001048: 0002 movs r2, r0
800104a: 69bb ldr r3, [r7, #24]
800104c: 1ad3 subs r3, r2, r3
800104e: 2b02 cmp r3, #2
8001050: d901 bls.n 8001056 <HAL_RCC_OscConfig+0x586>
{
return HAL_TIMEOUT;
8001052: 2303 movs r3, #3
8001054: e047 b.n 80010e6 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001056: 4b26 ldr r3, [pc, #152] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8001058: 681a ldr r2, [r3, #0]
800105a: 2380 movs r3, #128 ; 0x80
800105c: 049b lsls r3, r3, #18
800105e: 4013 ands r3, r2
8001060: d0f0 beq.n 8001044 <HAL_RCC_OscConfig+0x574>
8001062: e03f b.n 80010e4 <HAL_RCC_OscConfig+0x614>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001064: 4b22 ldr r3, [pc, #136] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
8001066: 681a ldr r2, [r3, #0]
8001068: 4b21 ldr r3, [pc, #132] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
800106a: 4924 ldr r1, [pc, #144] ; (80010fc <HAL_RCC_OscConfig+0x62c>)
800106c: 400a ands r2, r1
800106e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001070: f7ff fb08 bl 8000684 <HAL_GetTick>
8001074: 0003 movs r3, r0
8001076: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001078: e008 b.n 800108c <HAL_RCC_OscConfig+0x5bc>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
800107a: f7ff fb03 bl 8000684 <HAL_GetTick>
800107e: 0002 movs r2, r0
8001080: 69bb ldr r3, [r7, #24]
8001082: 1ad3 subs r3, r2, r3
8001084: 2b02 cmp r3, #2
8001086: d901 bls.n 800108c <HAL_RCC_OscConfig+0x5bc>
{
return HAL_TIMEOUT;
8001088: 2303 movs r3, #3
800108a: e02c b.n 80010e6 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800108c: 4b18 ldr r3, [pc, #96] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
800108e: 681a ldr r2, [r3, #0]
8001090: 2380 movs r3, #128 ; 0x80
8001092: 049b lsls r3, r3, #18
8001094: 4013 ands r3, r2
8001096: d1f0 bne.n 800107a <HAL_RCC_OscConfig+0x5aa>
8001098: e024 b.n 80010e4 <HAL_RCC_OscConfig+0x614>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
800109a: 687b ldr r3, [r7, #4]
800109c: 6a1b ldr r3, [r3, #32]
800109e: 2b01 cmp r3, #1
80010a0: d101 bne.n 80010a6 <HAL_RCC_OscConfig+0x5d6>
{
return HAL_ERROR;
80010a2: 2301 movs r3, #1
80010a4: e01f b.n 80010e6 <HAL_RCC_OscConfig+0x616>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
80010a6: 4b12 ldr r3, [pc, #72] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
80010a8: 685b ldr r3, [r3, #4]
80010aa: 617b str r3, [r7, #20]
pll_config2 = RCC->CFGR2;
80010ac: 4b10 ldr r3, [pc, #64] ; (80010f0 <HAL_RCC_OscConfig+0x620>)
80010ae: 6adb ldr r3, [r3, #44] ; 0x2c
80010b0: 613b str r3, [r7, #16]
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80010b2: 697a ldr r2, [r7, #20]
80010b4: 2380 movs r3, #128 ; 0x80
80010b6: 025b lsls r3, r3, #9
80010b8: 401a ands r2, r3
80010ba: 687b ldr r3, [r7, #4]
80010bc: 6a5b ldr r3, [r3, #36] ; 0x24
80010be: 429a cmp r2, r3
80010c0: d10e bne.n 80010e0 <HAL_RCC_OscConfig+0x610>
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
80010c2: 693b ldr r3, [r7, #16]
80010c4: 220f movs r2, #15
80010c6: 401a ands r2, r3
80010c8: 687b ldr r3, [r7, #4]
80010ca: 6adb ldr r3, [r3, #44] ; 0x2c
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80010cc: 429a cmp r2, r3
80010ce: d107 bne.n 80010e0 <HAL_RCC_OscConfig+0x610>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
80010d0: 697a ldr r2, [r7, #20]
80010d2: 23f0 movs r3, #240 ; 0xf0
80010d4: 039b lsls r3, r3, #14
80010d6: 401a ands r2, r3
80010d8: 687b ldr r3, [r7, #4]
80010da: 6a9b ldr r3, [r3, #40] ; 0x28
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
80010dc: 429a cmp r2, r3
80010de: d001 beq.n 80010e4 <HAL_RCC_OscConfig+0x614>
{
return HAL_ERROR;
80010e0: 2301 movs r3, #1
80010e2: e000 b.n 80010e6 <HAL_RCC_OscConfig+0x616>
}
}
}
}
return HAL_OK;
80010e4: 2300 movs r3, #0
}
80010e6: 0018 movs r0, r3
80010e8: 46bd mov sp, r7
80010ea: b008 add sp, #32
80010ec: bd80 pop {r7, pc}
80010ee: 46c0 nop ; (mov r8, r8)
80010f0: 40021000 .word 0x40021000
80010f4: 00001388 .word 0x00001388
80010f8: efffffff .word 0xefffffff
80010fc: feffffff .word 0xfeffffff
8001100: ffc2ffff .word 0xffc2ffff
08001104 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001104: b580 push {r7, lr}
8001106: b084 sub sp, #16
8001108: af00 add r7, sp, #0
800110a: 6078 str r0, [r7, #4]
800110c: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
800110e: 687b ldr r3, [r7, #4]
8001110: 2b00 cmp r3, #0
8001112: d101 bne.n 8001118 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8001114: 2301 movs r3, #1
8001116: e0b3 b.n 8001280 <HAL_RCC_ClockConfig+0x17c>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8001118: 4b5b ldr r3, [pc, #364] ; (8001288 <HAL_RCC_ClockConfig+0x184>)
800111a: 681b ldr r3, [r3, #0]
800111c: 2201 movs r2, #1
800111e: 4013 ands r3, r2
8001120: 683a ldr r2, [r7, #0]
8001122: 429a cmp r2, r3
8001124: d911 bls.n 800114a <HAL_RCC_ClockConfig+0x46>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001126: 4b58 ldr r3, [pc, #352] ; (8001288 <HAL_RCC_ClockConfig+0x184>)
8001128: 681b ldr r3, [r3, #0]
800112a: 2201 movs r2, #1
800112c: 4393 bics r3, r2
800112e: 0019 movs r1, r3
8001130: 4b55 ldr r3, [pc, #340] ; (8001288 <HAL_RCC_ClockConfig+0x184>)
8001132: 683a ldr r2, [r7, #0]
8001134: 430a orrs r2, r1
8001136: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001138: 4b53 ldr r3, [pc, #332] ; (8001288 <HAL_RCC_ClockConfig+0x184>)
800113a: 681b ldr r3, [r3, #0]
800113c: 2201 movs r2, #1
800113e: 4013 ands r3, r2
8001140: 683a ldr r2, [r7, #0]
8001142: 429a cmp r2, r3
8001144: d001 beq.n 800114a <HAL_RCC_ClockConfig+0x46>
{
return HAL_ERROR;
8001146: 2301 movs r3, #1
8001148: e09a b.n 8001280 <HAL_RCC_ClockConfig+0x17c>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800114a: 687b ldr r3, [r7, #4]
800114c: 681b ldr r3, [r3, #0]
800114e: 2202 movs r2, #2
8001150: 4013 ands r3, r2
8001152: d015 beq.n 8001180 <HAL_RCC_ClockConfig+0x7c>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001154: 687b ldr r3, [r7, #4]
8001156: 681b ldr r3, [r3, #0]
8001158: 2204 movs r2, #4
800115a: 4013 ands r3, r2
800115c: d006 beq.n 800116c <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
800115e: 4b4b ldr r3, [pc, #300] ; (800128c <HAL_RCC_ClockConfig+0x188>)
8001160: 685a ldr r2, [r3, #4]
8001162: 4b4a ldr r3, [pc, #296] ; (800128c <HAL_RCC_ClockConfig+0x188>)
8001164: 21e0 movs r1, #224 ; 0xe0
8001166: 00c9 lsls r1, r1, #3
8001168: 430a orrs r2, r1
800116a: 605a str r2, [r3, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
800116c: 4b47 ldr r3, [pc, #284] ; (800128c <HAL_RCC_ClockConfig+0x188>)
800116e: 685b ldr r3, [r3, #4]
8001170: 22f0 movs r2, #240 ; 0xf0
8001172: 4393 bics r3, r2
8001174: 0019 movs r1, r3
8001176: 687b ldr r3, [r7, #4]
8001178: 689a ldr r2, [r3, #8]
800117a: 4b44 ldr r3, [pc, #272] ; (800128c <HAL_RCC_ClockConfig+0x188>)
800117c: 430a orrs r2, r1
800117e: 605a str r2, [r3, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001180: 687b ldr r3, [r7, #4]
8001182: 681b ldr r3, [r3, #0]
8001184: 2201 movs r2, #1
8001186: 4013 ands r3, r2
8001188: d040 beq.n 800120c <HAL_RCC_ClockConfig+0x108>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
800118a: 687b ldr r3, [r7, #4]
800118c: 685b ldr r3, [r3, #4]
800118e: 2b01 cmp r3, #1
8001190: d107 bne.n 80011a2 <HAL_RCC_ClockConfig+0x9e>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001192: 4b3e ldr r3, [pc, #248] ; (800128c <HAL_RCC_ClockConfig+0x188>)
8001194: 681a ldr r2, [r3, #0]
8001196: 2380 movs r3, #128 ; 0x80
8001198: 029b lsls r3, r3, #10
800119a: 4013 ands r3, r2
800119c: d114 bne.n 80011c8 <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
800119e: 2301 movs r3, #1
80011a0: e06e b.n 8001280 <HAL_RCC_ClockConfig+0x17c>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
80011a2: 687b ldr r3, [r7, #4]
80011a4: 685b ldr r3, [r3, #4]
80011a6: 2b02 cmp r3, #2
80011a8: d107 bne.n 80011ba <HAL_RCC_ClockConfig+0xb6>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80011aa: 4b38 ldr r3, [pc, #224] ; (800128c <HAL_RCC_ClockConfig+0x188>)
80011ac: 681a ldr r2, [r3, #0]
80011ae: 2380 movs r3, #128 ; 0x80
80011b0: 049b lsls r3, r3, #18
80011b2: 4013 ands r3, r2
80011b4: d108 bne.n 80011c8 <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
80011b6: 2301 movs r3, #1
80011b8: e062 b.n 8001280 <HAL_RCC_ClockConfig+0x17c>
#endif /* RCC_CFGR_SWS_HSI48 */
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80011ba: 4b34 ldr r3, [pc, #208] ; (800128c <HAL_RCC_ClockConfig+0x188>)
80011bc: 681b ldr r3, [r3, #0]
80011be: 2202 movs r2, #2
80011c0: 4013 ands r3, r2
80011c2: d101 bne.n 80011c8 <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
80011c4: 2301 movs r3, #1
80011c6: e05b b.n 8001280 <HAL_RCC_ClockConfig+0x17c>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
80011c8: 4b30 ldr r3, [pc, #192] ; (800128c <HAL_RCC_ClockConfig+0x188>)
80011ca: 685b ldr r3, [r3, #4]
80011cc: 2203 movs r2, #3
80011ce: 4393 bics r3, r2
80011d0: 0019 movs r1, r3
80011d2: 687b ldr r3, [r7, #4]
80011d4: 685a ldr r2, [r3, #4]
80011d6: 4b2d ldr r3, [pc, #180] ; (800128c <HAL_RCC_ClockConfig+0x188>)
80011d8: 430a orrs r2, r1
80011da: 605a str r2, [r3, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
80011dc: f7ff fa52 bl 8000684 <HAL_GetTick>
80011e0: 0003 movs r3, r0
80011e2: 60fb str r3, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80011e4: e009 b.n 80011fa <HAL_RCC_ClockConfig+0xf6>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
80011e6: f7ff fa4d bl 8000684 <HAL_GetTick>
80011ea: 0002 movs r2, r0
80011ec: 68fb ldr r3, [r7, #12]
80011ee: 1ad3 subs r3, r2, r3
80011f0: 4a27 ldr r2, [pc, #156] ; (8001290 <HAL_RCC_ClockConfig+0x18c>)
80011f2: 4293 cmp r3, r2
80011f4: d901 bls.n 80011fa <HAL_RCC_ClockConfig+0xf6>
{
return HAL_TIMEOUT;
80011f6: 2303 movs r3, #3
80011f8: e042 b.n 8001280 <HAL_RCC_ClockConfig+0x17c>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80011fa: 4b24 ldr r3, [pc, #144] ; (800128c <HAL_RCC_ClockConfig+0x188>)
80011fc: 685b ldr r3, [r3, #4]
80011fe: 220c movs r2, #12
8001200: 401a ands r2, r3
8001202: 687b ldr r3, [r7, #4]
8001204: 685b ldr r3, [r3, #4]
8001206: 009b lsls r3, r3, #2
8001208: 429a cmp r2, r3
800120a: d1ec bne.n 80011e6 <HAL_RCC_ClockConfig+0xe2>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
800120c: 4b1e ldr r3, [pc, #120] ; (8001288 <HAL_RCC_ClockConfig+0x184>)
800120e: 681b ldr r3, [r3, #0]
8001210: 2201 movs r2, #1
8001212: 4013 ands r3, r2
8001214: 683a ldr r2, [r7, #0]
8001216: 429a cmp r2, r3
8001218: d211 bcs.n 800123e <HAL_RCC_ClockConfig+0x13a>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800121a: 4b1b ldr r3, [pc, #108] ; (8001288 <HAL_RCC_ClockConfig+0x184>)
800121c: 681b ldr r3, [r3, #0]
800121e: 2201 movs r2, #1
8001220: 4393 bics r3, r2
8001222: 0019 movs r1, r3
8001224: 4b18 ldr r3, [pc, #96] ; (8001288 <HAL_RCC_ClockConfig+0x184>)
8001226: 683a ldr r2, [r7, #0]
8001228: 430a orrs r2, r1
800122a: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
800122c: 4b16 ldr r3, [pc, #88] ; (8001288 <HAL_RCC_ClockConfig+0x184>)
800122e: 681b ldr r3, [r3, #0]
8001230: 2201 movs r2, #1
8001232: 4013 ands r3, r2
8001234: 683a ldr r2, [r7, #0]
8001236: 429a cmp r2, r3
8001238: d001 beq.n 800123e <HAL_RCC_ClockConfig+0x13a>
{
return HAL_ERROR;
800123a: 2301 movs r3, #1
800123c: e020 b.n 8001280 <HAL_RCC_ClockConfig+0x17c>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
800123e: 687b ldr r3, [r7, #4]
8001240: 681b ldr r3, [r3, #0]
8001242: 2204 movs r2, #4
8001244: 4013 ands r3, r2
8001246: d009 beq.n 800125c <HAL_RCC_ClockConfig+0x158>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
8001248: 4b10 ldr r3, [pc, #64] ; (800128c <HAL_RCC_ClockConfig+0x188>)
800124a: 685b ldr r3, [r3, #4]
800124c: 4a11 ldr r2, [pc, #68] ; (8001294 <HAL_RCC_ClockConfig+0x190>)
800124e: 4013 ands r3, r2
8001250: 0019 movs r1, r3
8001252: 687b ldr r3, [r7, #4]
8001254: 68da ldr r2, [r3, #12]
8001256: 4b0d ldr r3, [pc, #52] ; (800128c <HAL_RCC_ClockConfig+0x188>)
8001258: 430a orrs r2, r1
800125a: 605a str r2, [r3, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
800125c: f000 f820 bl 80012a0 <HAL_RCC_GetSysClockFreq>
8001260: 0001 movs r1, r0
8001262: 4b0a ldr r3, [pc, #40] ; (800128c <HAL_RCC_ClockConfig+0x188>)
8001264: 685b ldr r3, [r3, #4]
8001266: 091b lsrs r3, r3, #4
8001268: 220f movs r2, #15
800126a: 4013 ands r3, r2
800126c: 4a0a ldr r2, [pc, #40] ; (8001298 <HAL_RCC_ClockConfig+0x194>)
800126e: 5cd3 ldrb r3, [r2, r3]
8001270: 000a movs r2, r1
8001272: 40da lsrs r2, r3
8001274: 4b09 ldr r3, [pc, #36] ; (800129c <HAL_RCC_ClockConfig+0x198>)
8001276: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
8001278: 2000 movs r0, #0
800127a: f7ff f9bd bl 80005f8 <HAL_InitTick>
return HAL_OK;
800127e: 2300 movs r3, #0
}
8001280: 0018 movs r0, r3
8001282: 46bd mov sp, r7
8001284: b004 add sp, #16
8001286: bd80 pop {r7, pc}
8001288: 40022000 .word 0x40022000
800128c: 40021000 .word 0x40021000
8001290: 00001388 .word 0x00001388
8001294: fffff8ff .word 0xfffff8ff
8001298: 08001ce4 .word 0x08001ce4
800129c: 20000000 .word 0x20000000
080012a0 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
80012a0: b580 push {r7, lr}
80012a2: b086 sub sp, #24
80012a4: af00 add r7, sp, #0
static const uint8_t aPLLMULFactorTable[16U] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
static const uint8_t aPredivFactorTable[16U] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
80012a6: 2300 movs r3, #0
80012a8: 60fb str r3, [r7, #12]
80012aa: 2300 movs r3, #0
80012ac: 60bb str r3, [r7, #8]
80012ae: 2300 movs r3, #0
80012b0: 617b str r3, [r7, #20]
80012b2: 2300 movs r3, #0
80012b4: 607b str r3, [r7, #4]
uint32_t sysclockfreq = 0U;
80012b6: 2300 movs r3, #0
80012b8: 613b str r3, [r7, #16]
tmpreg = RCC->CFGR;
80012ba: 4b20 ldr r3, [pc, #128] ; (800133c <HAL_RCC_GetSysClockFreq+0x9c>)
80012bc: 685b ldr r3, [r3, #4]
80012be: 60fb str r3, [r7, #12]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
80012c0: 68fb ldr r3, [r7, #12]
80012c2: 220c movs r2, #12
80012c4: 4013 ands r3, r2
80012c6: 2b04 cmp r3, #4
80012c8: d002 beq.n 80012d0 <HAL_RCC_GetSysClockFreq+0x30>
80012ca: 2b08 cmp r3, #8
80012cc: d003 beq.n 80012d6 <HAL_RCC_GetSysClockFreq+0x36>
80012ce: e02c b.n 800132a <HAL_RCC_GetSysClockFreq+0x8a>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
80012d0: 4b1b ldr r3, [pc, #108] ; (8001340 <HAL_RCC_GetSysClockFreq+0xa0>)
80012d2: 613b str r3, [r7, #16]
break;
80012d4: e02c b.n 8001330 <HAL_RCC_GetSysClockFreq+0x90>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
80012d6: 68fb ldr r3, [r7, #12]
80012d8: 0c9b lsrs r3, r3, #18
80012da: 220f movs r2, #15
80012dc: 4013 ands r3, r2
80012de: 4a19 ldr r2, [pc, #100] ; (8001344 <HAL_RCC_GetSysClockFreq+0xa4>)
80012e0: 5cd3 ldrb r3, [r2, r3]
80012e2: 607b str r3, [r7, #4]
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
80012e4: 4b15 ldr r3, [pc, #84] ; (800133c <HAL_RCC_GetSysClockFreq+0x9c>)
80012e6: 6adb ldr r3, [r3, #44] ; 0x2c
80012e8: 220f movs r2, #15
80012ea: 4013 ands r3, r2
80012ec: 4a16 ldr r2, [pc, #88] ; (8001348 <HAL_RCC_GetSysClockFreq+0xa8>)
80012ee: 5cd3 ldrb r3, [r2, r3]
80012f0: 60bb str r3, [r7, #8]
if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
80012f2: 68fa ldr r2, [r7, #12]
80012f4: 2380 movs r3, #128 ; 0x80
80012f6: 025b lsls r3, r3, #9
80012f8: 4013 ands r3, r2
80012fa: d009 beq.n 8001310 <HAL_RCC_GetSysClockFreq+0x70>
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
80012fc: 68b9 ldr r1, [r7, #8]
80012fe: 4810 ldr r0, [pc, #64] ; (8001340 <HAL_RCC_GetSysClockFreq+0xa0>)
8001300: f7fe ff02 bl 8000108 <__udivsi3>
8001304: 0003 movs r3, r0
8001306: 001a movs r2, r3
8001308: 687b ldr r3, [r7, #4]
800130a: 4353 muls r3, r2
800130c: 617b str r3, [r7, #20]
800130e: e009 b.n 8001324 <HAL_RCC_GetSysClockFreq+0x84>
#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
#else
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
8001310: 6879 ldr r1, [r7, #4]
8001312: 000a movs r2, r1
8001314: 0152 lsls r2, r2, #5
8001316: 1a52 subs r2, r2, r1
8001318: 0193 lsls r3, r2, #6
800131a: 1a9b subs r3, r3, r2
800131c: 00db lsls r3, r3, #3
800131e: 185b adds r3, r3, r1
8001320: 021b lsls r3, r3, #8
8001322: 617b str r3, [r7, #20]
#endif
}
sysclockfreq = pllclk;
8001324: 697b ldr r3, [r7, #20]
8001326: 613b str r3, [r7, #16]
break;
8001328: e002 b.n 8001330 <HAL_RCC_GetSysClockFreq+0x90>
}
#endif /* RCC_CFGR_SWS_HSI48 */
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
800132a: 4b05 ldr r3, [pc, #20] ; (8001340 <HAL_RCC_GetSysClockFreq+0xa0>)
800132c: 613b str r3, [r7, #16]
break;
800132e: 46c0 nop ; (mov r8, r8)
}
}
return sysclockfreq;
8001330: 693b ldr r3, [r7, #16]
}
8001332: 0018 movs r0, r3
8001334: 46bd mov sp, r7
8001336: b006 add sp, #24
8001338: bd80 pop {r7, pc}
800133a: 46c0 nop ; (mov r8, r8)
800133c: 40021000 .word 0x40021000
8001340: 007a1200 .word 0x007a1200
8001344: 08001cfc .word 0x08001cfc
8001348: 08001d0c .word 0x08001d0c
0800134c <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
800134c: b580 push {r7, lr}
800134e: af00 add r7, sp, #0
return SystemCoreClock;
8001350: 4b02 ldr r3, [pc, #8] ; (800135c <HAL_RCC_GetHCLKFreq+0x10>)
8001352: 681b ldr r3, [r3, #0]
}
8001354: 0018 movs r0, r3
8001356: 46bd mov sp, r7
8001358: bd80 pop {r7, pc}
800135a: 46c0 nop ; (mov r8, r8)
800135c: 20000000 .word 0x20000000
08001360 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8001360: b580 push {r7, lr}
8001362: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_BITNUMBER]);
8001364: f7ff fff2 bl 800134c <HAL_RCC_GetHCLKFreq>
8001368: 0001 movs r1, r0
800136a: 4b06 ldr r3, [pc, #24] ; (8001384 <HAL_RCC_GetPCLK1Freq+0x24>)
800136c: 685b ldr r3, [r3, #4]
800136e: 0a1b lsrs r3, r3, #8
8001370: 2207 movs r2, #7
8001372: 4013 ands r3, r2
8001374: 4a04 ldr r2, [pc, #16] ; (8001388 <HAL_RCC_GetPCLK1Freq+0x28>)
8001376: 5cd3 ldrb r3, [r2, r3]
8001378: 40d9 lsrs r1, r3
800137a: 000b movs r3, r1
}
800137c: 0018 movs r0, r3
800137e: 46bd mov sp, r7
8001380: bd80 pop {r7, pc}
8001382: 46c0 nop ; (mov r8, r8)
8001384: 40021000 .word 0x40021000
8001388: 08001cf4 .word 0x08001cf4
0800138c <HAL_RCCEx_PeriphCLKConfig>:
* the backup registers) and RCC_BDCR register are set to their reset values.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
800138c: b580 push {r7, lr}
800138e: b086 sub sp, #24
8001390: af00 add r7, sp, #0
8001392: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8001394: 2300 movs r3, #0
8001396: 613b str r3, [r7, #16]
uint32_t temp_reg = 0U;
8001398: 2300 movs r3, #0
800139a: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*---------------------------- RTC configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
800139c: 687b ldr r3, [r7, #4]
800139e: 681a ldr r2, [r3, #0]
80013a0: 2380 movs r3, #128 ; 0x80
80013a2: 025b lsls r3, r3, #9
80013a4: 4013 ands r3, r2
80013a6: d100 bne.n 80013aa <HAL_RCCEx_PeriphCLKConfig+0x1e>
80013a8: e08e b.n 80014c8 <HAL_RCCEx_PeriphCLKConfig+0x13c>
{
/* check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
FlagStatus pwrclkchanged = RESET;
80013aa: 2017 movs r0, #23
80013ac: 183b adds r3, r7, r0
80013ae: 2200 movs r2, #0
80013b0: 701a strb r2, [r3, #0]
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
80013b2: 4b57 ldr r3, [pc, #348] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
80013b4: 69da ldr r2, [r3, #28]
80013b6: 2380 movs r3, #128 ; 0x80
80013b8: 055b lsls r3, r3, #21
80013ba: 4013 ands r3, r2
80013bc: d110 bne.n 80013e0 <HAL_RCCEx_PeriphCLKConfig+0x54>
{
__HAL_RCC_PWR_CLK_ENABLE();
80013be: 4b54 ldr r3, [pc, #336] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
80013c0: 69da ldr r2, [r3, #28]
80013c2: 4b53 ldr r3, [pc, #332] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
80013c4: 2180 movs r1, #128 ; 0x80
80013c6: 0549 lsls r1, r1, #21
80013c8: 430a orrs r2, r1
80013ca: 61da str r2, [r3, #28]
80013cc: 4b50 ldr r3, [pc, #320] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
80013ce: 69da ldr r2, [r3, #28]
80013d0: 2380 movs r3, #128 ; 0x80
80013d2: 055b lsls r3, r3, #21
80013d4: 4013 ands r3, r2
80013d6: 60bb str r3, [r7, #8]
80013d8: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
80013da: 183b adds r3, r7, r0
80013dc: 2201 movs r2, #1
80013de: 701a strb r2, [r3, #0]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80013e0: 4b4c ldr r3, [pc, #304] ; (8001514 <HAL_RCCEx_PeriphCLKConfig+0x188>)
80013e2: 681a ldr r2, [r3, #0]
80013e4: 2380 movs r3, #128 ; 0x80
80013e6: 005b lsls r3, r3, #1
80013e8: 4013 ands r3, r2
80013ea: d11a bne.n 8001422 <HAL_RCCEx_PeriphCLKConfig+0x96>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80013ec: 4b49 ldr r3, [pc, #292] ; (8001514 <HAL_RCCEx_PeriphCLKConfig+0x188>)
80013ee: 681a ldr r2, [r3, #0]
80013f0: 4b48 ldr r3, [pc, #288] ; (8001514 <HAL_RCCEx_PeriphCLKConfig+0x188>)
80013f2: 2180 movs r1, #128 ; 0x80
80013f4: 0049 lsls r1, r1, #1
80013f6: 430a orrs r2, r1
80013f8: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80013fa: f7ff f943 bl 8000684 <HAL_GetTick>
80013fe: 0003 movs r3, r0
8001400: 613b str r3, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001402: e008 b.n 8001416 <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001404: f7ff f93e bl 8000684 <HAL_GetTick>
8001408: 0002 movs r2, r0
800140a: 693b ldr r3, [r7, #16]
800140c: 1ad3 subs r3, r2, r3
800140e: 2b64 cmp r3, #100 ; 0x64
8001410: d901 bls.n 8001416 <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
return HAL_TIMEOUT;
8001412: 2303 movs r3, #3
8001414: e077 b.n 8001506 <HAL_RCCEx_PeriphCLKConfig+0x17a>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001416: 4b3f ldr r3, [pc, #252] ; (8001514 <HAL_RCCEx_PeriphCLKConfig+0x188>)
8001418: 681a ldr r2, [r3, #0]
800141a: 2380 movs r3, #128 ; 0x80
800141c: 005b lsls r3, r3, #1
800141e: 4013 ands r3, r2
8001420: d0f0 beq.n 8001404 <HAL_RCCEx_PeriphCLKConfig+0x78>
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
8001422: 4b3b ldr r3, [pc, #236] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
8001424: 6a1a ldr r2, [r3, #32]
8001426: 23c0 movs r3, #192 ; 0xc0
8001428: 009b lsls r3, r3, #2
800142a: 4013 ands r3, r2
800142c: 60fb str r3, [r7, #12]
if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
800142e: 68fb ldr r3, [r7, #12]
8001430: 2b00 cmp r3, #0
8001432: d034 beq.n 800149e <HAL_RCCEx_PeriphCLKConfig+0x112>
8001434: 687b ldr r3, [r7, #4]
8001436: 685a ldr r2, [r3, #4]
8001438: 23c0 movs r3, #192 ; 0xc0
800143a: 009b lsls r3, r3, #2
800143c: 4013 ands r3, r2
800143e: 68fa ldr r2, [r7, #12]
8001440: 429a cmp r2, r3
8001442: d02c beq.n 800149e <HAL_RCCEx_PeriphCLKConfig+0x112>
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8001444: 4b32 ldr r3, [pc, #200] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
8001446: 6a1b ldr r3, [r3, #32]
8001448: 4a33 ldr r2, [pc, #204] ; (8001518 <HAL_RCCEx_PeriphCLKConfig+0x18c>)
800144a: 4013 ands r3, r2
800144c: 60fb str r3, [r7, #12]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
800144e: 4b30 ldr r3, [pc, #192] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
8001450: 6a1a ldr r2, [r3, #32]
8001452: 4b2f ldr r3, [pc, #188] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
8001454: 2180 movs r1, #128 ; 0x80
8001456: 0249 lsls r1, r1, #9
8001458: 430a orrs r2, r1
800145a: 621a str r2, [r3, #32]
__HAL_RCC_BACKUPRESET_RELEASE();
800145c: 4b2c ldr r3, [pc, #176] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
800145e: 6a1a ldr r2, [r3, #32]
8001460: 4b2b ldr r3, [pc, #172] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
8001462: 492e ldr r1, [pc, #184] ; (800151c <HAL_RCCEx_PeriphCLKConfig+0x190>)
8001464: 400a ands r2, r1
8001466: 621a str r2, [r3, #32]
/* Restore the Content of BDCR register */
RCC->BDCR = temp_reg;
8001468: 4b29 ldr r3, [pc, #164] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
800146a: 68fa ldr r2, [r7, #12]
800146c: 621a str r2, [r3, #32]
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
800146e: 68fb ldr r3, [r7, #12]
8001470: 2201 movs r2, #1
8001472: 4013 ands r3, r2
8001474: d013 beq.n 800149e <HAL_RCCEx_PeriphCLKConfig+0x112>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001476: f7ff f905 bl 8000684 <HAL_GetTick>
800147a: 0003 movs r3, r0
800147c: 613b str r3, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800147e: e009 b.n 8001494 <HAL_RCCEx_PeriphCLKConfig+0x108>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8001480: f7ff f900 bl 8000684 <HAL_GetTick>
8001484: 0002 movs r2, r0
8001486: 693b ldr r3, [r7, #16]
8001488: 1ad3 subs r3, r2, r3
800148a: 4a25 ldr r2, [pc, #148] ; (8001520 <HAL_RCCEx_PeriphCLKConfig+0x194>)
800148c: 4293 cmp r3, r2
800148e: d901 bls.n 8001494 <HAL_RCCEx_PeriphCLKConfig+0x108>
{
return HAL_TIMEOUT;
8001490: 2303 movs r3, #3
8001492: e038 b.n 8001506 <HAL_RCCEx_PeriphCLKConfig+0x17a>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001494: 4b1e ldr r3, [pc, #120] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
8001496: 6a1b ldr r3, [r3, #32]
8001498: 2202 movs r2, #2
800149a: 4013 ands r3, r2
800149c: d0f0 beq.n 8001480 <HAL_RCCEx_PeriphCLKConfig+0xf4>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
800149e: 4b1c ldr r3, [pc, #112] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
80014a0: 6a1b ldr r3, [r3, #32]
80014a2: 4a1d ldr r2, [pc, #116] ; (8001518 <HAL_RCCEx_PeriphCLKConfig+0x18c>)
80014a4: 4013 ands r3, r2
80014a6: 0019 movs r1, r3
80014a8: 687b ldr r3, [r7, #4]
80014aa: 685a ldr r2, [r3, #4]
80014ac: 4b18 ldr r3, [pc, #96] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
80014ae: 430a orrs r2, r1
80014b0: 621a str r2, [r3, #32]
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
80014b2: 2317 movs r3, #23
80014b4: 18fb adds r3, r7, r3
80014b6: 781b ldrb r3, [r3, #0]
80014b8: 2b01 cmp r3, #1
80014ba: d105 bne.n 80014c8 <HAL_RCCEx_PeriphCLKConfig+0x13c>
{
__HAL_RCC_PWR_CLK_DISABLE();
80014bc: 4b14 ldr r3, [pc, #80] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
80014be: 69da ldr r2, [r3, #28]
80014c0: 4b13 ldr r3, [pc, #76] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
80014c2: 4918 ldr r1, [pc, #96] ; (8001524 <HAL_RCCEx_PeriphCLKConfig+0x198>)
80014c4: 400a ands r2, r1
80014c6: 61da str r2, [r3, #28]
}
}
/*------------------------------- USART1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
80014c8: 687b ldr r3, [r7, #4]
80014ca: 681b ldr r3, [r3, #0]
80014cc: 2201 movs r2, #1
80014ce: 4013 ands r3, r2
80014d0: d009 beq.n 80014e6 <HAL_RCCEx_PeriphCLKConfig+0x15a>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
80014d2: 4b0f ldr r3, [pc, #60] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
80014d4: 6b1b ldr r3, [r3, #48] ; 0x30
80014d6: 2203 movs r2, #3
80014d8: 4393 bics r3, r2
80014da: 0019 movs r1, r3
80014dc: 687b ldr r3, [r7, #4]
80014de: 689a ldr r2, [r3, #8]
80014e0: 4b0b ldr r3, [pc, #44] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
80014e2: 430a orrs r2, r1
80014e4: 631a str r2, [r3, #48] ; 0x30
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
}
#endif /* STM32F091xC || STM32F098xx */
/*------------------------------ I2C1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
80014e6: 687b ldr r3, [r7, #4]
80014e8: 681b ldr r3, [r3, #0]
80014ea: 2220 movs r2, #32
80014ec: 4013 ands r3, r2
80014ee: d009 beq.n 8001504 <HAL_RCCEx_PeriphCLKConfig+0x178>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
80014f0: 4b07 ldr r3, [pc, #28] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
80014f2: 6b1b ldr r3, [r3, #48] ; 0x30
80014f4: 2210 movs r2, #16
80014f6: 4393 bics r3, r2
80014f8: 0019 movs r1, r3
80014fa: 687b ldr r3, [r7, #4]
80014fc: 68da ldr r2, [r3, #12]
80014fe: 4b04 ldr r3, [pc, #16] ; (8001510 <HAL_RCCEx_PeriphCLKConfig+0x184>)
8001500: 430a orrs r2, r1
8001502: 631a str r2, [r3, #48] ; 0x30
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
return HAL_OK;
8001504: 2300 movs r3, #0
}
8001506: 0018 movs r0, r3
8001508: 46bd mov sp, r7
800150a: b006 add sp, #24
800150c: bd80 pop {r7, pc}
800150e: 46c0 nop ; (mov r8, r8)
8001510: 40021000 .word 0x40021000
8001514: 40007000 .word 0x40007000
8001518: fffffcff .word 0xfffffcff
800151c: fffeffff .word 0xfffeffff
8001520: 00001388 .word 0x00001388
8001524: efffffff .word 0xefffffff
08001528 <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8001528: b580 push {r7, lr}
800152a: b082 sub sp, #8
800152c: af00 add r7, sp, #0
800152e: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8001530: 687b ldr r3, [r7, #4]
8001532: 2b00 cmp r3, #0
8001534: d101 bne.n 800153a <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8001536: 2301 movs r3, #1
8001538: e044 b.n 80015c4 <HAL_UART_Init+0x9c>
{
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
}
if (huart->gState == HAL_UART_STATE_RESET)
800153a: 687b ldr r3, [r7, #4]
800153c: 6fdb ldr r3, [r3, #124] ; 0x7c
800153e: 2b00 cmp r3, #0
8001540: d107 bne.n 8001552 <HAL_UART_Init+0x2a>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8001542: 687b ldr r3, [r7, #4]
8001544: 2278 movs r2, #120 ; 0x78
8001546: 2100 movs r1, #0
8001548: 5499 strb r1, [r3, r2]
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
800154a: 687b ldr r3, [r7, #4]
800154c: 0018 movs r0, r3
800154e: f7fe ffb1 bl 80004b4 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8001552: 687b ldr r3, [r7, #4]
8001554: 2224 movs r2, #36 ; 0x24
8001556: 67da str r2, [r3, #124] ; 0x7c
__HAL_UART_DISABLE(huart);
8001558: 687b ldr r3, [r7, #4]
800155a: 681b ldr r3, [r3, #0]
800155c: 681a ldr r2, [r3, #0]
800155e: 687b ldr r3, [r7, #4]
8001560: 681b ldr r3, [r3, #0]
8001562: 2101 movs r1, #1
8001564: 438a bics r2, r1
8001566: 601a str r2, [r3, #0]
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
8001568: 687b ldr r3, [r7, #4]
800156a: 0018 movs r0, r3
800156c: f000 f830 bl 80015d0 <UART_SetConfig>
8001570: 0003 movs r3, r0
8001572: 2b01 cmp r3, #1
8001574: d101 bne.n 800157a <HAL_UART_Init+0x52>
{
return HAL_ERROR;
8001576: 2301 movs r3, #1
8001578: e024 b.n 80015c4 <HAL_UART_Init+0x9c>
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
800157a: 687b ldr r3, [r7, #4]
800157c: 6a5b ldr r3, [r3, #36] ; 0x24
800157e: 2b00 cmp r3, #0
8001580: d003 beq.n 800158a <HAL_UART_Init+0x62>
{
UART_AdvFeatureConfig(huart);
8001582: 687b ldr r3, [r7, #4]
8001584: 0018 movs r0, r3
8001586: f000 f94b bl 8001820 <UART_AdvFeatureConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register,
- SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register.*/
#if defined (USART_CR2_LINEN)
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
800158a: 687b ldr r3, [r7, #4]
800158c: 681b ldr r3, [r3, #0]
800158e: 685a ldr r2, [r3, #4]
8001590: 687b ldr r3, [r7, #4]
8001592: 681b ldr r3, [r3, #0]
8001594: 490d ldr r1, [pc, #52] ; (80015cc <HAL_UART_Init+0xa4>)
8001596: 400a ands r2, r1
8001598: 605a str r2, [r3, #4]
#else
CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
#endif /* USART_CR2_LINEN */
#if defined (USART_CR3_SCEN)
#if defined (USART_CR3_IREN)
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
800159a: 687b ldr r3, [r7, #4]
800159c: 681b ldr r3, [r3, #0]
800159e: 689a ldr r2, [r3, #8]
80015a0: 687b ldr r3, [r7, #4]
80015a2: 681b ldr r3, [r3, #0]
80015a4: 212a movs r1, #42 ; 0x2a
80015a6: 438a bics r2, r1
80015a8: 609a str r2, [r3, #8]
#else
CLEAR_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
#endif /* USART_CR3_IREN*/
#endif /* USART_CR3_SCEN */
__HAL_UART_ENABLE(huart);
80015aa: 687b ldr r3, [r7, #4]
80015ac: 681b ldr r3, [r3, #0]
80015ae: 681a ldr r2, [r3, #0]
80015b0: 687b ldr r3, [r7, #4]
80015b2: 681b ldr r3, [r3, #0]
80015b4: 2101 movs r1, #1
80015b6: 430a orrs r2, r1
80015b8: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
80015ba: 687b ldr r3, [r7, #4]
80015bc: 0018 movs r0, r3
80015be: f000 f9e3 bl 8001988 <UART_CheckIdleState>
80015c2: 0003 movs r3, r0
}
80015c4: 0018 movs r0, r3
80015c6: 46bd mov sp, r7
80015c8: b002 add sp, #8
80015ca: bd80 pop {r7, pc}
80015cc: ffffb7ff .word 0xffffb7ff
080015d0 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
80015d0: b580 push {r7, lr}
80015d2: b088 sub sp, #32
80015d4: af00 add r7, sp, #0
80015d6: 6078 str r0, [r7, #4]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
80015d8: 231e movs r3, #30
80015da: 18fb adds r3, r7, r3
80015dc: 2200 movs r2, #0
80015de: 701a strb r2, [r3, #0]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
80015e0: 687b ldr r3, [r7, #4]
80015e2: 689a ldr r2, [r3, #8]
80015e4: 687b ldr r3, [r7, #4]
80015e6: 691b ldr r3, [r3, #16]
80015e8: 431a orrs r2, r3
80015ea: 687b ldr r3, [r7, #4]
80015ec: 695b ldr r3, [r3, #20]
80015ee: 431a orrs r2, r3
80015f0: 687b ldr r3, [r7, #4]
80015f2: 69db ldr r3, [r3, #28]
80015f4: 4313 orrs r3, r2
80015f6: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
80015f8: 687b ldr r3, [r7, #4]
80015fa: 681b ldr r3, [r3, #0]
80015fc: 681b ldr r3, [r3, #0]
80015fe: 4a83 ldr r2, [pc, #524] ; (800180c <UART_SetConfig+0x23c>)
8001600: 4013 ands r3, r2
8001602: 0019 movs r1, r3
8001604: 687b ldr r3, [r7, #4]
8001606: 681b ldr r3, [r3, #0]
8001608: 697a ldr r2, [r7, #20]
800160a: 430a orrs r2, r1
800160c: 601a str r2, [r3, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
800160e: 687b ldr r3, [r7, #4]
8001610: 681b ldr r3, [r3, #0]
8001612: 685b ldr r3, [r3, #4]
8001614: 4a7e ldr r2, [pc, #504] ; (8001810 <UART_SetConfig+0x240>)
8001616: 4013 ands r3, r2
8001618: 0019 movs r1, r3
800161a: 687b ldr r3, [r7, #4]
800161c: 68da ldr r2, [r3, #12]
800161e: 687b ldr r3, [r7, #4]
8001620: 681b ldr r3, [r3, #0]
8001622: 430a orrs r2, r1
8001624: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
8001626: 687b ldr r3, [r7, #4]
8001628: 699b ldr r3, [r3, #24]
800162a: 617b str r3, [r7, #20]
tmpreg |= huart->Init.OneBitSampling;
800162c: 687b ldr r3, [r7, #4]
800162e: 6a1b ldr r3, [r3, #32]
8001630: 697a ldr r2, [r7, #20]
8001632: 4313 orrs r3, r2
8001634: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8001636: 687b ldr r3, [r7, #4]
8001638: 681b ldr r3, [r3, #0]
800163a: 689b ldr r3, [r3, #8]
800163c: 4a75 ldr r2, [pc, #468] ; (8001814 <UART_SetConfig+0x244>)
800163e: 4013 ands r3, r2
8001640: 0019 movs r1, r3
8001642: 687b ldr r3, [r7, #4]
8001644: 681b ldr r3, [r3, #0]
8001646: 697a ldr r2, [r7, #20]
8001648: 430a orrs r2, r1
800164a: 609a str r2, [r3, #8]
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
800164c: 4b72 ldr r3, [pc, #456] ; (8001818 <UART_SetConfig+0x248>)
800164e: 6b1b ldr r3, [r3, #48] ; 0x30
8001650: 2203 movs r2, #3
8001652: 4013 ands r3, r2
8001654: 2b03 cmp r3, #3
8001656: d00d beq.n 8001674 <UART_SetConfig+0xa4>
8001658: d81b bhi.n 8001692 <UART_SetConfig+0xc2>
800165a: 2b02 cmp r3, #2
800165c: d014 beq.n 8001688 <UART_SetConfig+0xb8>
800165e: d818 bhi.n 8001692 <UART_SetConfig+0xc2>
8001660: 2b00 cmp r3, #0
8001662: d002 beq.n 800166a <UART_SetConfig+0x9a>
8001664: 2b01 cmp r3, #1
8001666: d00a beq.n 800167e <UART_SetConfig+0xae>
8001668: e013 b.n 8001692 <UART_SetConfig+0xc2>
800166a: 231f movs r3, #31
800166c: 18fb adds r3, r7, r3
800166e: 2200 movs r2, #0
8001670: 701a strb r2, [r3, #0]
8001672: e012 b.n 800169a <UART_SetConfig+0xca>
8001674: 231f movs r3, #31
8001676: 18fb adds r3, r7, r3
8001678: 2202 movs r2, #2
800167a: 701a strb r2, [r3, #0]
800167c: e00d b.n 800169a <UART_SetConfig+0xca>
800167e: 231f movs r3, #31
8001680: 18fb adds r3, r7, r3
8001682: 2204 movs r2, #4
8001684: 701a strb r2, [r3, #0]
8001686: e008 b.n 800169a <UART_SetConfig+0xca>
8001688: 231f movs r3, #31
800168a: 18fb adds r3, r7, r3
800168c: 2208 movs r2, #8
800168e: 701a strb r2, [r3, #0]
8001690: e003 b.n 800169a <UART_SetConfig+0xca>
8001692: 231f movs r3, #31
8001694: 18fb adds r3, r7, r3
8001696: 2210 movs r2, #16
8001698: 701a strb r2, [r3, #0]
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
800169a: 687b ldr r3, [r7, #4]
800169c: 69da ldr r2, [r3, #28]
800169e: 2380 movs r3, #128 ; 0x80
80016a0: 021b lsls r3, r3, #8
80016a2: 429a cmp r2, r3
80016a4: d15c bne.n 8001760 <UART_SetConfig+0x190>
{
switch (clocksource)
80016a6: 231f movs r3, #31
80016a8: 18fb adds r3, r7, r3
80016aa: 781b ldrb r3, [r3, #0]
80016ac: 2b08 cmp r3, #8
80016ae: d015 beq.n 80016dc <UART_SetConfig+0x10c>
80016b0: dc18 bgt.n 80016e4 <UART_SetConfig+0x114>
80016b2: 2b04 cmp r3, #4
80016b4: d00d beq.n 80016d2 <UART_SetConfig+0x102>
80016b6: dc15 bgt.n 80016e4 <UART_SetConfig+0x114>
80016b8: 2b00 cmp r3, #0
80016ba: d002 beq.n 80016c2 <UART_SetConfig+0xf2>
80016bc: 2b02 cmp r3, #2
80016be: d005 beq.n 80016cc <UART_SetConfig+0xfc>
80016c0: e010 b.n 80016e4 <UART_SetConfig+0x114>
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
80016c2: f7ff fe4d bl 8001360 <HAL_RCC_GetPCLK1Freq>
80016c6: 0003 movs r3, r0
80016c8: 61bb str r3, [r7, #24]
break;
80016ca: e012 b.n 80016f2 <UART_SetConfig+0x122>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
80016cc: 4b53 ldr r3, [pc, #332] ; (800181c <UART_SetConfig+0x24c>)
80016ce: 61bb str r3, [r7, #24]
break;
80016d0: e00f b.n 80016f2 <UART_SetConfig+0x122>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80016d2: f7ff fde5 bl 80012a0 <HAL_RCC_GetSysClockFreq>
80016d6: 0003 movs r3, r0
80016d8: 61bb str r3, [r7, #24]
break;
80016da: e00a b.n 80016f2 <UART_SetConfig+0x122>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
80016dc: 2380 movs r3, #128 ; 0x80
80016de: 021b lsls r3, r3, #8
80016e0: 61bb str r3, [r7, #24]
break;
80016e2: e006 b.n 80016f2 <UART_SetConfig+0x122>
default:
pclk = 0U;
80016e4: 2300 movs r3, #0
80016e6: 61bb str r3, [r7, #24]
ret = HAL_ERROR;
80016e8: 231e movs r3, #30
80016ea: 18fb adds r3, r7, r3
80016ec: 2201 movs r2, #1
80016ee: 701a strb r2, [r3, #0]
break;
80016f0: 46c0 nop ; (mov r8, r8)
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
80016f2: 69bb ldr r3, [r7, #24]
80016f4: 2b00 cmp r3, #0
80016f6: d100 bne.n 80016fa <UART_SetConfig+0x12a>
80016f8: e07a b.n 80017f0 <UART_SetConfig+0x220>
{
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
80016fa: 69bb ldr r3, [r7, #24]
80016fc: 005a lsls r2, r3, #1
80016fe: 687b ldr r3, [r7, #4]
8001700: 685b ldr r3, [r3, #4]
8001702: 085b lsrs r3, r3, #1
8001704: 18d2 adds r2, r2, r3
8001706: 687b ldr r3, [r7, #4]
8001708: 685b ldr r3, [r3, #4]
800170a: 0019 movs r1, r3
800170c: 0010 movs r0, r2
800170e: f7fe fcfb bl 8000108 <__udivsi3>
8001712: 0003 movs r3, r0
8001714: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8001716: 693b ldr r3, [r7, #16]
8001718: 2b0f cmp r3, #15
800171a: d91c bls.n 8001756 <UART_SetConfig+0x186>
800171c: 693a ldr r2, [r7, #16]
800171e: 2380 movs r3, #128 ; 0x80
8001720: 025b lsls r3, r3, #9
8001722: 429a cmp r2, r3
8001724: d217 bcs.n 8001756 <UART_SetConfig+0x186>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
8001726: 693b ldr r3, [r7, #16]
8001728: b29a uxth r2, r3
800172a: 200e movs r0, #14
800172c: 183b adds r3, r7, r0
800172e: 210f movs r1, #15
8001730: 438a bics r2, r1
8001732: 801a strh r2, [r3, #0]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8001734: 693b ldr r3, [r7, #16]
8001736: 085b lsrs r3, r3, #1
8001738: b29b uxth r3, r3
800173a: 2207 movs r2, #7
800173c: 4013 ands r3, r2
800173e: b299 uxth r1, r3
8001740: 183b adds r3, r7, r0
8001742: 183a adds r2, r7, r0
8001744: 8812 ldrh r2, [r2, #0]
8001746: 430a orrs r2, r1
8001748: 801a strh r2, [r3, #0]
huart->Instance->BRR = brrtemp;
800174a: 687b ldr r3, [r7, #4]
800174c: 681b ldr r3, [r3, #0]
800174e: 183a adds r2, r7, r0
8001750: 8812 ldrh r2, [r2, #0]
8001752: 60da str r2, [r3, #12]
8001754: e04c b.n 80017f0 <UART_SetConfig+0x220>
}
else
{
ret = HAL_ERROR;
8001756: 231e movs r3, #30
8001758: 18fb adds r3, r7, r3
800175a: 2201 movs r2, #1
800175c: 701a strb r2, [r3, #0]
800175e: e047 b.n 80017f0 <UART_SetConfig+0x220>
}
}
}
else
{
switch (clocksource)
8001760: 231f movs r3, #31
8001762: 18fb adds r3, r7, r3
8001764: 781b ldrb r3, [r3, #0]
8001766: 2b08 cmp r3, #8
8001768: d015 beq.n 8001796 <UART_SetConfig+0x1c6>
800176a: dc18 bgt.n 800179e <UART_SetConfig+0x1ce>
800176c: 2b04 cmp r3, #4
800176e: d00d beq.n 800178c <UART_SetConfig+0x1bc>
8001770: dc15 bgt.n 800179e <UART_SetConfig+0x1ce>
8001772: 2b00 cmp r3, #0
8001774: d002 beq.n 800177c <UART_SetConfig+0x1ac>
8001776: 2b02 cmp r3, #2
8001778: d005 beq.n 8001786 <UART_SetConfig+0x1b6>
800177a: e010 b.n 800179e <UART_SetConfig+0x1ce>
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
800177c: f7ff fdf0 bl 8001360 <HAL_RCC_GetPCLK1Freq>
8001780: 0003 movs r3, r0
8001782: 61bb str r3, [r7, #24]
break;
8001784: e012 b.n 80017ac <UART_SetConfig+0x1dc>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8001786: 4b25 ldr r3, [pc, #148] ; (800181c <UART_SetConfig+0x24c>)
8001788: 61bb str r3, [r7, #24]
break;
800178a: e00f b.n 80017ac <UART_SetConfig+0x1dc>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
800178c: f7ff fd88 bl 80012a0 <HAL_RCC_GetSysClockFreq>
8001790: 0003 movs r3, r0
8001792: 61bb str r3, [r7, #24]
break;
8001794: e00a b.n 80017ac <UART_SetConfig+0x1dc>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8001796: 2380 movs r3, #128 ; 0x80
8001798: 021b lsls r3, r3, #8
800179a: 61bb str r3, [r7, #24]
break;
800179c: e006 b.n 80017ac <UART_SetConfig+0x1dc>
default:
pclk = 0U;
800179e: 2300 movs r3, #0
80017a0: 61bb str r3, [r7, #24]
ret = HAL_ERROR;
80017a2: 231e movs r3, #30
80017a4: 18fb adds r3, r7, r3
80017a6: 2201 movs r2, #1
80017a8: 701a strb r2, [r3, #0]
break;
80017aa: 46c0 nop ; (mov r8, r8)
}
if (pclk != 0U)
80017ac: 69bb ldr r3, [r7, #24]
80017ae: 2b00 cmp r3, #0
80017b0: d01e beq.n 80017f0 <UART_SetConfig+0x220>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
80017b2: 687b ldr r3, [r7, #4]
80017b4: 685b ldr r3, [r3, #4]
80017b6: 085a lsrs r2, r3, #1
80017b8: 69bb ldr r3, [r7, #24]
80017ba: 18d2 adds r2, r2, r3
80017bc: 687b ldr r3, [r7, #4]
80017be: 685b ldr r3, [r3, #4]
80017c0: 0019 movs r1, r3
80017c2: 0010 movs r0, r2
80017c4: f7fe fca0 bl 8000108 <__udivsi3>
80017c8: 0003 movs r3, r0
80017ca: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
80017cc: 693b ldr r3, [r7, #16]
80017ce: 2b0f cmp r3, #15
80017d0: d90a bls.n 80017e8 <UART_SetConfig+0x218>
80017d2: 693a ldr r2, [r7, #16]
80017d4: 2380 movs r3, #128 ; 0x80
80017d6: 025b lsls r3, r3, #9
80017d8: 429a cmp r2, r3
80017da: d205 bcs.n 80017e8 <UART_SetConfig+0x218>
{
huart->Instance->BRR = (uint16_t)usartdiv;
80017dc: 693b ldr r3, [r7, #16]
80017de: b29a uxth r2, r3
80017e0: 687b ldr r3, [r7, #4]
80017e2: 681b ldr r3, [r3, #0]
80017e4: 60da str r2, [r3, #12]
80017e6: e003 b.n 80017f0 <UART_SetConfig+0x220>
}
else
{
ret = HAL_ERROR;
80017e8: 231e movs r3, #30
80017ea: 18fb adds r3, r7, r3
80017ec: 2201 movs r2, #1
80017ee: 701a strb r2, [r3, #0]
}
}
/* Clear ISR function pointers */
huart->RxISR = NULL;
80017f0: 687b ldr r3, [r7, #4]
80017f2: 2200 movs r2, #0
80017f4: 669a str r2, [r3, #104] ; 0x68
huart->TxISR = NULL;
80017f6: 687b ldr r3, [r7, #4]
80017f8: 2200 movs r2, #0
80017fa: 66da str r2, [r3, #108] ; 0x6c
return ret;
80017fc: 231e movs r3, #30
80017fe: 18fb adds r3, r7, r3
8001800: 781b ldrb r3, [r3, #0]
}
8001802: 0018 movs r0, r3
8001804: 46bd mov sp, r7
8001806: b008 add sp, #32
8001808: bd80 pop {r7, pc}
800180a: 46c0 nop ; (mov r8, r8)
800180c: ffff69f3 .word 0xffff69f3
8001810: ffffcfff .word 0xffffcfff
8001814: fffff4ff .word 0xfffff4ff
8001818: 40021000 .word 0x40021000
800181c: 007a1200 .word 0x007a1200
08001820 <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
8001820: b580 push {r7, lr}
8001822: b082 sub sp, #8
8001824: af00 add r7, sp, #0
8001826: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
8001828: 687b ldr r3, [r7, #4]
800182a: 6a5b ldr r3, [r3, #36] ; 0x24
800182c: 2201 movs r2, #1
800182e: 4013 ands r3, r2
8001830: d00b beq.n 800184a <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
8001832: 687b ldr r3, [r7, #4]
8001834: 681b ldr r3, [r3, #0]
8001836: 685b ldr r3, [r3, #4]
8001838: 4a4a ldr r2, [pc, #296] ; (8001964 <UART_AdvFeatureConfig+0x144>)
800183a: 4013 ands r3, r2
800183c: 0019 movs r1, r3
800183e: 687b ldr r3, [r7, #4]
8001840: 6a9a ldr r2, [r3, #40] ; 0x28
8001842: 687b ldr r3, [r7, #4]
8001844: 681b ldr r3, [r3, #0]
8001846: 430a orrs r2, r1
8001848: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
800184a: 687b ldr r3, [r7, #4]
800184c: 6a5b ldr r3, [r3, #36] ; 0x24
800184e: 2202 movs r2, #2
8001850: 4013 ands r3, r2
8001852: d00b beq.n 800186c <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
8001854: 687b ldr r3, [r7, #4]
8001856: 681b ldr r3, [r3, #0]
8001858: 685b ldr r3, [r3, #4]
800185a: 4a43 ldr r2, [pc, #268] ; (8001968 <UART_AdvFeatureConfig+0x148>)
800185c: 4013 ands r3, r2
800185e: 0019 movs r1, r3
8001860: 687b ldr r3, [r7, #4]
8001862: 6ada ldr r2, [r3, #44] ; 0x2c
8001864: 687b ldr r3, [r7, #4]
8001866: 681b ldr r3, [r3, #0]
8001868: 430a orrs r2, r1
800186a: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
800186c: 687b ldr r3, [r7, #4]
800186e: 6a5b ldr r3, [r3, #36] ; 0x24
8001870: 2204 movs r2, #4
8001872: 4013 ands r3, r2
8001874: d00b beq.n 800188e <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
8001876: 687b ldr r3, [r7, #4]
8001878: 681b ldr r3, [r3, #0]
800187a: 685b ldr r3, [r3, #4]
800187c: 4a3b ldr r2, [pc, #236] ; (800196c <UART_AdvFeatureConfig+0x14c>)
800187e: 4013 ands r3, r2
8001880: 0019 movs r1, r3
8001882: 687b ldr r3, [r7, #4]
8001884: 6b1a ldr r2, [r3, #48] ; 0x30
8001886: 687b ldr r3, [r7, #4]
8001888: 681b ldr r3, [r3, #0]
800188a: 430a orrs r2, r1
800188c: 605a str r2, [r3, #4]
}
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
800188e: 687b ldr r3, [r7, #4]
8001890: 6a5b ldr r3, [r3, #36] ; 0x24
8001892: 2208 movs r2, #8
8001894: 4013 ands r3, r2
8001896: d00b beq.n 80018b0 <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
8001898: 687b ldr r3, [r7, #4]
800189a: 681b ldr r3, [r3, #0]
800189c: 685b ldr r3, [r3, #4]
800189e: 4a34 ldr r2, [pc, #208] ; (8001970 <UART_AdvFeatureConfig+0x150>)
80018a0: 4013 ands r3, r2
80018a2: 0019 movs r1, r3
80018a4: 687b ldr r3, [r7, #4]
80018a6: 6b5a ldr r2, [r3, #52] ; 0x34
80018a8: 687b ldr r3, [r7, #4]
80018aa: 681b ldr r3, [r3, #0]
80018ac: 430a orrs r2, r1
80018ae: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
80018b0: 687b ldr r3, [r7, #4]
80018b2: 6a5b ldr r3, [r3, #36] ; 0x24
80018b4: 2210 movs r2, #16
80018b6: 4013 ands r3, r2
80018b8: d00b beq.n 80018d2 <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
80018ba: 687b ldr r3, [r7, #4]
80018bc: 681b ldr r3, [r3, #0]
80018be: 689b ldr r3, [r3, #8]
80018c0: 4a2c ldr r2, [pc, #176] ; (8001974 <UART_AdvFeatureConfig+0x154>)
80018c2: 4013 ands r3, r2
80018c4: 0019 movs r1, r3
80018c6: 687b ldr r3, [r7, #4]
80018c8: 6b9a ldr r2, [r3, #56] ; 0x38
80018ca: 687b ldr r3, [r7, #4]
80018cc: 681b ldr r3, [r3, #0]
80018ce: 430a orrs r2, r1
80018d0: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
80018d2: 687b ldr r3, [r7, #4]
80018d4: 6a5b ldr r3, [r3, #36] ; 0x24
80018d6: 2220 movs r2, #32
80018d8: 4013 ands r3, r2
80018da: d00b beq.n 80018f4 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
80018dc: 687b ldr r3, [r7, #4]
80018de: 681b ldr r3, [r3, #0]
80018e0: 689b ldr r3, [r3, #8]
80018e2: 4a25 ldr r2, [pc, #148] ; (8001978 <UART_AdvFeatureConfig+0x158>)
80018e4: 4013 ands r3, r2
80018e6: 0019 movs r1, r3
80018e8: 687b ldr r3, [r7, #4]
80018ea: 6bda ldr r2, [r3, #60] ; 0x3c
80018ec: 687b ldr r3, [r7, #4]
80018ee: 681b ldr r3, [r3, #0]
80018f0: 430a orrs r2, r1
80018f2: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
80018f4: 687b ldr r3, [r7, #4]
80018f6: 6a5b ldr r3, [r3, #36] ; 0x24
80018f8: 2240 movs r2, #64 ; 0x40
80018fa: 4013 ands r3, r2
80018fc: d01d beq.n 800193a <UART_AdvFeatureConfig+0x11a>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
80018fe: 687b ldr r3, [r7, #4]
8001900: 681b ldr r3, [r3, #0]
8001902: 685b ldr r3, [r3, #4]
8001904: 4a1d ldr r2, [pc, #116] ; (800197c <UART_AdvFeatureConfig+0x15c>)
8001906: 4013 ands r3, r2
8001908: 0019 movs r1, r3
800190a: 687b ldr r3, [r7, #4]
800190c: 6c1a ldr r2, [r3, #64] ; 0x40
800190e: 687b ldr r3, [r7, #4]
8001910: 681b ldr r3, [r3, #0]
8001912: 430a orrs r2, r1
8001914: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
8001916: 687b ldr r3, [r7, #4]
8001918: 6c1a ldr r2, [r3, #64] ; 0x40
800191a: 2380 movs r3, #128 ; 0x80
800191c: 035b lsls r3, r3, #13
800191e: 429a cmp r2, r3
8001920: d10b bne.n 800193a <UART_AdvFeatureConfig+0x11a>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
8001922: 687b ldr r3, [r7, #4]
8001924: 681b ldr r3, [r3, #0]
8001926: 685b ldr r3, [r3, #4]
8001928: 4a15 ldr r2, [pc, #84] ; (8001980 <UART_AdvFeatureConfig+0x160>)
800192a: 4013 ands r3, r2
800192c: 0019 movs r1, r3
800192e: 687b ldr r3, [r7, #4]
8001930: 6c5a ldr r2, [r3, #68] ; 0x44
8001932: 687b ldr r3, [r7, #4]
8001934: 681b ldr r3, [r3, #0]
8001936: 430a orrs r2, r1
8001938: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
800193a: 687b ldr r3, [r7, #4]
800193c: 6a5b ldr r3, [r3, #36] ; 0x24
800193e: 2280 movs r2, #128 ; 0x80
8001940: 4013 ands r3, r2
8001942: d00b beq.n 800195c <UART_AdvFeatureConfig+0x13c>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
8001944: 687b ldr r3, [r7, #4]
8001946: 681b ldr r3, [r3, #0]
8001948: 685b ldr r3, [r3, #4]
800194a: 4a0e ldr r2, [pc, #56] ; (8001984 <UART_AdvFeatureConfig+0x164>)
800194c: 4013 ands r3, r2
800194e: 0019 movs r1, r3
8001950: 687b ldr r3, [r7, #4]
8001952: 6c9a ldr r2, [r3, #72] ; 0x48
8001954: 687b ldr r3, [r7, #4]
8001956: 681b ldr r3, [r3, #0]
8001958: 430a orrs r2, r1
800195a: 605a str r2, [r3, #4]
}
}
800195c: 46c0 nop ; (mov r8, r8)
800195e: 46bd mov sp, r7
8001960: b002 add sp, #8
8001962: bd80 pop {r7, pc}
8001964: fffdffff .word 0xfffdffff
8001968: fffeffff .word 0xfffeffff
800196c: fffbffff .word 0xfffbffff
8001970: ffff7fff .word 0xffff7fff
8001974: ffffefff .word 0xffffefff
8001978: ffffdfff .word 0xffffdfff
800197c: ffefffff .word 0xffefffff
8001980: ff9fffff .word 0xff9fffff
8001984: fff7ffff .word 0xfff7ffff
08001988 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
8001988: b580 push {r7, lr}
800198a: b092 sub sp, #72 ; 0x48
800198c: af02 add r7, sp, #8
800198e: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8001990: 687b ldr r3, [r7, #4]
8001992: 2284 movs r2, #132 ; 0x84
8001994: 2100 movs r1, #0
8001996: 5099 str r1, [r3, r2]
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8001998: f7fe fe74 bl 8000684 <HAL_GetTick>
800199c: 0003 movs r3, r0
800199e: 63fb str r3, [r7, #60] ; 0x3c
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
80019a0: 687b ldr r3, [r7, #4]
80019a2: 681b ldr r3, [r3, #0]
80019a4: 681b ldr r3, [r3, #0]
80019a6: 2208 movs r2, #8
80019a8: 4013 ands r3, r2
80019aa: 2b08 cmp r3, #8
80019ac: d12c bne.n 8001a08 <UART_CheckIdleState+0x80>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
80019ae: 6bfb ldr r3, [r7, #60] ; 0x3c
80019b0: 2280 movs r2, #128 ; 0x80
80019b2: 0391 lsls r1, r2, #14
80019b4: 6878 ldr r0, [r7, #4]
80019b6: 4a46 ldr r2, [pc, #280] ; (8001ad0 <UART_CheckIdleState+0x148>)
80019b8: 9200 str r2, [sp, #0]
80019ba: 2200 movs r2, #0
80019bc: f000 f88c bl 8001ad8 <UART_WaitOnFlagUntilTimeout>
80019c0: 1e03 subs r3, r0, #0
80019c2: d021 beq.n 8001a08 <UART_CheckIdleState+0x80>
*/
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80019c4: f3ef 8310 mrs r3, PRIMASK
80019c8: 627b str r3, [r7, #36] ; 0x24
return(result);
80019ca: 6a7b ldr r3, [r7, #36] ; 0x24
{
/* Disable TXE interrupt for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
80019cc: 63bb str r3, [r7, #56] ; 0x38
80019ce: 2301 movs r3, #1
80019d0: 62bb str r3, [r7, #40] ; 0x28
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80019d2: 6abb ldr r3, [r7, #40] ; 0x28
80019d4: f383 8810 msr PRIMASK, r3
}
80019d8: 46c0 nop ; (mov r8, r8)
80019da: 687b ldr r3, [r7, #4]
80019dc: 681b ldr r3, [r3, #0]
80019de: 681a ldr r2, [r3, #0]
80019e0: 687b ldr r3, [r7, #4]
80019e2: 681b ldr r3, [r3, #0]
80019e4: 2180 movs r1, #128 ; 0x80
80019e6: 438a bics r2, r1
80019e8: 601a str r2, [r3, #0]
80019ea: 6bbb ldr r3, [r7, #56] ; 0x38
80019ec: 62fb str r3, [r7, #44] ; 0x2c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80019ee: 6afb ldr r3, [r7, #44] ; 0x2c
80019f0: f383 8810 msr PRIMASK, r3
}
80019f4: 46c0 nop ; (mov r8, r8)
huart->gState = HAL_UART_STATE_READY;
80019f6: 687b ldr r3, [r7, #4]
80019f8: 2220 movs r2, #32
80019fa: 67da str r2, [r3, #124] ; 0x7c
__HAL_UNLOCK(huart);
80019fc: 687b ldr r3, [r7, #4]
80019fe: 2278 movs r2, #120 ; 0x78
8001a00: 2100 movs r1, #0
8001a02: 5499 strb r1, [r3, r2]
/* Timeout occurred */
return HAL_TIMEOUT;
8001a04: 2303 movs r3, #3
8001a06: e05f b.n 8001ac8 <UART_CheckIdleState+0x140>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
8001a08: 687b ldr r3, [r7, #4]
8001a0a: 681b ldr r3, [r3, #0]
8001a0c: 681b ldr r3, [r3, #0]
8001a0e: 2204 movs r2, #4
8001a10: 4013 ands r3, r2
8001a12: 2b04 cmp r3, #4
8001a14: d146 bne.n 8001aa4 <UART_CheckIdleState+0x11c>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8001a16: 6bfb ldr r3, [r7, #60] ; 0x3c
8001a18: 2280 movs r2, #128 ; 0x80
8001a1a: 03d1 lsls r1, r2, #15
8001a1c: 6878 ldr r0, [r7, #4]
8001a1e: 4a2c ldr r2, [pc, #176] ; (8001ad0 <UART_CheckIdleState+0x148>)
8001a20: 9200 str r2, [sp, #0]
8001a22: 2200 movs r2, #0
8001a24: f000 f858 bl 8001ad8 <UART_WaitOnFlagUntilTimeout>
8001a28: 1e03 subs r3, r0, #0
8001a2a: d03b beq.n 8001aa4 <UART_CheckIdleState+0x11c>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8001a2c: f3ef 8310 mrs r3, PRIMASK
8001a30: 60fb str r3, [r7, #12]
return(result);
8001a32: 68fb ldr r3, [r7, #12]
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8001a34: 637b str r3, [r7, #52] ; 0x34
8001a36: 2301 movs r3, #1
8001a38: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8001a3a: 693b ldr r3, [r7, #16]
8001a3c: f383 8810 msr PRIMASK, r3
}
8001a40: 46c0 nop ; (mov r8, r8)
8001a42: 687b ldr r3, [r7, #4]
8001a44: 681b ldr r3, [r3, #0]
8001a46: 681a ldr r2, [r3, #0]
8001a48: 687b ldr r3, [r7, #4]
8001a4a: 681b ldr r3, [r3, #0]
8001a4c: 4921 ldr r1, [pc, #132] ; (8001ad4 <UART_CheckIdleState+0x14c>)
8001a4e: 400a ands r2, r1
8001a50: 601a str r2, [r3, #0]
8001a52: 6b7b ldr r3, [r7, #52] ; 0x34
8001a54: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8001a56: 697b ldr r3, [r7, #20]
8001a58: f383 8810 msr PRIMASK, r3
}
8001a5c: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8001a5e: f3ef 8310 mrs r3, PRIMASK
8001a62: 61bb str r3, [r7, #24]
return(result);
8001a64: 69bb ldr r3, [r7, #24]
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8001a66: 633b str r3, [r7, #48] ; 0x30
8001a68: 2301 movs r3, #1
8001a6a: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8001a6c: 69fb ldr r3, [r7, #28]
8001a6e: f383 8810 msr PRIMASK, r3
}
8001a72: 46c0 nop ; (mov r8, r8)
8001a74: 687b ldr r3, [r7, #4]
8001a76: 681b ldr r3, [r3, #0]
8001a78: 689a ldr r2, [r3, #8]
8001a7a: 687b ldr r3, [r7, #4]
8001a7c: 681b ldr r3, [r3, #0]
8001a7e: 2101 movs r1, #1
8001a80: 438a bics r2, r1
8001a82: 609a str r2, [r3, #8]
8001a84: 6b3b ldr r3, [r7, #48] ; 0x30
8001a86: 623b str r3, [r7, #32]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8001a88: 6a3b ldr r3, [r7, #32]
8001a8a: f383 8810 msr PRIMASK, r3
}
8001a8e: 46c0 nop ; (mov r8, r8)
huart->RxState = HAL_UART_STATE_READY;
8001a90: 687b ldr r3, [r7, #4]
8001a92: 2280 movs r2, #128 ; 0x80
8001a94: 2120 movs r1, #32
8001a96: 5099 str r1, [r3, r2]
__HAL_UNLOCK(huart);
8001a98: 687b ldr r3, [r7, #4]
8001a9a: 2278 movs r2, #120 ; 0x78
8001a9c: 2100 movs r1, #0
8001a9e: 5499 strb r1, [r3, r2]
/* Timeout occurred */
return HAL_TIMEOUT;
8001aa0: 2303 movs r3, #3
8001aa2: e011 b.n 8001ac8 <UART_CheckIdleState+0x140>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
8001aa4: 687b ldr r3, [r7, #4]
8001aa6: 2220 movs r2, #32
8001aa8: 67da str r2, [r3, #124] ; 0x7c
huart->RxState = HAL_UART_STATE_READY;
8001aaa: 687b ldr r3, [r7, #4]
8001aac: 2280 movs r2, #128 ; 0x80
8001aae: 2120 movs r1, #32
8001ab0: 5099 str r1, [r3, r2]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8001ab2: 687b ldr r3, [r7, #4]
8001ab4: 2200 movs r2, #0
8001ab6: 661a str r2, [r3, #96] ; 0x60
huart->RxEventType = HAL_UART_RXEVENT_TC;
8001ab8: 687b ldr r3, [r7, #4]
8001aba: 2200 movs r2, #0
8001abc: 665a str r2, [r3, #100] ; 0x64
__HAL_UNLOCK(huart);
8001abe: 687b ldr r3, [r7, #4]
8001ac0: 2278 movs r2, #120 ; 0x78
8001ac2: 2100 movs r1, #0
8001ac4: 5499 strb r1, [r3, r2]
return HAL_OK;
8001ac6: 2300 movs r3, #0
}
8001ac8: 0018 movs r0, r3
8001aca: 46bd mov sp, r7
8001acc: b010 add sp, #64 ; 0x40
8001ace: bd80 pop {r7, pc}
8001ad0: 01ffffff .word 0x01ffffff
8001ad4: fffffedf .word 0xfffffedf
08001ad8 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8001ad8: b580 push {r7, lr}
8001ada: b084 sub sp, #16
8001adc: af00 add r7, sp, #0
8001ade: 60f8 str r0, [r7, #12]
8001ae0: 60b9 str r1, [r7, #8]
8001ae2: 603b str r3, [r7, #0]
8001ae4: 1dfb adds r3, r7, #7
8001ae6: 701a strb r2, [r3, #0]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8001ae8: e04b b.n 8001b82 <UART_WaitOnFlagUntilTimeout+0xaa>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8001aea: 69bb ldr r3, [r7, #24]
8001aec: 3301 adds r3, #1
8001aee: d048 beq.n 8001b82 <UART_WaitOnFlagUntilTimeout+0xaa>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8001af0: f7fe fdc8 bl 8000684 <HAL_GetTick>
8001af4: 0002 movs r2, r0
8001af6: 683b ldr r3, [r7, #0]
8001af8: 1ad3 subs r3, r2, r3
8001afa: 69ba ldr r2, [r7, #24]
8001afc: 429a cmp r2, r3
8001afe: d302 bcc.n 8001b06 <UART_WaitOnFlagUntilTimeout+0x2e>
8001b00: 69bb ldr r3, [r7, #24]
8001b02: 2b00 cmp r3, #0
8001b04: d101 bne.n 8001b0a <UART_WaitOnFlagUntilTimeout+0x32>
{
return HAL_TIMEOUT;
8001b06: 2303 movs r3, #3
8001b08: e04b b.n 8001ba2 <UART_WaitOnFlagUntilTimeout+0xca>
}
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
8001b0a: 68fb ldr r3, [r7, #12]
8001b0c: 681b ldr r3, [r3, #0]
8001b0e: 681b ldr r3, [r3, #0]
8001b10: 2204 movs r2, #4
8001b12: 4013 ands r3, r2
8001b14: d035 beq.n 8001b82 <UART_WaitOnFlagUntilTimeout+0xaa>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
8001b16: 68fb ldr r3, [r7, #12]
8001b18: 681b ldr r3, [r3, #0]
8001b1a: 69db ldr r3, [r3, #28]
8001b1c: 2208 movs r2, #8
8001b1e: 4013 ands r3, r2
8001b20: 2b08 cmp r3, #8
8001b22: d111 bne.n 8001b48 <UART_WaitOnFlagUntilTimeout+0x70>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8001b24: 68fb ldr r3, [r7, #12]
8001b26: 681b ldr r3, [r3, #0]
8001b28: 2208 movs r2, #8
8001b2a: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8001b2c: 68fb ldr r3, [r7, #12]
8001b2e: 0018 movs r0, r3
8001b30: f000 f83c bl 8001bac <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
8001b34: 68fb ldr r3, [r7, #12]
8001b36: 2284 movs r2, #132 ; 0x84
8001b38: 2108 movs r1, #8
8001b3a: 5099 str r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(huart);
8001b3c: 68fb ldr r3, [r7, #12]
8001b3e: 2278 movs r2, #120 ; 0x78
8001b40: 2100 movs r1, #0
8001b42: 5499 strb r1, [r3, r2]
return HAL_ERROR;
8001b44: 2301 movs r3, #1
8001b46: e02c b.n 8001ba2 <UART_WaitOnFlagUntilTimeout+0xca>
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
8001b48: 68fb ldr r3, [r7, #12]
8001b4a: 681b ldr r3, [r3, #0]
8001b4c: 69da ldr r2, [r3, #28]
8001b4e: 2380 movs r3, #128 ; 0x80
8001b50: 011b lsls r3, r3, #4
8001b52: 401a ands r2, r3
8001b54: 2380 movs r3, #128 ; 0x80
8001b56: 011b lsls r3, r3, #4
8001b58: 429a cmp r2, r3
8001b5a: d112 bne.n 8001b82 <UART_WaitOnFlagUntilTimeout+0xaa>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8001b5c: 68fb ldr r3, [r7, #12]
8001b5e: 681b ldr r3, [r3, #0]
8001b60: 2280 movs r2, #128 ; 0x80
8001b62: 0112 lsls r2, r2, #4
8001b64: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8001b66: 68fb ldr r3, [r7, #12]
8001b68: 0018 movs r0, r3
8001b6a: f000 f81f bl 8001bac <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
8001b6e: 68fb ldr r3, [r7, #12]
8001b70: 2284 movs r2, #132 ; 0x84
8001b72: 2120 movs r1, #32
8001b74: 5099 str r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(huart);
8001b76: 68fb ldr r3, [r7, #12]
8001b78: 2278 movs r2, #120 ; 0x78
8001b7a: 2100 movs r1, #0
8001b7c: 5499 strb r1, [r3, r2]
return HAL_TIMEOUT;
8001b7e: 2303 movs r3, #3
8001b80: e00f b.n 8001ba2 <UART_WaitOnFlagUntilTimeout+0xca>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8001b82: 68fb ldr r3, [r7, #12]
8001b84: 681b ldr r3, [r3, #0]
8001b86: 69db ldr r3, [r3, #28]
8001b88: 68ba ldr r2, [r7, #8]
8001b8a: 4013 ands r3, r2
8001b8c: 68ba ldr r2, [r7, #8]
8001b8e: 1ad3 subs r3, r2, r3
8001b90: 425a negs r2, r3
8001b92: 4153 adcs r3, r2
8001b94: b2db uxtb r3, r3
8001b96: 001a movs r2, r3
8001b98: 1dfb adds r3, r7, #7
8001b9a: 781b ldrb r3, [r3, #0]
8001b9c: 429a cmp r2, r3
8001b9e: d0a4 beq.n 8001aea <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8001ba0: 2300 movs r3, #0
}
8001ba2: 0018 movs r0, r3
8001ba4: 46bd mov sp, r7
8001ba6: b004 add sp, #16
8001ba8: bd80 pop {r7, pc}
...
08001bac <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8001bac: b580 push {r7, lr}
8001bae: b08e sub sp, #56 ; 0x38
8001bb0: af00 add r7, sp, #0
8001bb2: 6078 str r0, [r7, #4]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8001bb4: f3ef 8310 mrs r3, PRIMASK
8001bb8: 617b str r3, [r7, #20]
return(result);
8001bba: 697b ldr r3, [r7, #20]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8001bbc: 637b str r3, [r7, #52] ; 0x34
8001bbe: 2301 movs r3, #1
8001bc0: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8001bc2: 69bb ldr r3, [r7, #24]
8001bc4: f383 8810 msr PRIMASK, r3
}
8001bc8: 46c0 nop ; (mov r8, r8)
8001bca: 687b ldr r3, [r7, #4]
8001bcc: 681b ldr r3, [r3, #0]
8001bce: 681a ldr r2, [r3, #0]
8001bd0: 687b ldr r3, [r7, #4]
8001bd2: 681b ldr r3, [r3, #0]
8001bd4: 4926 ldr r1, [pc, #152] ; (8001c70 <UART_EndRxTransfer+0xc4>)
8001bd6: 400a ands r2, r1
8001bd8: 601a str r2, [r3, #0]
8001bda: 6b7b ldr r3, [r7, #52] ; 0x34
8001bdc: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8001bde: 69fb ldr r3, [r7, #28]
8001be0: f383 8810 msr PRIMASK, r3
}
8001be4: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8001be6: f3ef 8310 mrs r3, PRIMASK
8001bea: 623b str r3, [r7, #32]
return(result);
8001bec: 6a3b ldr r3, [r7, #32]
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8001bee: 633b str r3, [r7, #48] ; 0x30
8001bf0: 2301 movs r3, #1
8001bf2: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8001bf4: 6a7b ldr r3, [r7, #36] ; 0x24
8001bf6: f383 8810 msr PRIMASK, r3
}
8001bfa: 46c0 nop ; (mov r8, r8)
8001bfc: 687b ldr r3, [r7, #4]
8001bfe: 681b ldr r3, [r3, #0]
8001c00: 689a ldr r2, [r3, #8]
8001c02: 687b ldr r3, [r7, #4]
8001c04: 681b ldr r3, [r3, #0]
8001c06: 2101 movs r1, #1
8001c08: 438a bics r2, r1
8001c0a: 609a str r2, [r3, #8]
8001c0c: 6b3b ldr r3, [r7, #48] ; 0x30
8001c0e: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8001c10: 6abb ldr r3, [r7, #40] ; 0x28
8001c12: f383 8810 msr PRIMASK, r3
}
8001c16: 46c0 nop ; (mov r8, r8)
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8001c18: 687b ldr r3, [r7, #4]
8001c1a: 6e1b ldr r3, [r3, #96] ; 0x60
8001c1c: 2b01 cmp r3, #1
8001c1e: d118 bne.n 8001c52 <UART_EndRxTransfer+0xa6>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8001c20: f3ef 8310 mrs r3, PRIMASK
8001c24: 60bb str r3, [r7, #8]
return(result);
8001c26: 68bb ldr r3, [r7, #8]
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8001c28: 62fb str r3, [r7, #44] ; 0x2c
8001c2a: 2301 movs r3, #1
8001c2c: 60fb str r3, [r7, #12]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8001c2e: 68fb ldr r3, [r7, #12]
8001c30: f383 8810 msr PRIMASK, r3
}
8001c34: 46c0 nop ; (mov r8, r8)
8001c36: 687b ldr r3, [r7, #4]
8001c38: 681b ldr r3, [r3, #0]
8001c3a: 681a ldr r2, [r3, #0]
8001c3c: 687b ldr r3, [r7, #4]
8001c3e: 681b ldr r3, [r3, #0]
8001c40: 2110 movs r1, #16
8001c42: 438a bics r2, r1
8001c44: 601a str r2, [r3, #0]
8001c46: 6afb ldr r3, [r7, #44] ; 0x2c
8001c48: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8001c4a: 693b ldr r3, [r7, #16]
8001c4c: f383 8810 msr PRIMASK, r3
}
8001c50: 46c0 nop ; (mov r8, r8)
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8001c52: 687b ldr r3, [r7, #4]
8001c54: 2280 movs r2, #128 ; 0x80
8001c56: 2120 movs r1, #32
8001c58: 5099 str r1, [r3, r2]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8001c5a: 687b ldr r3, [r7, #4]
8001c5c: 2200 movs r2, #0
8001c5e: 661a str r2, [r3, #96] ; 0x60
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
8001c60: 687b ldr r3, [r7, #4]
8001c62: 2200 movs r2, #0
8001c64: 669a str r2, [r3, #104] ; 0x68
}
8001c66: 46c0 nop ; (mov r8, r8)
8001c68: 46bd mov sp, r7
8001c6a: b00e add sp, #56 ; 0x38
8001c6c: bd80 pop {r7, pc}
8001c6e: 46c0 nop ; (mov r8, r8)
8001c70: fffffedf .word 0xfffffedf
08001c74 <memset>:
8001c74: 0003 movs r3, r0
8001c76: 1882 adds r2, r0, r2
8001c78: 4293 cmp r3, r2
8001c7a: d100 bne.n 8001c7e <memset+0xa>
8001c7c: 4770 bx lr
8001c7e: 7019 strb r1, [r3, #0]
8001c80: 3301 adds r3, #1
8001c82: e7f9 b.n 8001c78 <memset+0x4>
08001c84 <__libc_init_array>:
8001c84: b570 push {r4, r5, r6, lr}
8001c86: 2600 movs r6, #0
8001c88: 4c0c ldr r4, [pc, #48] ; (8001cbc <__libc_init_array+0x38>)
8001c8a: 4d0d ldr r5, [pc, #52] ; (8001cc0 <__libc_init_array+0x3c>)
8001c8c: 1b64 subs r4, r4, r5
8001c8e: 10a4 asrs r4, r4, #2
8001c90: 42a6 cmp r6, r4
8001c92: d109 bne.n 8001ca8 <__libc_init_array+0x24>
8001c94: 2600 movs r6, #0
8001c96: f000 f819 bl 8001ccc <_init>
8001c9a: 4c0a ldr r4, [pc, #40] ; (8001cc4 <__libc_init_array+0x40>)
8001c9c: 4d0a ldr r5, [pc, #40] ; (8001cc8 <__libc_init_array+0x44>)
8001c9e: 1b64 subs r4, r4, r5
8001ca0: 10a4 asrs r4, r4, #2
8001ca2: 42a6 cmp r6, r4
8001ca4: d105 bne.n 8001cb2 <__libc_init_array+0x2e>
8001ca6: bd70 pop {r4, r5, r6, pc}
8001ca8: 00b3 lsls r3, r6, #2
8001caa: 58eb ldr r3, [r5, r3]
8001cac: 4798 blx r3
8001cae: 3601 adds r6, #1
8001cb0: e7ee b.n 8001c90 <__libc_init_array+0xc>
8001cb2: 00b3 lsls r3, r6, #2
8001cb4: 58eb ldr r3, [r5, r3]
8001cb6: 4798 blx r3
8001cb8: 3601 adds r6, #1
8001cba: e7f2 b.n 8001ca2 <__libc_init_array+0x1e>
8001cbc: 08001d1c .word 0x08001d1c
8001cc0: 08001d1c .word 0x08001d1c
8001cc4: 08001d20 .word 0x08001d20
8001cc8: 08001d1c .word 0x08001d1c
08001ccc <_init>:
8001ccc: b5f8 push {r3, r4, r5, r6, r7, lr}
8001cce: 46c0 nop ; (mov r8, r8)
8001cd0: bcf8 pop {r3, r4, r5, r6, r7}
8001cd2: bc08 pop {r3}
8001cd4: 469e mov lr, r3
8001cd6: 4770 bx lr
08001cd8 <_fini>:
8001cd8: b5f8 push {r3, r4, r5, r6, r7, lr}
8001cda: 46c0 nop ; (mov r8, r8)
8001cdc: bcf8 pop {r3, r4, r5, r6, r7}
8001cde: bc08 pop {r3}
8001ce0: 469e mov lr, r3
8001ce2: 4770 bx lr
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