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140 lines
4.0 KiB
140 lines
4.0 KiB
/**
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**************************************************************************************************
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* @file i2c.c
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* @author Kerem Yollu & Edwin Koch
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* @date 18.07.2022
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* @version 1.0
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**************************************************************************************************
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* @brief I2C communitation based on the Standart I2C Protocol V7 Defined by NXP/Philips :
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* following third Party Protocols based on I2C Bus are not going to be implemented : C-BUS SMBUS PMBUS IPMI DDC ATCA
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* This will also not have a I3C support for the forseable futrue. This code is generated for the stm32f4xK6 series of mcu for stm
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*
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* **Detailed Description :**
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*
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* I2C communitation based on the Standart I2C Protocol V7 Defined by NXP/Philips :
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* following third Party Protocols based on I2C Bus are not going to be implemented : C-BUS SMBUS PMBUS IPMI DDC ATCA
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* This will also not have a I3C support for the forseable futrue.
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*
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* @todo
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* - 18.07.2021 : Implement the i2c.c
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**************************************************************************************************
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*/
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#include "i2c.h"
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#define I2C_BASE ((I2C_TypeDef*)i2cBase_Addr_List[i2cHardware->channelNo])
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void i2cInit(i2c_t *i2cHardware)
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{
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i2cReset(i2cHardware);
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// Enables the i2c bus
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RCC->APB1ENR |= (1 << i2cBus_En_bitPos[i2cHardware->channelNo]);
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// Make sure that the periferal is disabled.
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I2C_BASE->CR1 &= ~I2C_CR1_PE;
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//Configure analog filter. Anlalog filter is on
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//I2C_BASE->CR1 |= I2C_CR1_ANFOFF;
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//Configure NoStrech Streching mode is disabled (slave only)
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//I2C_BASE->CR1 |= I2C_CR1_NOSTRETCH;
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//Configure the clock
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I2C_BASE->TIMINGR = i2cHardware->timing;
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//Automatic end mode (master mode) Enablede as default
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I2C_BASE->CR2 &= ~I2C_CR2_AUTOEND;
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//I2C_BASE->CR2 |= I2C_CR2_AUTOEND;
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if(i2cHardware->mode == i2cModeMaster)
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{
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if(i2cHardware->addressSize == i2cAddressSizeTenBits)
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{
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I2C_BASE->CR2 |= I2C_CR2_ADD10; // 10 Bit addressing
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I2C_BASE->CR2 &= ~I2C_CR2_HEAD10R; // 7 Bit header read turned on DEFAULT
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}
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else
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{
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I2C_BASE->CR2 &= ~I2C_CR2_ADD10; // 7 Bit addressing DEFAULT
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I2C_BASE->CR2 |= I2C_CR2_HEAD10R; // 7 Bit header read turned off DEFAULT
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}
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}
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//activating the Perriferal.
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I2C_BASE->CR1 |= I2C_CR1_PE;
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i2cCR1= I2C_BASE->CR1;
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i2cCR2= I2C_BASE->CR2;
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i2cISR= I2C_BASE->ISR;
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i2cHardware->state = i2cInitialized;
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}
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void i2cReset(i2c_t *i2cHardware)
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{
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RCC->APB1RSTR |= (1 << i2cBus_Rst_bitPos[i2cHardware->channelNo]);
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RCC->APB1RSTR &= ~(1 << i2cBus_Rst_bitPos[i2cHardware->channelNo]);
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}
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void i2cRead( i2c_t *i2cHardware,
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uint16_t *devAddress,
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uint8_t *registerAddress,
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uint8_t *data,
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uint8_t dataLenght)
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{
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i2cHardware->state = i2cBusy;
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switch(i2cHardware->mode)
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{
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case i2cModeMaster: // Implement for loops for more than one byte.
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i2cMasterRecieve(i2cHardware, devAddress, registerAddress, data);
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break;
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case i2cModeSlave:
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i2cSlaveRecieve(i2cHardware, devAddress, registerAddress, data);
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break;
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case i2cModeMultyMaster:
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// TO implement
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break;
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default:
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i2cThrowError(1);
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}
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}
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// this function still doesn't implment 10 bit oopeartion TODO
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void i2cMasterRecieve(i2c_t *i2cHardware, uint8_t devAddress, uint8_t registerAddress, uint8_t *data)
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{
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// Wait until no communication is ongoign
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while((I2C_BASE->ISR & (I2C_ISR_BUSY))==I2C_ISR_BUSY);
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i2cHardware->state = i2cRecieving;
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//Slave address
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I2C_BASE->CR2 |= 0x40 << 1; // The bit no 0 is not taken in concideration in 7bit mode
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//Read Mode
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I2C_BASE->CR2 &= ~I2C_CR2_RD_WRN;
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//Set Buffer size
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I2C_BASE->CR2 |= 1 << I2C_CR2_NBYTES_Pos;
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//Generate start condition
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I2C_BASE->CR2 |= I2C_CR2_START;
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//Wait until the start condition in generated.
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while(!(I2C_BASE->ISR & (I2C_ISR_BUSY)));
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//Check if the TX buffer is empty
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while(!(I2C_BASE->ISR & (I2C_ISR_TXE)));
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//Register to be sent
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I2C_BASE->TXDR |= 0xf0;
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while(!(I2C_BASE->ISR & (I2C_ISR_RXNE)));
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i2cCR1= I2C_BASE->CR1;
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i2cCR2= I2C_BASE->CR2;
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i2cISR= I2C_BASE->ISR;
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data = I2C_BASE->RXDR;
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}
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