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147 lines
3.3 KiB
147 lines
3.3 KiB
#include "spi.h"
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#define SPI_BASE ((SPI_TypeDef *)spiBase_Addr_List[spi_hw_ch])
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void spiReset(spiCH_t spi_hw_ch)
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{
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if(spiBus_No[spi_hw_ch] == 1) {
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RCC->APB1RSTR |= (1 << spiBus_Rst_bitPos[spi_hw_ch]);
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RCC->APB1RSTR &= ~(1 << spiBus_Rst_bitPos[spi_hw_ch]);
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return;
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}
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RCC->APB2RSTR |= (1 << spiBus_Rst_bitPos[spi_hw_ch]);
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RCC->APB2RSTR &= ~(1 << spiBus_Rst_bitPos[spi_hw_ch]);
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}
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void spiEnableBus(spiCH_t spi_hw_ch)
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{
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if(spiBus_No[spi_hw_ch] == 1) {
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RCC->APB1ENR |= (1 << spiBus_En_bitPos[spi_hw_ch]);
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return;
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}
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RCC->APB2ENR |= (1 << spiBus_En_bitPos[spi_hw_ch]);
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}
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void spiEnable(spiCH_t spi_hw_ch)
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{
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SPI_BASE->CR1 |= SPI_CR1_SPE;
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}
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void spiDissable(spiCH_t spi_hw_ch)
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{
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// TODO: implement p.768 procedure for dissabling
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//while(SPI_BASE->SR
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SPI_BASE->CR1 &= ~SPI_CR1_SPE;
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}
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void spiSetMode(spiCH_t spi_hw_ch, spi_mode_t mode)
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{
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SPI_BASE->CR1 &= ~(mode << SPI_CR1_MSTR_Pos);
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SPI_BASE->CR1 |= mode << SPI_CR1_MSTR_Pos;
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// TODO: find out if this is the correct place to set the SSOE bit
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SPI_BASE->CR2 &= ~SPI_CR2_SSOE;
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if(mode == SPI_MASTER) {
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SPI_BASE->CR2 |= SPI_CR2_SSOE;
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}
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}
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void spiSetPolarity(spiCH_t spi_hw_ch, spi_clkPol_t clkPol)
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{
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// reset
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SPI_BASE->CR1 &= ~SPI_CR1_CPOL;
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// set
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SPI_BASE->CR1 |= clkPol << SPI_CR1_CPOL_Pos;
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}
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void spiSetPhase(spiCH_t spi_hw_ch, spi_phase_t phase)
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{
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// reset
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SPI_BASE->CR1 &= ~(phase << SPI_CR1_CPHA_Pos);
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// set
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SPI_BASE->CR1 |= phase << SPI_CR1_CPHA_Pos;
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}
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void spiSetBitFrameLength(spiCH_t spi_hw_ch, spi_framel_t framel)
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{
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SPI_BASE->CR2 &= ~(SPI_CR2_FRXTH | SPI_CR2_DS);
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// using p.974 as example
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if(framel == SPI_FRAME_LENGTH_8BIT) {
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// set FIFO reception threshold to 8 bit
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SPI_BASE->CR2 |= SPI_CR2_FRXTH;
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// set transfer lwnght to 8 bit
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SPI_BASE->CR2 |= SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2;
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return;
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}
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SPI_BASE->CR2 |= SPI_CR2_DS;
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}
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void spiSetFrameFormat(spiCH_t spi_hw_ch, spi_framef_t framef)
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{
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// reset
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SPI_BASE->CR1 &= ~SPI_CR1_LSBFIRST;
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// set
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SPI_BASE->CR1 |= framef << SPI_CR1_LSBFIRST_Pos;
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}
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spi_framef_t spiGetFrameFormat(spiCH_t spi_hw_ch)
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{
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return (spi_framef_t)(SPI_BASE->CR1 & SPI_CR1_LSBFIRST) >> SPI_CR1_LSBFIRST_Pos;
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}
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void spiSetClockPrescaler(spiCH_t spi_hw_ch, uint32_t clkDiv)
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{
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// reset
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SPI_BASE->CR1 &= ~SPI_CR1_BR;
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// set
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SPI_BASE->CR1 |= (clkDiv << SPI_CR1_BR_Pos) & SPI_CR1_BR;
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}
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void spiSetComMode(spiCH_t spi_hw_ch, spi_comMode_t comMode)
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{
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// reset
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SPI_BASE->CR1 &= ~SPI_CR1_RXONLY;
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// set
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SPI_BASE->CR1 |= comMode << SPI_CR1_RXONLY_Pos;
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}
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void spiSetSoftwareSlaveManagement(spiCH_t spi_hw_ch, uint8_t logic)
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{
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SPI_BASE->CR1 &= ~SPI_CR1_SSM;
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if(logic){
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SPI_BASE->CR1 |= SPI_CR1_SSM;
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}
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}
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void spiSetInternalSlaveSelect(spiCH_t spi_hw_ch, uint8_t logic)
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{
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SPI_BASE->CR1 &= ~SPI_CR1_SSI;
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if(logic) {
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SPI_BASE->CR1 |= SPI_CR1_SSI;
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}
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}
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uint8_t spiTrx8BitPolling(spiCH_t spi_hw_ch, uint8_t tx_data)
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{
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// wait for BSY bit to Reset -> This will indicate that SPI is not busy in communication
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while (SPI_BASE->SR & SPI_SR_BSY);
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// from example code p.975 f
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// this masking must be done. otherwise 16bits frame will be used
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*(uint8_t*)&(SPI_BASE->DR) = tx_data;
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// Wait for RXNE to set -> This will indicate that the Rx buffer is not empty
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while (!(SPI_BASE->SR &SPI_SR_RXNE));
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// TODO: test read!
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return *(uint8_t*)&(SPI_BASE->DR);
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}
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