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278 lines
8.2 KiB
278 lines
8.2 KiB
/**
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**************************************************************************************************
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* @file hardwareDescription.h
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* @author Kerem Yollu & Edwin Koch
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* @date 19.12.2021
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* @version 1.0
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**************************************************************************************************
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* @brief This file contains all hardware specific definitions for STM32F042K6
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*
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* **Detailed Description :**
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* This Header file contains all the registers and their bit manipulation options.
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* All the extra Tables created here are to somplifly the main codes readability
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*
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* @todo
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* - 19.12.2021 : implement until it runs :)
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**************************************************************************************************
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*/
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#ifndef _hardwareDescription_H_
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#define _hardwareDescription_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "stm32f042x6.h"
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#include <stdint.h>
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#define PACKAGE_LQFP32 1
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#define MAX_USART_CHANNEL_COUNT 2
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#define MAX_I2C_CHANNEL_COUNT 1
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#define MAX_SPI_CHANNEL_COUNT 2
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#define MAX_I2S_CHANNEL_COUNT 2
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#define MAX_CAN_CHANNEL_COUNT 1
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#define MAX_TIMER_CHANNEL_COUNT 6
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#define MAX_N_PORTS_COUNT 3
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#define MAX_PORT_PINS_COUNT 16
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#define MAX_N_PIN_ALT_FUNC 8
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#define MAX_PORT_A_PIN_NO 15
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#define MAX_PORT_B_PIN_NO 15
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#define MAX_PORT_F_PIN_NO 1
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/*! Pin number typedef enum. It contains all the available pins */
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typedef enum
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{
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// NAME = BASE ADDR | PORT | PIN NO
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pinA0 = 0x00 | 0, /*!< Port: A Pin: 0 -> Port A Mask | Pin Mask */
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pinA1 = 0x00 | 1, /*!< Port: A Pin: 1 -> Port A Mask | Pin Mask */
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pinA2 = 0x00 | 2, /*!< Port: A Pin: 2 -> Port A Mask | Pin Mask */
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pinA3 = 0x00 | 3, /*!< Port: A Pin: 3 -> Port A Mask | Pin Mask */
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pinA4 = 0x00 | 4, /*!< Port: A Pin: 4 -> Port A Mask | Pin Mask */
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pinA5 = 0x00 | 5, /*!< Port: A Pin: 5 -> Port A Mask | Pin Mask */
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pinA6 = 0x00 | 6, /*!< Port: A Pin: 6 -> Port A Mask | Pin Mask */
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pinA7 = 0x00 | 7, /*!< Port: A Pin: 7 -> Port A Mask | Pin Mask */
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pinA8 = 0x00 | 8, /*!< Port: A Pin: 8 -> Port A Mask | Pin Mask */
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pinA9 = 0x00 | 9, /*!< Port: A Pin: 9 -> Port A Mask | Pin Mask */
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pinA10 = 0x00 | 10, /*!< Port: A Pin: 10 -> Port A Mask | Pin Mask */
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pinA11 = 0x00 | 11, /*!< Port: A Pin: 11 -> Port A Mask | Pin Mask */
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pinA12 = 0x00 | 12, /*!< Port: A Pin: 12 -> Port A Mask | Pin Mask */
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pinA13 = 0x00 | 13, /*!< Port: A Pin: 13 -> Port A Mask | Pin Mask */
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pinA14 = 0x00 | 14, /*!< Port: A Pin: 14 -> Port A Mask | Pin Mask */
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pinA15 = 0x00 | 15, /*!< Port: A Pin: 15 -> Port A Mask | Pin Mask */
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pinB0 = 0x10 | 0, /*!< Port: B Pin: 0 -> Port B Mask | Pin Mask */
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pinB1 = 0x10 | 1, /*!< Port: B Pin: 1 -> Port B Mask | Pin Mask */
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pinB3 = 0x10 | 3, /*!< Port: B Pin: 3 -> Port B Mask | Pin Mask */
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pinB4 = 0x10 | 4, /*!< Port: B Pin: 4 -> Port B Mask | Pin Mask */
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pinB5 = 0x10 | 5, /*!< Port: B Pin: 5 -> Port B Mask | Pin Mask */
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pinB6 = 0x10 | 6, /*!< Port: B Pin: 6 -> Port B Mask | Pin Mask */
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pinB7 = 0x10 | 7, /*!< Port: B Pin: 7 -> Port B Mask | Pin Mask */
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pinB8 = 0x10 | 8, /*!< Port: B Pin: 8 -> Port B Mask | Pin Mask */
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pinF0 = 0x20 | 0, /*!< Port: F Pin: 0 -> Port F Mask | Pin Mask */
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pinF1 = 0x20 | 1 /*!< Port: F Pin: 1 -> Port F Mask | Pin Mask */
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}pinNo_t;
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/*!List of all possible port base addresses. This is used for the funcionality of of pin.h*/
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static const uint32_t portBase_Addr_List[MAX_N_PORTS_COUNT] = {
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GPIOA_BASE, //!< Base address Port A
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GPIOB_BASE, //!< Base address Port B
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GPIOF_BASE //!< Base address Port F
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};
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/*! This is a bitmap list of all possible alternative functions for each pin.
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* 1means that there is an alternative function available and 0 for none. Tis is used
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* for the functionality in pin.h
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* */
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static const uint8_t altFunc_List[MAX_N_PORTS_COUNT][MAX_PORT_PINS_COUNT] = {
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{ // PORT A
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0b01110000, //PA0
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0b11110000, //PA1
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0b01110000, //PA2
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0b01110000, //PA3
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0b11111000, //PA4
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0b11110000, //PA5
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0b11110110, //PA6
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0b11111110, //PA7
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0b11111000, //PA8
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0b01111100, //PA9
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0b11111000, //PA10
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0b11111100, //PA11
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0b11111100, //PA12
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0b11100000, //PA13
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0b11000000, //PA14
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0b11110100 //PA15
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},
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{ // PORT B
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0b11110000, //PB0
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0b11110000, //PB1
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0b00010000, //PB2
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0b11110000, //PB3
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0b11110100, //PB4
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0b11110000, //PB5
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0b11110000, //PB6
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0b11110000, //PB7
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0b11111000, //PB8
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0b11111100, //PB9
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0b11110100, //PB10
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0b11100000, //PB11
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0b11100000, //PB12
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0b10100100, //PB13
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0b10100100, //PB14
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0b10100000 //PB15
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},
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{ // PORT F
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0b11000000, //PF0
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0b01000000, //PF1
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0b00000000, //N.A
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0b00000000, //N.A
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0b00000000, //N.A
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0b00000000, //N.A
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0b00000000, //N.A
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0b00000000, //N.A
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0b00000000, //N.A
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0b00000000, //N.A
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0b00000000, //N.A
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0b00000000, //N.A
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0b00000000, //N.A
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0b00000000, //N.A
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0b00000000, //N.A
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0b00000000 //N.A
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}
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};
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/*!
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* Enum for awailable timer DS Page: 12 (block diagaram) The order of the enums is very important
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* and should not be changed as it is used ofr table indexing
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* */
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typedef enum {
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timer_1, /*!< Advanced control 16-bit timer with PWM capability RM Page: 320 */
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timer_2, /*!< General purpose 32-bit timer RM Page: 393 */
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timer_3, /*!< General purpose 16-bit timer RM Page: 393 */
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timer_14, /*!< General purpose 16-bit timer RM Page: 459 */
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timer_16, /*!< General purpose 16-bit timer RM Page: 480 */
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timer_17 /*!< General purpose 16-bit timer RM Page: 480 */
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} timerNo_t;
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/*!
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* Enum for awailable clok sources RM Page: 95
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* */
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typedef enum {
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CLK_HSI, /*!< High speed internal */
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CLK_HSE, /*!< High speed external */
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CLK_LSI, /*!< Low speed internal */
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CLK_LSE /*!< Low speed External */
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}clkSources_t;
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/*!
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* Timer base addresslist of all available timers
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* */
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static const uint32_t timerBase_Addr_List[MAX_TIMER_CHANNEL_COUNT] = {
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TIM1_BASE, /*!< Timer 1 Base Address */
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TIM2_BASE, /*!< Timer 2 Base Address */
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TIM3_BASE, /*!< Timer 3 Base Address */
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TIM14_BASE, /*!< Timer 14 Base Address */
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TIM16_BASE, /*!< Timer 16 Base Address */
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TIM17_BASE /*!< Timer 17 Base Address */
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};
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/*!
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* RCC clock enabcke bit position for the given register
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* */
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static const uint8_t timerBus_En_bitPos[MAX_TIMER_CHANNEL_COUNT] = {
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RCC_APB2ENR_TIM1EN_Pos,
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RCC_APB1ENR_TIM2EN_Pos,
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RCC_APB1ENR_TIM3EN_Pos,
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RCC_APB1ENR_TIM14EN_Pos,
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RCC_APB2ENR_TIM16EN_Pos,
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RCC_APB2ENR_TIM17EN_Pos
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};
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/*!
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* RCC timer Reset Bit Position list
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* */
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static const uint8_t timerBus_Rst_bitPos[MAX_TIMER_CHANNEL_COUNT] = {
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RCC_APB2RSTR_TIM1RST_Pos,
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RCC_APB1RSTR_TIM2RST_Pos,
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RCC_APB1RSTR_TIM3RST_Pos,
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RCC_APB1RSTR_TIM14RST_Pos,
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RCC_APB2RSTR_TIM16RST_Pos,
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RCC_APB2RSTR_TIM17RST_Pos
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};
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/*!
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* RCC Bus number index list connected to the timer
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* */
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static const uint8_t timerBus_No[MAX_TIMER_CHANNEL_COUNT] = {
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2, /*!< timer 1 is connected to bus 2 */
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1, /*!< timer 2 is connected to bus 1 */
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1, /*!< timer 3 is connected to bus 1 */
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1, /*!< timer 14 is connected to bus 1 */
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2, /*!< timer 16 is connected to bus 2 */
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2 /*!< timer 17 is connected to bus 2 */
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};
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/*!
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* Timer Prescaler resolution list TO BE DELETED IF NOT NEEDED
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* */
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static const uint32_t timerRes_Prescaler[MAX_TIMER_CHANNEL_COUNT] = {
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0xFFFF, /*!< Timer 1 Prescaler Max Value */
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0xFFFF, /*!< Timer 2 Prescaler Max Value */
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0xFFFF, /*!< Timer 3 Prescaler Max Value */
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0xFFFF, /*!< Timer 14 Prescaler Max Value */
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0xFFFF, /*!< Timer 16 Prescaler Max Value */
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0xFFFF, /*!< Timer 17 Prescaler Max Value */
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};
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/*!
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* RCC Bus number index list connected to the SPI
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* */
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static const uint8_t spiBus_No[MAX_SPI_CHANNEL_COUNT] = {
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2, /*!< SPI 1 is connected to bus 2 */
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1 /*!< SPI 2 is connected to bus 1 */
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};
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/*!
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* RCC SPI clock enable bit position for the given register
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*
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*/
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static const uint8_t spiBus_En_bitPos[MAX_SPI_CHANNEL_COUNT] = {
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RCC_APB2ENR_SPI1EN_Pos,
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RCC_APB1ENR_SPI2EN_Pos
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};
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/*!
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* RCC SPI Reset Bit Position list
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* */
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static const uint8_t spiBus_Rst_bitPos[MAX_SPI_CHANNEL_COUNT] = {
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RCC_APB2RSTR_SPI1RST_Pos,
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RCC_APB1RSTR_SPI2RST_Pos
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};
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/**
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* Enumof available spi hardware channels
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*/
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typedef enum{
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SPI_CH_1,
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SPI_CH_2
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} spiCH_t;
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/**
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* SPI base address list
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*/
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static const uint32_t spiBase_Addr_List[MAX_SPI_CHANNEL_COUNT] = {
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SPI1_BASE,
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SPI2_BASE
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};
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#ifdef __cplusplus
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}
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#endif
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#endif // _hardwareDescription_H_
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