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101 lines
2.8 KiB
101 lines
2.8 KiB
#include"deviceSetup.h"
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#include "stm32f042x6.h"
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#define SET_BIT(REG, BIT) ((REG) |= (BIT))
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#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
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#define READ_BIT(REG, BIT) ((REG) & (BIT))
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#define CLEAR_REG(REG) ((REG) = (0x0))
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#define WRITE_REG(REG, VAL) ((REG) = (VAL))
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#define READ_REG(REG) ((REG))
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#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
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// FLASH->ACR = (((FLASH->ACR) & (~(FLASH_ACR_LATENCY))) | 0)
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#define SYS_CLK 8000000
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void setupInit()
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{
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setupBus();
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setupMemory();
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setupClock();
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setupPower();
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delayInitMs(SYS_CLK, 1000);
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}
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void setupClock()
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{
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uint8_t check = 1;
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/*Sets the clock source to internal clock*/
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RCC->CR |= RCC_CR_HSION;
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/* Wait till HSI is ready */
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while(check)
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{
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if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY))
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{
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check = 0;
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}
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}
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/**
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* @brief Set HSI Calibration trimming
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* @note Default value is 16, which, when added to the HSICAL value,
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* @param Value between Min_Data = 0x00 and Max_Data = 0x1F
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*/
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MODIFY_REG(RCC->CR, RCC_CR_HSITRIM_Msk, 16 << RCC_CR_HSITRIM_Pos) ;
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MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_CFGR_HPRE_DIV1);
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MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_CFGR_PPRE_DIV1);
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MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_HSI);
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/* Wait till System clock is ready */
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while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI){}
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}
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void setupBus()
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{
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volatile uint32_t tmpreg;
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/*Bit 0 SYSCFGCOMPEN: SYSCFG & COMP clock enable*/
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);
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/* Delay after an RCC peripheral clock enabling */
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);
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/*Bit 28 PWREN: Power interface clock enable*/
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SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
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/* Delay after an RCC peripheral clock enabling */
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tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
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(void)tmpreg;
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}
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void setupPower()
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{
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}
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void setupMemory()
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{
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/* Bits 2:0 LATENCY[2:0]: Latency
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* These bits represent the ratio of the SYSCLK (system clock) period to the Flash access time.
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* 000: Zero wait state, if SYSCLK ≤ 24 MHz
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* 001: One wait state, if 24 MHz < SYSCLK ≤ 48 MHz*/
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if(SYS_CLK <= 24000000)
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{
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FLASH->ACR = (((FLASH->ACR) & (~(FLASH_ACR_LATENCY_Msk))) | 0);
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while( ((FLASH->ACR) & (FLASH_ACR_LATENCY_Msk)) != 0){}
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}
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else
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{
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FLASH->ACR = (((FLASH->ACR) & (~(FLASH_ACR_LATENCY_Msk))) | 1);
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while( ((FLASH->ACR) & (FLASH_ACR_LATENCY_Msk)) != 1){}
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}
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}
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void delayInitMs(uint32_t clk, uint32_t ticks)
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{
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/* Configure the SysTick to have interrupt in 1ms time base */
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SysTick->LOAD = (uint32_t)((clk / ticks) - 1UL); /* set reload register */
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SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
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}
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