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#include "i2c.h"
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#include "usart.h"
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#include "delay.h"
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#define I2C_BASE ((I2C_TypeDef*)i2cBase_Addr_List[i2c_dev->channelNo])
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void i2c_hardware_enable(i2c_t *i2c_dev)
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{
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i2c_hardware_reset(i2c_dev);
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// Enables the i2c bus
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RCC->APB1ENR |= (1 << i2cBus_En_bitPos[i2c_dev->channelNo]);
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i2c_dev->hardwareState = i2c_hw_enabled;
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pinInit(pinA9);
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pinInit(pinA10);
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pinConfig(pinA9, alternate, openDrain, pullUp, fast);// I2C SCL
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pinConfig(pinA10, alternate, openDrain, pullUp, fast);// I2C CSA
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pinSetAlternate(pinA9, 4);
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pinSetAlternate(pinA10, 4);
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i2c_dev->hardwareState = i2c_hw_ready;
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}
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// Resets the I2C hardware using the reset registers,
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// This will init the device to it's defualt configuration established by STM
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void i2c_hardware_reset(i2c_t *i2c_dev)
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{
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RCC->APB1RSTR |= (1 << i2cBus_Rst_bitPos[i2c_dev->channelNo]);
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RCC->APB1RSTR &= ~(1 << i2cBus_Rst_bitPos[i2c_dev->channelNo]);
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i2c_dev->hardwareState = i2c_hw_reset;
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}
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//enables periferal
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void i2c_periferal_enable(i2c_t *i2c_dev)
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{
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I2C_BASE->CR1 |= I2C_CR1_PE;
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i2c_dev->periferalState = i2c_perif_enabled;
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//Wait untill periferal is ready for communication
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while(!i2c_is_perif_ready(i2c_dev));
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i2c_dev->periferalState = i2c_perif_ready;
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}
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void i2c_periferal_disable(i2c_t *i2c_dev)
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{
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I2C_BASE->CR1 &= ~I2C_CR1_PE;
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i2c_dev->periferalState = i2c_perif_disabled;
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}
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void i2c_set_mode(i2c_t *i2c_dev, i2c_mode_t mode)
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{
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//This device will set himself automatically to master mode
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if(i2c_dev->mode == i2c_mode_master)
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{
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}
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else if(i2c_dev->mode == i2c_mode_slave)
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{
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// to be written.
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}
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}
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void i2c_set_address_lenght(i2c_t *i2c_dev, i2c_address_size_t size)
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{
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if(i2c_dev->mode == i2c_mode_master)
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{
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if(i2c_dev->addressSize == i2c_address_size_10b)
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{
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I2C_BASE->CR2 |= I2C_CR2_ADD10; // 10 Bit addressing
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I2C_BASE->CR2 &= ~I2C_CR2_HEAD10R; // 7 Bit header read turned on DEFAULT
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}
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else
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{
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I2C_BASE->CR2 &= ~I2C_CR2_ADD10; // 7 Bit addressing DEFAULT
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I2C_BASE->CR2 |= I2C_CR2_HEAD10R; // 7 Bit header read turned off DEFAULT
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}
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}
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else if(i2c_dev->mode == i2c_mode_slave)
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{
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// to be written.
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}
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}
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void i2c_set_clk_stretch(i2c_t *i2c_dev, i2c_clk_stretching_t stretching)
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{
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if(i2c_dev->stretching == i2c_clk_stretching_enable)
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{
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I2C_BASE->CR1 &=~ I2C_CR1_NOSTRETCH;
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}
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else if(i2c_dev->stretching == i2c_clk_stretching_disable)
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{
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I2C_BASE->CR1 |= I2C_CR1_NOSTRETCH;
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}
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}
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void i2c_set_clk_speed(i2c_t *i2c_dev, i2c_clk_speed_t speed)
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{
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switch(speed)
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{
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case i2c_clk_speed_standart:
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I2C_BASE->TIMINGR = 0x2000090E;
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break;
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case i2c_clk_speed_fast:
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break;
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case i2c_clk_speed_fastPlus:
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break;
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case i2c_clk_speed_hightSpeed:
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break;
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case i2c_clk_speed_ultraFast:
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break;
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default:
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break;
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}
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}
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void i2c_set_filter(i2c_t *i2c_dev, uint8_t enable)
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{
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if(enable)
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{
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//Anlalog filter is on
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I2C_BASE->CR1 &= ~I2C_CR1_ANFOFF;
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}
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else
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{
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//Anlalog filter is off
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I2C_BASE->CR1 |= I2C_CR1_ANFOFF;
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}
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}
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/**************************************************************************************************
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I2C Hardware functions
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***************************************************************************************************/
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void i2c_send_start(i2c_t *i2c_dev)
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{
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I2C_BASE->CR2 &=~ I2C_CR2_STOP;
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I2C_BASE->CR2 |= I2C_CR2_START;
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//Wait until the start condition in generated.
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//Bit 15BUSY: Bus busy
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//This flag indicates that a communication is in progress on the bus. It is set by hardware when a
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//START condition is detected. It is cleared by hardware when a Stop condition is detected, or
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//when PE=0.
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while(!(I2C_BASE->ISR & (I2C_ISR_BUSY)));
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i2c_dev->hardwareState = i2c_hw_sent_start;
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}
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void i2c_send_stop(i2c_t *i2c_dev)
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{
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// Send stop command
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I2C_BASE->CR2 |= I2C_CR2_STOP;
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I2C_BASE->CR2 &=~ I2C_CR2_START;
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i2c_dev->hardwareState = i2c_hw_sent_stop;
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}
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uint8_t i2c_is_perif_ready(i2c_t *i2c_dev)
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{
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if((I2C_BASE->ISR & (I2C_ISR_BUSY))!=I2C_ISR_BUSY)
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{
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i2c_dev->periferalState = i2c_perif_ready;
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return 1;
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}
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return 0;
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}
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void i2c_set_transfer_counter(i2c_t *i2c_dev, uint8_t count)
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{
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I2C_BASE->CR2 &= ~(0xFF << I2C_CR2_NBYTES_Pos);
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I2C_BASE->CR2 |= (count << I2C_CR2_NBYTES_Pos);
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}
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uint8_t i2c_get_transfer_counter(i2c_t *i2c_dev)
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{
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return (I2C_BASE->CR2 & I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos;
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}
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void i2c_init_write_command(i2c_t *i2c_dev)
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{
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I2C_BASE->CR2 &= ~I2C_CR2_RD_WRN;
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i2c_dev->hardwareState = i2c_hw_send_write;
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}
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void i2c_init_read_command(i2c_t *i2c_dev)
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{
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I2C_BASE->CR2 |= I2C_CR2_RD_WRN;
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i2c_dev->hardwareState =i2c_hw_send_read;
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}
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uint8_t i2c_send_address_for_write(i2c_t *i2c_dev, uint16_t *slaveAddress)
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{
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//Automatic end mode (master mode) disabled Enablede as default
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I2C_BASE->CR2 &= ~I2C_CR2_AUTOEND;
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// On This chip this shoudl be done before the start condition
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i2c_init_write_command(i2c_dev);
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// The Slave addrress is automatically place on the output buffer (must be done before the start condition)
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I2C_BASE->CR2 |= (*slaveAddress & 0xff) << 1; // The bit no 0 is not taken in concideration in 7bit mode
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// This device places the salve address automaticaly in the output buffer before sending the star condition
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i2c_send_start(i2c_dev);
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while(i2c_is_output_buffer_full(i2c_dev));
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return 1;
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}
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uint8_t i2c_send_address_for_read(i2c_t *i2c_dev, uint16_t *slaveAddress)
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{
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// On This chip this shoudl be done before the start condition
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i2c_init_read_command(i2c_dev);
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// The Slave addrress is automatically place on the output buffer (must be done before the start condition)
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I2C_BASE->CR2 |= (*slaveAddress & 0xff) << 1; // The bit no 0 is not taken in concideration in 7bit mode
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// This device places the salve address automaticaly in the output buffer before sending the star condition
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i2c_send_start(i2c_dev);
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while(i2c_is_output_buffer_full(i2c_dev));
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return 1;
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}
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uint8_t i2c_is_output_buffer_full(i2c_t *i2c_dev)
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{
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/*
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Bit 0 TXE: Transmit data register empty (transmitters)
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This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next
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data to be sent is written in the I2C_TXDR register.
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This bit can be written to ‘1’ by software in order to flush the transmit data register I2C_TXDR.
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Note: This bit is set by hardware when PE=0.
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*/
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if(I2C_BASE->ISR & I2C_ISR_TXE)
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{
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i2c_dev->hardwareState = i2c_hw_out_buff_empty;
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return 0;
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}
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else
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{
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i2c_dev->hardwareState = i2c_hw_out_buff_full;
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return 1;
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}
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}
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uint8_t i2c_is_txis(i2c_t *i2c_dev)
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{
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if(I2C_BASE->ISR & I2C_ISR_TXIS)
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{
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i2c_dev->hardwareState = i2c_hw_out_buff_empty;
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return 0;
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}
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else
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{
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i2c_dev->hardwareState = i2c_hw_out_buff_full;
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return 1;
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}
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}
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void i2c_send_reg_address(i2c_t *i2c_dev, uint8_t *registerAddress)
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{
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I2C_BASE->TXDR = *registerAddress;
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i2c_dev->hardwareState = i2c_hw_out_buff_full;
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while(i2c_is_output_buffer_full(i2c_dev));
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}
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void i2c_send_data(i2c_t *i2c_dev, uint8_t *data)
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{
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I2C_BASE->TXDR = *data;
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i2c_dev->hardwareState = i2c_hw_out_buff_full;
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while(i2c_is_output_buffer_full(i2c_dev));
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}
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uint8_t i2c_is_transfer_complete(i2c_t *i2c_dev)
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{
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/*
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TC: Transfer Complete (master mode)
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This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been
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transferred. It is cleared by software when START bit or STOP bit is set.
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Note: This bit is cleared by hardware when PE=0.
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*/
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if(I2C_BASE->ISR & I2C_ISR_TC)
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{
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return 1;
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}
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else
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{
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return 0;
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}
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}
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uint8_t i2c_is_input_buffer_full(i2c_t *i2c_dev)
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{
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if(I2C_BASE->ISR & I2C_ISR_RXNE)
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{
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i2c_dev->hardwareState = i2c_hw_in_buff_full;
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return 1;
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}
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else
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{
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i2c_dev->hardwareState = i2c_hw_in_buff_empty;
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return 0;
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}
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}
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void i2c_get_input_register(i2c_t *i2c_dev, uint8_t *data)
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{
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while(!i2c_is_input_buffer_full(i2c_dev));
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*data = I2C_BASE->RXDR;
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while(!i2c_is_transfer_complete(i2c_dev));
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}
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void i2c_send_nack(i2c_t *i2c_dev)
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{
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if(i2c_dev->mode == i2c_mode_master)
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{
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//IN master mode this ic geretes NACK's otomatically
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i2c_dev->hardwareState = i2c_hw_sent_nack;
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}
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else if(i2c_dev->mode == i2c_mode_slave)
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{
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// to be written.
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}
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}
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uint8_t i2c_check_nack(i2c_t *i2c_dev)
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{
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delayMs(2);
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return(I2C_BASE->ISR & I2C_ISR_NACKF);
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}
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void i2c_set_address(i2c_t *i2c_dev, uint16_t address){}
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void i2c_set_address_second(i2c_t *i2c_dev, uint16_t address){}
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