sound impairement test simulations

master
Kerem Yollu 3 years ago
parent dba4201c3d
commit d2b3fa21fb

@ -1,23 +1,56 @@
Circuit: * C:\keyterm\git\amplifier_6c\03_lm3886_amp\06_simulation\Active_balanced_reciever.asc
WARNING: Less than two connections to node AMP_OUT_SUPER. This node is used by R17.
Direct Newton iteration for .op point succeeded.
Direct Newton iteration failed to find .op point. (Use ".option noopiter" to skip.)
Starting Gmin stepping
Gmin = 10
Gmin = 1.07374
vernier = 0.5
vernier = 0.25
vernier = 0.125
vernier = 0.0625
Gmin = 1.08884
vernier = 0.03125
vernier = 0.015625
Gmin = 1.03122
vernier = 0.0078125
vernier = 0.0104167
vernier = 0.00520833
Gmin = 1.01724
vernier = 0.00260417
vernier = 0.00347222
Gmin = 1.01042
vernier = 0.00173611
vernier = 0.00231481
vernier = 0.00115741
Gmin = 1.00852
vernier = 0.00154321
vernier = 0.000771604
Gmin = 1.00667
vernier = 0.00102881
vernier = 0.000514403
vernier = 0.00068587
Gmin = 1.00542
vernier = 0.000514403
vernier = 0.00068587
vernier = 0.000514402
Gmin = 1.00461
Gmin = 0
Gmin stepping failed
Date: Mon Oct 10 14:07:26 2022
Total elapsed time: 2.248 seconds.
tnom = 27
temp = 27
method = modified trap
totiter = 149655
traniter = 149605
tranpoints = 28700
accept = 21155
rejected = 7545
matrix size = 209
fillins = 171
solver = Normal
Thread vector: 8.2/5.0[6] 4.6/2.2[6] 1.2/0.9[6] 0.7/1.1[1] 2592/500
Matrix Compiler1: 17.87 KB object code size 4.3/2.0/[0.9]
Matrix Compiler2: 20.39 KB object code size 2.1/3.2/[0.8]
Starting source stepping with srcstepmethod=0
Source Step = 3.0303%
Source Step = 33.3333%
Source Step = 63.6364%
Source Step = 93.9394%
Source stepping succeeded in finding the operating point.
.step drive_voltage=0
Heightened Def Con from 0.00199975 to 0.00199975
Heightened Def Con from 0.00199975 to 0.00199975
Heightened Def Con from 0.00199975 to 0.00199975
Heightened Def Con from 0.00399975 to 0.00399975
.step drive_voltage=0.5
.step drive_voltage=1
.step drive_voltage=1.5
.step drive_voltage=2

@ -0,0 +1,134 @@
$ 1 0.000005 382.76258214399064 72 5 43 5e-11
409 256 160 400 160 1 0.6 -14.339204308548627 0.023100000000000002 0
r 144 144 256 144 0 20000
r 160 176 240 176 0 20000
r 240 256 240 336 0 22000
r 272 48 336 48 0 18000
w 240 256 240 176 0
w 256 176 240 176 0
v -176 208 -176 128 0 0 40 15 0 0 0.5
g -128 240 -128 256 0 0
w -128 208 -128 240 0
207 -176 320 -176 352 4 -15
g 80 304 80 320 0 0
g 0 256 0 272 0 0
g 240 352 240 368 0 0
v -176 304 -176 224 0 0 40 15 0 0 0.5
w 240 336 240 352 0
w -176 304 -176 320 0
w -176 128 -176 112 0
w -176 208 -176 224 0
w -176 208 -128 208 0
w 144 144 0 144 0
w 160 176 80 176 0
w 256 144 256 48 0
207 320 112 320 80 4 \p15
207 320 208 320 240 4 -15
w 320 192 320 208 0
w 320 112 320 128 0
v 0 160 0 240 0 1 1000 1.7 0 0 0.5
v 80 208 80 288 0 1 1000 1.7 0 0 0.5
w 0 144 0 160 0
w 80 176 80 208 0
w 80 288 80 304 0
w 0 240 0 256 0
409 752 128 896 128 1 0.6 -14.352600704884347 0.023100000000000002 0
409 752 416 896 416 1 0.6 -14.383413640703308 0.023100000000000002 0
207 816 80 816 48 4 \p15
207 816 368 816 336 4 \p15
207 816 464 816 496 4 -15
207 816 176 816 208 4 -15
w 816 368 816 384 0
w 816 448 816 464 0
w 816 160 816 176 0
w 816 80 816 96 0
w 896 128 896 32 0
w 896 32 752 32 0
w 752 32 752 112 0
w 896 416 896 304 0
w 752 304 752 400 0
r 784 304 848 304 0 10000
w 896 304 848 304 0
w 784 304 752 304 0
r 752 256 752 192 0 10000
w 752 288 752 304 0
w 752 192 752 144 0
g 752 464 752 480 0 0
w 752 256 752 288 0
d 912 128 960 128 2 1N4148
d 912 304 960 304 2 1N4148
w 912 128 896 128 0
c 960 336 960 384 0 4.7000000000000004e-8 0.559755635439749 0.001
g 960 400 960 416 0 0
r 1024 304 1088 304 0 10000
409 560 144 704 144 1 0.6 -14.350256890819471 0.023100000000000002 0
r 480 176 480 240 0 100000
g 480 256 480 272 0 0
w 400 160 416 160 0
w 464 160 480 160 0
w 480 160 480 176 0
w 480 240 480 256 0
207 624 96 624 64 4 \p15
207 624 192 624 224 4 -15
w 624 112 624 96 0
w 624 176 624 192 0
w 544 128 544 48 0
r 560 48 608 48 0 10000
r 544 208 544 272 0 1000
c 544 288 544 336 0 0.000047 0.0016309221695480556 0.001
g 544 352 544 368 0 0
w 544 336 544 352 0
g 1136 336 1136 352 0 0
w 1136 320 1136 336 0
162 1136 224 1136 272 2 default-led 1 0 0 0.02
w 1136 272 1136 288 0
r 1136 144 1136 208 0 2200
w 1136 208 1136 224 0
207 1136 128 1136 96 4 \p15
w 1136 128 1136 144 0
w 416 48 400 48 0
w 272 48 256 48 0
w 544 48 560 48 0
w 704 48 704 144 0
w 480 160 560 160 0
w 960 384 960 400 0
w 544 272 544 288 0
w 752 464 752 432 0
w 544 128 560 128 0
w 544 128 544 208 0
t 1104 304 1136 304 0 1 -13.677953589087766 0.5597307493250995 100 spice-default
w 1104 304 1088 304 0
w 896 304 912 304 0
207 -176 112 -176 80 4 \p15
w 1024 304 992 304 0
w 960 128 960 304 0
w 960 304 960 336 0
w 960 304 992 304 0
w 704 144 752 144 0
174 336 48 384 80 1 10000 0.401 Resistance
w 416 48 416 160 0
w 416 160 464 160 0
w 416 160 368 80 0
174 640 48 688 80 1 100000 0.5 Resistance
w 672 80 640 48 0
w 608 48 640 48 0
w 544 -256 544 -208 0
w 704 -256 704 -208 0
w 608 -208 640 -208 0
w 672 -176 640 -208 0
174 640 -208 688 -176 1 100000 0.49010000000000004 Resistance
w 704 -208 704 -112 0
w 544 -208 560 -208 0
r 560 -208 608 -208 0 10000
w 288 -208 288 -256 0
w 448 -256 448 -208 0
w 448 -96 400 -176 0
w 448 -208 448 -96 0
174 368 -208 416 -176 1 10000 0.401 Resistance
w 304 -208 288 -208 0
w 448 -208 432 -208 0
r 304 -208 368 -208 0 18000
216 288 -256 448 -256 0 0.01
216 544 -256 704 -256 0 0.01
o 83 2 0 4098 0.009765625 0.1 0 2 83 3
38 28 F1 0 1 2 -1 Max\sVoltage

@ -0,0 +1,272 @@
Version 4
SHEET 1 2912 2100
WIRE -752 896 -752 880
WIRE -416 960 -416 944
WIRE -752 992 -752 976
WIRE -656 992 -752 992
WIRE 432 1008 416 1008
WIRE 560 1008 512 1008
WIRE 640 1008 560 1008
WIRE -752 1024 -752 992
WIRE 784 1024 784 1008
WIRE 784 1024 768 1024
WIRE -656 1040 -656 992
WIRE 640 1040 640 1008
WIRE 688 1040 640 1040
WIRE 1344 1040 1344 1024
WIRE 1344 1040 1328 1040
WIRE -416 1056 -416 1040
WIRE 864 1056 864 896
WIRE 864 1056 768 1056
WIRE 944 1056 864 1056
WIRE 1056 1056 1008 1056
WIRE 1248 1056 1056 1056
WIRE 1744 1056 1744 1040
WIRE 1744 1056 1728 1056
WIRE 2336 1056 2336 1040
WIRE 688 1072 640 1072
WIRE 1424 1072 1328 1072
WIRE 1472 1072 1472 896
WIRE 1472 1072 1424 1072
WIRE 1536 1072 1472 1072
WIRE 1648 1072 1536 1072
WIRE 784 1088 768 1088
WIRE 1248 1088 1168 1088
WIRE 1888 1088 1728 1088
WIRE 1920 1088 1888 1088
WIRE 2112 1088 1984 1088
WIRE 432 1104 416 1104
WIRE 608 1104 512 1104
WIRE 640 1104 640 1072
WIRE 640 1104 608 1104
WIRE 784 1104 784 1088
WIRE 1344 1104 1328 1104
WIRE 1648 1104 1584 1104
WIRE -752 1120 -752 1104
WIRE 1344 1120 1344 1104
WIRE 1744 1120 1728 1120
WIRE 1744 1136 1744 1120
WIRE 1536 1152 1536 1072
WIRE 2336 1152 2336 1136
WIRE 2432 1152 2336 1152
WIRE 2544 1152 2512 1152
WIRE 2544 1184 2544 1152
WIRE 1584 1200 1584 1104
WIRE 1888 1200 1888 1088
WIRE 1888 1200 1584 1200
WIRE 608 1248 608 1104
WIRE 624 1248 608 1248
WIRE 864 1248 864 1056
WIRE 864 1248 704 1248
WIRE -752 1264 -752 1248
WIRE -416 1264 -416 1248
WIRE 1168 1264 1168 1088
WIRE 1184 1264 1168 1264
WIRE 1424 1264 1424 1072
WIRE 1424 1264 1264 1264
WIRE 2336 1280 2336 1152
WIRE 1744 1296 1744 1280
WIRE 1744 1296 1728 1296
WIRE 560 1312 560 1008
WIRE 1648 1312 1488 1312
WIRE 1056 1328 1056 1056
WIRE 1168 1328 1168 1264
WIRE 1888 1328 1728 1328
WIRE 1920 1328 1888 1328
WIRE 2112 1328 2112 1088
WIRE 2112 1328 1984 1328
WIRE 2160 1328 2112 1328
WIRE 2256 1328 2256 896
WIRE 2256 1328 2240 1328
WIRE 2272 1328 2256 1328
WIRE 1536 1344 1536 1232
WIRE 1648 1344 1536 1344
WIRE -416 1360 -416 1344
WIRE 1744 1360 1728 1360
WIRE 2112 1360 2112 1328
WIRE 2112 1360 2048 1360
WIRE 1744 1376 1744 1360
WIRE -752 1392 -752 1344
WIRE 2112 1392 2112 1360
WIRE 1168 1440 1168 1408
WIRE 1536 1456 1536 1344
WIRE 1776 1456 1536 1456
WIRE 1888 1456 1888 1328
WIRE 1888 1456 1856 1456
WIRE 2112 1472 2112 1456
WIRE 2112 1472 2048 1472
WIRE -512 1520 -512 1504
WIRE -672 1536 -672 1520
WIRE 560 1536 560 1392
WIRE 1056 1536 1056 1408
WIRE 1168 1536 1168 1504
WIRE 1488 1536 1488 1312
WIRE 2112 1536 2112 1472
WIRE 2336 1536 2336 1376
WIRE -512 1616 -512 1600
WIRE -672 1632 -672 1616
FLAG -656 1040 0
FLAG -752 880 +15
FLAG -752 1120 -15
FLAG 784 1008 +15
FLAG 784 1104 -15
FLAG 560 1536 0
FLAG 1344 1024 +15
FLAG 1344 1120 -15
FLAG 1056 1536 0
FLAG 1168 1536 0
FLAG -416 1360 0
FLAG -416 1056 0
FLAG -416 944 SIN_IN
FLAG -416 1248 SIN_REF
FLAG 864 896 SIM_FS
FLAG 1744 1040 +15
FLAG 1744 1136 -15
FLAG 1744 1280 +15
FLAG 1744 1376 -15
FLAG 1488 1536 0
FLAG 2112 1536 0
FLAG 2336 1040 +15
FLAG 2336 1536 0
FLAG -752 1248 Drive
FLAG -752 1392 0
FLAG 1472 896 SIM_SS
FLAG 2256 896 SIM_DRIVE
FLAG -672 1632 0
FLAG -512 1616 0
FLAG -512 1504 LIN_IN
FLAG -672 1520 LIN_REF
FLAG 2544 1184 0
FLAG 416 1008 SIN_IN
FLAG 416 1104 SIN_REF
SYMBOL voltage -752 880 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 15v
SYMBOL voltage -752 1008 R0
SYMATTR InstName V4
SYMATTR Value 15v
SYMBOL AutoGenerated\\AD825 720 1056 R0
SYMATTR InstName U7
SYMBOL res 528 992 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R21
SYMATTR Value 20k
SYMBOL res 528 1088 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R22
SYMATTR Value 20k
SYMBOL res 544 1296 R0
SYMATTR InstName R23
SYMATTR Value 22k
SYMBOL res 720 1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R24
SYMATTR Value 22.1k
SYMBOL res 896 1344 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R25
SYMATTR Value {VR1}
SYMBOL cap 1008 1040 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 35 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1ľf
SYMBOL AutoGenerated\\AD825 1280 1072 R0
SYMATTR InstName U8
SYMBOL res 1280 1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R26
SYMATTR Value 61k
SYMBOL res 1424 1392 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 53 60 VTop 2
SYMATTR InstName R27
SYMATTR Value {VR2}
SYMBOL res 1040 1312 R0
SYMATTR InstName R28
SYMATTR Value 100k
SYMBOL res 1152 1312 R0
SYMATTR InstName R29
SYMATTR Value 1k
SYMBOL cap 1152 1440 R0
SYMATTR InstName C4
SYMATTR Value 47ľ
SYMBOL voltage -416 944 R0
WINDOW 123 24 44 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName IN_SINUS
SYMATTR Value SINE(0 {sig_diff} {freq} {delay})
SYMBOL voltage -416 1248 R0
WINDOW 123 24 44 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName OUT_SINUS
SYMATTR Value SINE(0 1.7 {freq} {delay})
SYMBOL AutoGenerated\\AD825 1680 1088 R0
SYMATTR InstName U9
SYMBOL AutoGenerated\\AD825 1680 1328 R0
SYMATTR InstName U10
SYMBOL res 1872 1440 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R30
SYMATTR Value 10k
SYMBOL res 1552 1248 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R31
SYMATTR Value 10k
SYMBOL diode 1920 1104 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL diode 1920 1344 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value 1N4148
SYMBOL cap 2096 1392 R0
SYMATTR InstName C3
SYMATTR Value 47n
SYMBOL res 2256 1312 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R32
SYMATTR Value 10k
SYMBOL npn 2272 1280 R0
SYMATTR InstName Q1
SYMATTR Value BC547C
SYMBOL res 2320 1040 R0
SYMATTR InstName R33
SYMATTR Value 100k
SYMBOL voltage -752 1248 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value {sim_drv}
SYMBOL voltage -672 1520 R0
WINDOW 123 24 44 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName LIN_REF
SYMATTR Value 1.7
SYMBOL voltage -512 1504 R0
WINDOW 123 24 44 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName LIN_IN
SYMATTR Value PULSE(1.7 {start_v} {delay} 15us 15us 300us 0 1)
SYMBOL res 2528 1136 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 20k
TEXT 368 840 Left 2 !.tran 0 5ms 0 0.001
TEXT 360 744 Left 2 !.param VR1=1k VR2=100k sim_drv=1.2v freq=1k start_v=1.62 stop_v=1.79 delay=0.3m
TEXT 360 776 Left 2 ;.step param drive_voltage 0 5 0.5
TEXT 360 808 Left 2 !.param sig_diff=1.707

@ -0,0 +1,79 @@
Circuit: * C:\keyterm\git\amplifier_6c\03_lm3886_amp\06_simulation\sound_impairment_monitor.asc
WARNING: Specified period is not longer than the sum of Trise, Tfall, and Ton for v§lin_in. Increasing period to 0.00033
WARNING: Node NC_02 is floating.
WARNING: Node NC_04 is floating.
WARNING: Less than two connections to node NC_01. This node is used by R25.
WARNING: Less than two connections to node NC_02. This node is used by R25.
WARNING: Less than two connections to node NC_03. This node is used by R27.
WARNING: Less than two connections to node NC_04. This node is used by R27.
WARNING: Less than two connections to node DRIVE. This node is used by V2.
WARNING: Less than two connections to node LIN_REF. This node is used by V§LIN_REF.
WARNING: Less than two connections to node LIN_IN. This node is used by V§LIN_IN.
Direct Newton iteration failed to find .op point. (Use ".option noopiter" to skip.)
Starting Gmin stepping
Gmin = 10
Gmin = 1.07374
vernier = 0.5
vernier = 0.25
vernier = 0.125
vernier = 0.0625
Gmin = 1.08884
vernier = 0.03125
vernier = 0.015625
Gmin = 1.03122
vernier = 0.0078125
vernier = 0.0104167
vernier = 0.00520833
Gmin = 1.01724
vernier = 0.00260417
vernier = 0.00347222
Gmin = 1.01042
vernier = 0.00173611
vernier = 0.00231481
vernier = 0.00115741
Gmin = 1.00852
vernier = 0.00154321
vernier = 0.000771604
Gmin = 1.00667
vernier = 0.00102881
vernier = 0.000514403
vernier = 0.00068587
Gmin = 1.00542
vernier = 0.000514403
vernier = 0.00068587
vernier = 0.000514402
Gmin = 1.00461
Gmin = 0
Gmin stepping failed
Starting source stepping with srcstepmethod=0
Source Step = 3.0303%
Source Step = 33.3333%
Source Step = 63.6364%
Source Step = 93.9394%
Source stepping succeeded in finding the operating point.
Heightened Def Con from 0.000800149 to 0.000800149
Heightened Def Con from 0.000800149 to 0.000800149
Heightened Def Con from 0.000800149 to 0.000800151
Date: Wed Oct 12 15:54:45 2022
Total elapsed time: 0.844 seconds.
tnom = 27
temp = 27
method = modified trap
totiter = 15002
traniter = 9179
tranpoints = 1715
accept = 1263
rejected = 455
matrix size = 160
fillins = 210
solver = Normal
Thread vector: 5.0/3.9[4] 4.3/2.6[4] 1.4/1.3[1] 0.5/0.8[1] 2592/500
Matrix Compiler1: 17.00 KB object code size 4.2/2.3/[0.9]
Matrix Compiler2: 16.39 KB object code size 1.8/2.3/[0.5]
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